SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

This discloser concerns a semiconductor device including an insulation layer; a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at both sides of the floating body region; gate insulation films provided on both side surfaces of the floating body region; gate electrodes provided on both side surfaces of the floating body region via the gate insulation films; and a source electrode and a drain electrode respectively contacting with the upper surface of the source region and the drain region, wherein in the cross section of the FIN-type semiconductor layer in parallel with the surface of the insulation layer, a thickness of the FIN-type semiconductor layer in the floating body region is smaller than a thickness of the FIN-type semiconductor layer in the source and the drain regions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a cross-sectional view and a top plan view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

FIGS. 2A and 2B are a cross-sectional view and a top plan view showing a method of manufacturing a semiconductor memory device following FIGS. 1A and 1B;

FIGS. 3A and 3B are a cross-sectional view and a top plan view showing a method of manufacturing a semiconductor memory device following FIGS. 2A and 2B;

FIGS. 4A and 4B are a cross-sectional view and a top plan view showing a method of manufacturing a semiconductor memory device following FIGS. 3A and 3B;

FIGS. 5A and 5B are a cross-sectional view and a top plan view showing a method of manufacturing a semiconductor memory device following FIGS. 4A and 4B;

FIG. 6 is a top plan view showing a method of manufacturing a semiconductor memory device following FIG. 5A;

FIG. 7 is a cross-sectional view of the configuration shown in FIG. 6 cut along a line 7-7;

FIG. 8 is a cross-sectional view of the configuration shown in FIG. 6 cut along a line 8-8;

FIG. 9 is a top plan view showing a method of manufacturing a semiconductor memory device following FIG. 6;

FIG. 10 is a top plan view showing a method of manufacturing a semiconductor memory device following FIG. 9;

FIG. 11 is a cross-sectional view of the configuration shown in FIG. 10 along a line 10-10; and

FIG. 12 is a cross-sectional view of the configuration shown in FIG. 11 along a line 11-11.

Claims

1. A semiconductor device comprising: an insulation layer;a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at both sides of the floating body region;gate insulation films provided on both side surfaces of the floating body region;gate electrodes provided on both side surfaces of the floating body region via the gate insulation films; anda source electrode and a drain electrode respectively contacting with the upper surface of the source region and the drain region, wherein in the cross section of the FIN-type semiconductor layer in parallel with the surface of the insulation layer, a thickness of the FIN-type semiconductor layer in the floating body region is smaller than a thickness of the FIN-type semiconductor layer in the source and the drain regions.

2. The semiconductor device according to claim 1 further comprising: protection films provided on side surfaces of the source and the drain regions, wherein thicknesses of the protection films are larger than thicknesses of the gate insulation films.

3. The semiconductor device according to claim 1, wherein the semiconductor device stores binary data on the basis of a number of charges stored in the floating body region.

4. The semiconductor device according to claim 1, wherein the semiconductor device is an FBC memory device having the FIN-type semiconductor layer as a part of a memory cell.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a fully-depleted type FBC memory device having the FIN-type semiconductor layer as a part of a memory cell.

6. The semiconductor device according to claim 1, wherein the source region and the drain region are formed by an N-type semiconductor.

7. A method of manufacturing a semiconductor memory device which includes a FIN-type semiconductor layer provided on an insulation layer and including a floating body region in an electrically floating state and including a source and a drain regions at both sides of the floating body region respectively, the method comprising: preparing a substrate having a semiconductor layer provided on the insulation layer;a first etching process to remove a semiconductor layer between the adjacent source and drain regions of the semiconductor layer; anda second etching process to remove a semiconductor layer between the adjacent floating body regions of the semiconductor layer.

8. The method of manufacturing a semiconductor memory device according to claim 7, wherein a distance between the source and drain regions to be etched in the first etching process is different from a distance between the floating body regions to be etched in the second etching process.

9. The method of manufacturing a semiconductor memory device according to claim 7, wherein a distance between the source and drain regions to be etched in the first etching process is smaller than a distance between the floating body regions to be etched in the second etching process.

10. The method of manufacturing a semiconductor memory device according to claim 7, the method further comprising: forming protection films on the side surfaces of the source and drain regions formed in the first etching process, after the first etching process;implanting impurities for source and drain layers into the side surface of the source and drain regions by using oblique implantation; andforming the gate insulation films on the side surfaces of the floating body region formed in the second etching process, after the second etching.

11. The method of manufacturing a semiconductor memory device according to claim 10, wherein the protection films are thicker than the gate insulation films.

12. The method of manufacturing a semiconductor memory device according to claim 7, wherein the FIN-type semiconductor layer is formed in a line shape in the first etching and the second etching.

13. The method of manufacturing a semiconductor memory device according to claim 7, the method further comprising: depositing a gate electrode material between the adjacent FIN-type semiconductor layers, after the second etching process; andpolishing the gate electrode material until when the upper surface of the FIN-type semiconductor layer is exposed.

14. The method of manufacturing a semiconductor memory device according to claim 7, wherein the semiconductor device stores binary data on the basis of a number of charges stored in the floating body region.

15. The method of manufacturing a semiconductor memory device according to claim 7, wherein the semiconductor device is an FBC memory device having the FIN-type semiconductor layer as a part of a memory cell.

16. The method of manufacturing a semiconductor memory device according to claim 7, wherein the semiconductor device is a fully-depleted type FBC memory device having the FIN-type semiconductor layer as a part of a memory cell.

17. The method of manufacturing a semiconductor memory device according to claim 10, wherein the impurities for source and drain layers are N-type impurities.