BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view of a NAND-type flash EEPROM (non-volatile semiconductor memory device) according to an embodiment of the present invention.
FIG. 2A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 2B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 3A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 3B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 4A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 4B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 5A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 5B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 6A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 6B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 7A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 7B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 8A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 8B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 9A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 9B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 10A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 10B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 11A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 11B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 12A is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
FIG. 12B is a cross-sectional view showing the NAND-type flash EEPROM in process step order.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The embodiment of the present invention will now be described below with reference to the drawings.
FIG. 1 is a plan view of a cell region in a NAND-type flash EEPROM (non-volatile semiconductor memory device) according to an embodiment of the present invention, and FIGS. 2A-12A (2B-12B) are cross-sectional views in process step order. FIGS. 2A-12A are cross-sectional views taken along A-A′ in FIG. 1, and FIGS. 2B-12B are cross-sectional views taken along B-B′ in FIG. 1.
In FIG. 1, within a memory cell array formation region, there are formed selection gates 1 laterally extending in the figure, and a plurality of word lines 2 sandwiched between a pair of the selection gates 1 and extending in parallel with the selection gate 1. On these selection gates 1 and word lines 2, there are formed a plurality of bit lines 3 extending in a direction orthogonal to them. Cell transistors are formed at intersections of the word lines 2 and the bit lines 3.
In FIGS. 2A-12A (2B-12B), a semiconductor substrate or silicon substrate 4 has a well structure in which an n-type well 4b is formed in a p-type silicon substrate 4a, and a p-type well 4c is formed in a region of the n-type well 4b corresponding to the memory cell array. The silicon substrate 4 is sectioned by device isolations 8 as shown in FIGS. 12A, 12B to form device formation regions in the form of stripes isolated from each other. The device formation region narrower in the B-B′ direction functions as a memory cell transistor while the device formation region wider in the B-B′ direction functions as a selection gate transistor. In each device formation region functioning as the memory cell transistor, a floating gate 6a is formed on the silicon substrate 4 with a first insulator 5a interposed therebetween. Further, double-layered control gates 10a, 11a are formed on the floating gate 6a with a tunnel oxide or second insulator 9 interposed therebetween. In each device formation region for the selection gate transistor, double-layered control gates 10b, 11b are formed on a floating gate 6b with a tunnel oxide or second insulator 9 interposed therebetween. A silicide film 16 is formed over the upper surfaces of the control gates 11a, 11b. Thus, the EEPROM of the present embodiment is configured to inject charge not from the silicon substrate 4 but from the control gates 10a, 11b, 11a, 11b through the tunnel oxide or second insulator 9 into the floating gates 6a, 6b.
The floating gates 6a, 6b are separated on a memory cell basis while the control gates 10a, 11a, 10b, 11b and the silicide film 16 form the word lines 2 that are common to a plurality of memory cells and continue in one direction. The floating gates 6a, 6b may use a film of polysilicon or a charge accumulation layer of insulator. On sides exposed in B-B′ section of the floating gates 6a, 6b, the second insulator 9 and the control gates 10a, 11a, 10b, 11b, there is formed a third insulator 5b equal to the first insulator 5a. Between the floating gates 6a, 6b that adjoin in the direction of the bit line 3, there is formed an epitaxial layer 12 epitaxially grown from the silicon substrate 4 with the third insulator 5b interposed therebetween. The epitaxial layer 12 contains a diffusion region 12a there beneath that is formed on epitaxial growth to serve as a source/drain region. A forth insulator 13 is formed over the epitaxial layer 12.
The memory cell array thus configured is covered with interlayer insulators 17, 18 on which the bit lines 3 are formed. Through the interlayer insulator 17, there are formed contact plugs 19 composed of metal, which contact the source region of the selection gate transistor and the silicide film 16 on the control gates 10a, 11a of the memory cell transistor, respectively.
The following description is given to the process steps of manufacturing the NAND-type flash EEPROM according to the embodiment.
First, as shown in FIGS. 2A, 2B, the n-type well 4b is formed in the p-type silicon substrate 4a, and the p-type well 4c is formed in the region of the n-type well 4b corresponding to the memory cell array. Over such the silicon substrate 4, which is composed of, for example, Si or SiGe, the first insulator 5a is formed.
Subsequently, as shown in FIGS. 3A, 3B, a first electrode film 6 is deposited, which is to be turned into the floating gates 6a and 6b of the memory cell transistor and the selection gate transistor. Then, a mask material 7 is deposited over the first electrode film 6.
Next, as shown in FIGS. 4A, 4B, lithography and etching technologies are used to form device isolation regions composed of the device isolation film 8, followed by peeling off the mask material 7. Then, over the entire surface, the second insulator 9 is deposited, which is to be turned into the tunnel insulator between gates of the cell transistor. Further, a second electrode film 10 is deposited, which is used to form the control gate 10a of the cell transistor.
Next, as shown in FIGS. 5A, 5B, on the second electrode film 10, a third electrode film 11 is formed, which is used to form the control gate 11a. In order to electrically connect the third electrode film 11 with the first electrode film 6, the second electrode film 10 and the second insulator 9 are peeled off partly or entirely from the gate region of the selection gate 1 of the cell transistor, followed by depositing the third electrode film 11, which is to be turned into the gate electrode of the selection gate 1 of the cell transistor.
Next, as shown in FIGS. 6A, 6B, lithography and etching technologies are used to form trenches at certain intervals. The trench has a width in the B-B′ direction and a depth extending to the upper surface of the silicon substrate 4. Subsequently, on the sides of the trenches formed through film formation and etching technologies, the third insulator 5b is formed. In the vicinity of the region from which the second electrode film 10 and the second insulator 9 are peeled off, a trench is formed wider in the B-B′ direction. The first insulator 5a is formed beneath the first electrode film 6 while the third insulator 5b is formed on the sides of the first electrode film 6. The first insulator 5a and the third insulator 5b may be composed of either the same material or different types of material.
Next, as shown in FIGS. 7A, 7B, a selective epitaxial layer 12 is formed by selectively epitaxially growing the silicon substrate 4 of which upper surface is exposed through the trenches formed in FIGS. 6A, 6B. Therefore, if the silicon substrate 4 is composed of Si or SiGe, for example, the selective epitaxial layer 12 is also composed of Si or SiGe. Another step may be used to deposit a semiconductor layer other than the selective epitaxial layer 12.
Subsequently, as shown in FIGS. 8A, 8B, after formation of the gate electrode, ions of an n-type impurity such as phosphorous (P) are implanted into the selective epitaxial layer 12 to form an n−-type impurity layer 12a in a region extending from the selective epitaxial layer 12 into the silicon substrate 4. The impurity layer 12a forms a source/drain region of a memory cell. On the selective epitaxial layer 12, a fourth insulator 13 is deposited up to the top of the trench. In the trench made wider in the B-B′ direction and located in the vicinity of the region from which the second electrode film 10 and the second insulator 9 are peeled off, the fourth insulator 13 is deposited only on a side.
Desirably, the upper surface of the selective epitaxial layer 12 formed through the above steps locates lower than the upper surface of the second electrode film 6. More preferably, the upper surface of the selective epitaxial layer 12 locates at ⅓ to ¾ of the height from the lower surface of the second electrode film 6.
Next, as shown in FIGS. 9A, 9B, after peeling off the fourth insulator 13 formed only on the gate side of the selection gate 1 of the cell transistor through the lithography and etching technologies, a fifth insulator 14 and a sixth insulator 15 are deposited.
Next, as shown in FIGS. 10A, 10B, the etching technology and CMP are used to remove the fifth insulator 14 and the upper surface portion of the sixth insulator 15 from above the control gate of the cell transistor and the selection gate 1 of the cell transistor, followed by siliciding the upper surface portion of the third insulator 11, which is to be turned into part of the control gate of the cell transistor, to form the silicide film 16.
Subsequently, as shown in FIGS. 11A, 11B, a general contact formation step is applied to deposit the interlayer insulators 17, 18. Then, as shown in FIGS. 12A, 12B, a general wire formation step is applied to arrange the contact plugs 19 and a metal wiring material, not shown. Thus, the NAND-type flash EEPROM of the present embodiment can be completed.
As described above, in the present embodiment, the NAND-type semiconductor memory device comprises the first electrode film 6 serving as the floating gates 6a formed at certain intervals on the silicon substrate 4 with the first insulator 5a interposed therebetween, and the control gates 10a, 11a formed on the first electrode film 6 with the second insulator 9 interposed therebetween. The device is configured to inject charge from the control gates 10a, 11a (the second electrode film 10 and the third electrode film 11) into the floating gates 6a (the first electrode film 6). Additionally, in the present embodiment, between the floating gates 6a (the first electrode film 6) on the silicon substrate 4, the selective epitaxial layer 12 is arranged as a conductor with the third insulator 5b interposed therebetween. Therefore, it is possible to provide the NAND-type flash EEPROM with a reduced influence of interference between cells adjacent in the direction of bit lines.
In the selective epitaxial layer 12 of the semiconductor layer formed between portions of the first electrode film 6 (the floating gates 6a), on reading the amount of charge from inside the floating gate 6a, an electric field may be applied. Therefore, the capacity between portions of the first electrode film 6 sandwiching the selective epitaxial layer 12 therebetween can be reduced by the amount of capacity between the lower surface of the first electrode film 6 (the floating gate 6a) and the upper surface of the selective epitaxial layer. As a result, the influence of interference between cells adjacent in the direction of bit lines can be reduced.
In addition, the selective epitaxial layer 12 is epitaxially grown in the trench provided between portions of the first electrode film 6. Accordingly, the depth of the trench can be made shallower. Therefore, it is sufficient to form the fourth insulator 13 only in a shallower region above the selective epitaxial layer 12 with easy deposition of the fourth insulator 13.
The above embodiment also discloses the following configurations (1) and (2).
(1) A method of manufacturing semiconductor memory devices for forming the layer of floating gates 6a composed of the first electrode film 6 and formed at certain intervals in a plane on the silicon substrate 4 with the first insulator 5a interposed therebetween, and the layer of control gates 10a composed of the second electrode film 10 and formed on the layer of floating gates 6a with the second insulator 9 interposed therebetween. The method comprises epitaxially growing the surface of the silicon substrate 4 to form the selective epitaxial layer 12 such that the selective epitaxial layer 12 can be formed between the floating gates 6a on the silicon substrate 4 with the third insulator 5b interposed therebetween.
(2) A method of manufacturing semiconductor memory devices for forming the layer of floating gates 6a composed of the first electrode film 6 and formed at certain intervals in a plane on the silicon substrate 4 with the first insulator 5a interposed therebetween, and the layer of control gates 10a composed of the second electrode film 10 and formed on the layer of floating gates 6a with the second insulator 9 interposed therebetween. The method comprises epitaxially growing the surface of the silicon substrate 4 to form the selective epitaxial layer 12 such that the selective epitaxial layer 12 can be formed between the floating gates 6a on the silicon substrate 4 with the third insulator 5b interposed therebetween such that the selective epitaxial layer 12 has an upper surface located lower than the upper surface of the layer of floating gates 6a.
Although the above embodiment exemplifies the NAND-type flash EEPROM, the present invention is also applicable to other semiconductor memory devices of the NOR-type and so forth, needless to say.
Patent Application
20080001205
