SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING MULTILAYER GATE ELECTRODE

Abstract

In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a layout chart showing an outline of a configuration of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a layout chart showing a configuration of cell units in NAND cell regions according to the embodiment of the present invention;

FIG. 3 is a circuit diagram of the cell unit according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view taken along a line 4-4 in the layout chart of FIG. 2;

FIG. 5 is a cross-sectional view taken along a line 5-5 in the layout chart of FIG. 2;

FIG. 6 is a layout chart showing a configuration of a peripheral transistor included in a conventional peripheral circuit;

FIG. 7 is a layout chart showing a first structural example of a peripheral transistor in a peripheral circuit region according to the embodiment of the present invention;

FIG. 8 is a cross-sectional view taken along a line 8-8 in the layout chart of FIG. 7; and

FIG. 9 is a layout chart showing a second structural example of a peripheral transistor in a peripheral circuit region according to the embodiment of the present invention.

Claims

1. A semiconductor memory device comprising: a memory cell array in which there are arranged a plurality of cell units having memory cells and selection gate transistor to select the memory cells; a first selection gate line which includes a first control gate of the selection gate transistors, the first selection gate line having a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order, the first inter-gate insulating film having a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other;a second selection gate line formed above the first selection gate line; anda first contact material which is formed on the first selection gate line and electrically connects the first selection gate line and the second selection gate line with each other, the first contact material being arranged on the first selection gate line on which the first opening portion is not arranged.

2. The semiconductor memory device according to claim 1, wherein the memory cell includes a first gate insulating film on a semiconductor substrate, a floating gate on the first gate insulating film, a second inter-gate insulating film on the floating gate, and a second control gate on the second inter-gate insulating film.

3. The semiconductor memory device according to claim 1, further comprising: a source region formed on the semiconductor substrate;a drain region formed on the semiconductor substrate apart from the source region;a second gate insulating film formed on the semiconductor substrate between the source region and the drain region;a third gate electrode formed on the second gate insulating film;a third inter-gate insulating film which is formed on the third gate electrode and has a second opening portion immediately above the semiconductor substrate between the source region and the drain region;a fourth gate electrode which is formed on the third gate electrode in the second opening portion and on the third inter-gate insulating film; anda second contact material which is formed on the fourth gate electrode immediately above the semiconductor substrate between the source region and the drain region,wherein the second opening portion and the second contact material do not overlap each other in a direction vertical to a surface of the semiconductor substrate.

4. The semiconductor memory device according to claim 1, wherein the second gate electrode includes a polysilicon film and a silicide film formed on the polysilicon film.

5. A semiconductor memory device comprising: first and second blocks in which a plurality of cell units having a plurality of memory cells connected in series and selection gate transistors connected with both ends of each of the plurality of memory cells are arranged;a shunt region which is arranged between the first block and the second block and in which the memory cell is not formed;a first selection gate line as a first control gate of the selection gate transistor which is formed to extend in the first and second blocks and in the shunt region, the first selection gate line having a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order, the first inter-gate insulating film having a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other;a second selection gate line formed above the first selection gate line; anda first contact material which is formed on the first selection gate line in the shunt region and electrically connects the first selection gate line and the second selection gate line with each other,wherein the first opening portion is arranged on the first selection gate line in the shunt region, and the first contact material is arranged on the first selection gate line on which the first opening portion is not arranged in the shunt region.

6. The semiconductor memory device according to claim 5, wherein first and second activation regions are arranged in the shunt region, the first opening portion is arranged on the first selection gate line on the first activation region, and the first contact material is arranged on the first selection gate line on the second activation region.

7. The semiconductor memory device according to claim 5, wherein the memory cell includes a first gate insulating film on a semiconductor substrate, a floating gate on the first gate insulating film, a second inter-gate insulating film on the floating gate, and a second control gate on the second inter-gate insulating film.

8. The semiconductor memory device according to claim 7, further comprising: a source region formed on the semiconductor substrate;a drain region formed on the semiconductor substrate apart from the source region;a second gate insulating film formed on the semiconductor substrate between the source region and the drain region;a third gate electrode formed on the second gate insulating film;a third inter-gate insulating film which is formed on the third gate electrode, and has a second opening portion immediately above the semiconductor substrate between the source region and the drain region;a fourth gate electrode formed on the third gate electrode in the second opening portion and on the third inter-gate insulating film; anda second contact material formed on the fourth gate electrode immediately above the semiconductor substrate between the source region and the drain region,wherein the second opening portion and the second contact material do not overlap each other in a direction vertical to a surface of the semiconductor substrate.

9. The semiconductor memory device according to claim 5, wherein the selection gate transistor connected with one end of each of the plurality of memory cells is connected with a source line, and the selection gate transistor connected with the other end of each of the plurality of memory cells is connected with a bit line.

10. The semiconductor memory device according to claim 5, wherein the plurality of memory cells are arranged in such a manner that the memory cells adjacent to each other share a source or a drain.

11. The semiconductor memory device according to claim 5, wherein the second gate electrode includes a polysilicon film and a silicide film formed on the polysilicon film.

12. A semiconductor memory device comprising: first and second blocks each including a plurality of activation regions, a plurality of memory cells and selection gate transistors, the plurality of activation regions extending in a column direction being arranged in a row direction, the plurality of memory cells connected in series being formed in each of the activation regions, and the selection gate transistors being formed at both ends of the plurality of memory cells connected in series;a shunt region which is arranged between the first block and the second block and in which first and second activation regions extending in the column direction are arranged in the row direction;a first selection gate line as a control gate of the selection gate transistors which is formed on the activation regions in the first and the second blocks and on the first and second activation regions in the shunt region to extend in the row direction, the first selection gate line having a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order, the first inter-gate insulating film having a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other;a second selection gate line which is formed above the first selection gate line; anda first contact material which is formed on the first selection gate line in the shunt region, and electrically connects the first selection gate line and the second selection gate line with each other,wherein, in the shunt region, the first opening portion is arranged on the first selection gate line on the first activation region, and the first contact material is arranged on the first selection gate line on the second activation region.

13. The semiconductor memory device according to claim 12, wherein the first contact material is arranged on the first selection gate line on which the first opening portion is not arranged in the shunt region.

14. The semiconductor memory device according to claim 12, wherein the memory cell includes a first gate insulating film on a semiconductor substrate, a floating gate on the first gate insulating film, a second inter-gate insulating film on the floating gate, and a second control gate on the second inter-gate insulating film.

15. The semiconductor memory device according to claim 14, further comprising: a source region formed on the semiconductor substrate;a drain region formed on the semiconductor substrate apart from the source region;a second gate insulating film formed on the semiconductor substrate between the source region and the drain region;a third gate electrode formed on the second gate insulating film;a third inter-gate insulating film formed on the third gate electrode, and has a second opening portion immediately above the semiconductor substrate between the source region and the drain region;a fourth gate electrode formed on the third gate electrode in the second opening portion and on the third inter-gate insulating film; anda second contact material formed on the fourth gate electrode immediately above the semiconductor substrate between the source region and the drain region,wherein the second opening portion and the second contact material do not overlap each other in a direction vertical to a surface of the semiconductor substrate.

16. The semiconductor memory device according to claim 12, wherein the selection gate transistor connected with one end of the plurality of memory cells is connected with a source line, and the selection gate transistor connected with the other end of the plurality of memory cells is connected with a bit line.

17. The semiconductor memory device according to claim 12, wherein the plurality of memory cells are arranged in such a manner that the memory cells adjacent to each other share a source or a drain.

18. The semiconductor memory device according to claim 12, wherein the second gate electrode includes a polysilicon film and a silicide film formed on the polysilicon film.

19. A semiconductor device comprising: a source region formed on a semiconductor substrate;a drain region formed on the semiconductor substrate apart from the source region;a gate insulating film formed on a channel region between the source region and the drain region;a first gate electrode formed on the gate insulating film;an inter-gate insulating film which is formed on the first gate electrode, and has an opening portion immediately above the channel region;a second gate electrode formed on the first gate electrode in the opening portion and on the inter-gate insulating film; anda contact material formed on the second gate electrode immediately above the channel region,wherein the opening portion and the contact material do not overlap each other in a direction vertical to a surface of the semiconductor substrate.