SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE

Abstract

Decreases in area efficiency and wiring efficiency and degradation in performance are prevented which result from imbalances in dimensional ratios between miniaturized control circuits and other components brought by the development of microfabrication process such as a process of fabricating large-capacity DRAMs as hard macros. A memory array region and a control region are placed such that the two regions are in contact with each other and have a convex shape when viewed from above. Because of this, the layout areas of memories such as large-capacity DRAMs are optimized and their production cost can be reduced. That is, by taking note that the fact that large-capacity DRAMs are in a quadrilateral shape is not an essential condition for the ease of their placement because large-scale DRAMs have the disadvantages that the number of the DRAMs provided in semiconductor devices is limited and the ratio of the areas of the DRAMs to that of the semiconductor devices is high unlike ROMs and SRAMs required to come in various sizes, a large-capacity DRAM can be not only fabricated with its area efficiency and wiring efficiency optimized but provided as a hard macro having a configuration easily laid out in terms of the implementation of a system LSI.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is an explanatory drawing of components placed in a control region presented in the first embodiment of the invention;

FIG. 3 is a schematic diagram of a semiconductor memory device according to a second embodiment of the invention;

FIG. 4 is a schematic diagram of a semiconductor memory device according to a third embodiment of the invention;

FIG. 5 is an explanatory drawing of changes in the placement locations of various lines of FIG. 4;

FIG. 6 is a schematic diagram of a semiconductor memory device according to a fourth embodiment of the invention;

FIG. 7 is a schematic diagram of a semiconductor memory device according to a fifth embodiment of the invention;

FIG. 8 is a schematic diagram of a semiconductor memory device according to a sixth embodiment of the invention;

FIG. 9 is a schematic diagram of the basic circuit of a semiconductor memory device including a DRAM;

FIG. 10 is a schematic diagram of a conventional configuration of the semiconductor memory device of FIG. 9; and

FIG. 11 is an explanatory drawing of components placed in a control region of FIG. 10.

Claims

1. A semiconductor memory device provided with a memory array region which is configured in such a way that the two-dimensional placement of a memory cell region where memory cells are arranged in the form of a matrix, plural circuits which selectively point to rows and columns in the memory cell region and which read and write data from and to the memory cells selectively pointed to, and a data input/output circuit which inputs the read data and which outputs the written data takes on the shape of a quadrilateral anda control region which is configured in such a way that the two-dimensional placement of an address input circuit which selectively outputs an address which specifies a row and a column according to an address control signal, a control circuit which sends out the address control signal according to an external control signal, a refresh circuit which produces the address control signal instead of the external control signal during standby to effect the refresh operation of the memory cell region, a timing generator circuit which adjusts the timings of the operations of the address input circuit, the control circuit, and the refresh circuit, and a clock generator circuit which synchronizes the data input/output circuit, the address input circuit, the control circuit, the refresh circuit, and the timing generator circuit takes on the shape of a quadrilateral, whereinthe control region is connected to the memory array region with the mutually connected sides of both the regions differing in length.

2. The semiconductor memory device according to claim 1, wherein the memory array region and the control region are spaced from each other.

3. The semiconductor memory device according to claim 1, wherein the memory array region and the control region are placed such that the two regions are in contact with each other and have a convex shape when viewed from above.

4. The semiconductor memory device according to claim 3, wherein the control region can be placed so as to be connected to any place on the specified side of the memory array region.

5. The semiconductor memory device according to claim 1, wherein the terminals which receive the external control signals are placed to at least two sides not contacting the memory array region of the control region.

6. The semiconductor memory device according to claim 2, wherein the terminals which receive the external control signals are placed to at least two sides not contacting the memory array region of the control region.

7. The semiconductor memory device according to claim 3, wherein the terminals which receive the external control signals are placed to at least two sides not contacting the memory array region of the control region.

8. The semiconductor memory device according to claim 4, wherein the terminals which receive the external control signals are placed to at least two sides not contacting the memory array region of the control region.

9. The semiconductor memory device according to claim 1, wherein the configuration of power supply wirings for the circuits constituting the control region is the same as the configuration of power supply wirings for large-scale logic circuits formed on a substrate on which the control region is provided.

10. The semiconductor memory device according to claim 2, wherein the configuration of power supply wirings for the circuits constituting the control region is the same as the configuration of power supply wirings for large-scale logic circuits formed on a substrate on which the control region is provided.

11. The semiconductor memory device according to claim 3, wherein the configuration of power supply wirings for the circuits constituting the control region is the same as the configuration of power supply wirings for large-scale logic circuits formed on a substrate on which the control region is provided.

12. The semiconductor memory device according to claim 4, wherein the configuration of power supply wirings for the circuits constituting the control region is the same as the configuration of power supply wirings for large-scale logic circuits formed on a substrate on which the control region is provided.

13. The semiconductor memory device according to claim 2, wherein the circuits constituting the control region receive power from a large-scale logic circuit formed on a substrate on which the control region is provided.

14. The semiconductor memory device according to claim 3, wherein the circuits constituting the control region receive power from the memory array region.

15. The semiconductor memory device according to claim 4, wherein the circuits constituting the control region receive power from the memory array region.

16. The semiconductor memory device according to claim 2, wherein the data input/output terminals of the data input/output circuit can be placed to any portions other than a portion connected with the control region on the side opposite to the control region of the memory array region spaced from the control region.

17. The semiconductor memory device according to claim 3, wherein the data input/output terminals of the data input/output circuit can be placed to any portions other than a portion contacting the control region on the side contacting the control region of the memory array region.

18. The semiconductor memory device according to claim 4, wherein the data input/output terminals of the data input/output circuit can be placed to any portions other than a portion contacting the control region on the side contacting the control region of the memory array region.

19. The semiconductor memory device according to claim 2, wherein redundancy saving address data setting terminals are placed to any portions other than a portion connected with the control region on the side opposite to the control region of the memory array region spaced from the control region.

20. The semiconductor memory device according to claim 3, wherein redundancy saving address data setting terminals are placed to any portions other than a portion contacting the control region on the side contacting the control region of the memory array region.

21. The semiconductor memory device according to claim 4, wherein redundancy saving address data setting terminals are placed to any portions other than a portion contacting the control region on the side contacting the control region of the memory array region.

22. A semiconductor device, wherein large-scale logic circuits to be formed on a substrate on which the control region is provided are placed to concave portions on both sides of the convex portion of the semiconductor memory device according to claim 3.

23. A semiconductor device, wherein large-scale logic circuits to be formed on a substrate on which the control region is provided are placed to concave portions on both sides of the convex portion of the semiconductor memory device according to claim 4.

24. A semiconductor device, wherein redundancy saving address storage units, which are connected to the redundancy saving address data setting terminals of the semiconductor memory device according to claim 19 and which are provided on a substrate on which the control region is provided, are placed to concave portions on both sides of the convex portion.

25. The semiconductor memory device according to claim 1, wherein the plural memory array regions can be controlled with the control region.

26. The semiconductor memory device according to claim 2, wherein the plural memory array regions can be controlled with the control region.

27. The semiconductor memory device according to claim 3, wherein the plural memory array regions can be controlled with the control region.

28. The semiconductor memory device according to claim 4, wherein the plural memory array regions can be controlled with the control region.

29. A semiconductor memory device, wherein the relationship between the placement location of the control region and that of the memory array region of the semiconductor memory device according to claim 2 is plurally utilized such that the plural memory array regions can be controlled with the control region.

30. A semiconductor memory device, wherein the relationship between the placement location of the control region and that of the memory array region of the semiconductor memory device according to claim 3 is plurally utilized such that the plural memory array regions can be controlled with the control region.

31. A semiconductor memory device characterized in that the semiconductor memory device according to claim 2 is plurally provided such that the semiconductor memory devices are desirably arranged one after the other with the desirable sides on which the data input/output circuits are not formed of the memory array regions oppositely arranged one after the other.

32. A semiconductor memory device characterized in that the semiconductor memory device according to claim 3 is plurally provided such that the semiconductor memory devices are desirably arranged one after the other with the desirable sides on which the data input/output circuits are not formed of the memory array regions oppositely arranged one after the other.

33. A semiconductor memory device characterized in that the semiconductor memory device according to claim 4 is plurally provided such that the semiconductor memory devices are desirably arranged one after the other with the desirable sides on which the data input/output circuits are not formed of the memory array regions oppositely arranged one after the other.