Claims
- 1. A semiconductor memory device, comprising:
- a semiconductor substrate;
- a memory cell array having a plurality of memory cells disposed in rows and columns on said substrate,
- each said memory cell being bounded by first and second ground lines in the column direction;
- a third ground line formed on said substrate in the row direction and connected to said memory cells; and
- first and second word lines formed on said substrate in the row direction and connected to said memory cells,
- successive memory cells connected to said third ground line being connected to said first and second word lines alternately.
- 2. The semiconductor memory device as recited in claim 1, wherein
- said third ground line includes a conductive layer formed on said substrate,
- each said memory cell includes a field effect transistor on said substrate,
- said field effect transistor includes active regions formed in said substrate, and
- said conductive layer is connected to said active regions in said memory cells.
- 3. The semiconductor memory device as recited in claim 2, wherein
- said conductive layer includes a polysilicon interconnection formed on said substrate.
- 4. The semiconductor memory device as recited in claim 1, wherein
- said first and second ground lines each include a grounded metal interconnection, and
- said third ground line has one end connected to said first ground line and the other end connected to said second ground line.
Priority Claims (1)
Number |
Date |
Country |
Kind |
4-257840 |
Sep 1992 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/126,765 filed Sep. 27,1993, now U.S. Pat. No. 5,379,247.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4733374 |
Furuyama et al. |
Mar 1988 |
|
5289404 |
Okamoto |
Feb 1994 |
|
5365475 |
Matsumura |
Nov 1994 |
|
Foreign Referenced Citations (2)
Number |
Date |
Country |
62-188263 |
Aug 1987 |
JPX |
4-186671 |
Jul 1992 |
JPX |
Non-Patent Literature Citations (3)
Entry |
"A Polysilicon Transistor Technology for Large Capacity SRAMs", by Shuji Ikeda et al., International Electron Devices Meeting, Dec. 9-12, 1990, pp. 469-472. |
Y. Kobayashi et al., "A 10-.mu.WStandbyPower 2.56K CMOS SRAM" IEEE Journal of Solid-State Circuits, vol. 20, No. 5, Oct. 1985, pp. 935-940. |
D. Min et al., "Wordline Coupling Noise Reduction Techniques For Scaled DRAMs" 1990 Symposium on VLSI Circuits, Jun. 1990, pp. 81-82. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
126765 |
Sep 1993 |
|