Semiconductor memory device including plurality of memory mats

Abstract

A semiconductor memory device includes a plurality of memory mats each including a memory cell storing data, a sense latch portion performing detection of data stored by the memory cell, and a buffer circuit externally outputting read data detected by the sense latch portion. The sense latch portion and the buffer circuit are shared between a plurality of memory mats and are arranged between a plurality of memory mats.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram schematically showing a configuration of a semiconductor memory device in accordance with a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a sense latch portion and a memory mat in the semiconductor memory device in accordance with the first embodiment of the present invention.

FIG. 3 is a diagram showing an interconnection line between a sense latch and a buffer circuit.

FIG. 4 is a diagram showing another example of an interconnection line between a sense latch and a buffer circuit.

FIG. 5 is a diagram showing a layout of a precharge/discharge MOS transistor in the semiconductor memory device in accordance with the first embodiment of the present invention.

FIG. 6 is a diagram showing a modified layout of a precharge/discharge MOS transistor in the semiconductor memory device in accordance with the first embodiment of the present invention.

FIG. 7 is a diagram schematically showing a configuration of a semiconductor memory device in accordance with a second embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a sense latch portion and a memory mat in the semiconductor memory device in accordance with the second embodiment of the present invention.

Claims

1. A semiconductor memory device comprising: a plurality of memory mats each including a memory cell storing data;a sense amplifier performing detection of data stored by said each memory cell; anda buffer circuit externally outputting read data detected by said sense amplifier, whereinsaid sense amplifier and said buffer circuit are shared between said plurality of memory mats and are arranged between said plurality of memory mats.

2. The semiconductor memory device according to claim 1, wherein said buffer circuit externally receives write data for said each memory cell, said semiconductor memory device further comprising:a latch circuit performing temporary storage of said externally received write data for said each memory cell and said detected read data, andsaid sense amplifier, said buffer circuit and said latch circuit are shared between said plurality of memory mats and are arranged between said plurality of memory mats.

3. A semiconductor memory device comprising: a first memory mat and a second memory mat each including a memory cell storing data;at least one first current line arranged for each of said memory mats and connected to one conductive electrode of said memory cell;a sense latch shared between said memory mats, storing electric charges corresponding to write data for said memory cell in said first current line and detecting data stored by said memory cell based on a voltage value or a current value of said first current line;at least one second current line arranged for each of said memory mats;a plurality of first transistors arranged corresponding to said first current line for switching between connection and disconnection between said first current line and said second current line;a plurality of second transistors arranged corresponding to said first current line for switching between connection and disconnection between said first current line and said sense latch;at least one third current line arranged for each of said memory mats; anda plurality of third transistors arranged corresponding to said first current line for switching between connection and disconnection between the other conductive electrode of said memory cell and said third current line.

4. The semiconductor memory device according to claim 3, further comprising: a voltage generation circuit supplying voltage to said each transistor; anda control circuit controlling said sense latch and said voltage generation circuit such thatin data reading from said memory cell of said each memory mat, said first transistor corresponding to said each memory mat is activated to connect said first current line and said second current line, and thereafter said third transistor corresponding to said each memory mat is activated to connect the other conductive electrode of said memory cell and said third current line, and thereaftersaid second transistor corresponding to any one of said memory mats is successively activated and said second transistor of another said memory mat is inactivated thereby to successively detect storage data of said memory cell connected to said first current line corresponding to said activated second transistor, based on a voltage value or a current value of said first current line corresponding to said activated second transistor.

5. The semiconductor memory device according to claim 3, further comprising: a voltage generation circuit supplying voltage to said each transistor; anda control circuit controlling said sense latch and said voltage generation circuit such thatin data writing to said memory cell of said each memory mat, said second transistor corresponding to any one of said memory mats is successively activated and said second transistor of another said memory mat is inactivated, and electric charges corresponding to said write data are stored in said first current line connected to said activated second transistor and thereafter said third transistor corresponding to said each memory mat is activated to connect the other conductive electrode of said memory cell and said third current line.

6. The semiconductor memory device according to claim 3, wherein said first memory mat, a drain region, a gate region and a source region of said first transistor corresponding to said first memory mat, said sense latch, a drain region, a gate region and a source region of said first transistor corresponding to said second memory mat, and said second memory mat are arranged in that order in a direction in which said first current line extends.

7. The semiconductor memory device according to claim 3, wherein a fourth transistor and a fifth transistor are arranged between said sense latch and said first memory mat, and a source region of said fourth transistor and said fifth transistor is formed in common,a sixth transistor and a seventh transistor are arranged between said sense latch and said second memory mat, and a source region of said sixth transistor and said seventh transistor is formed in common,said first memory mat, a drain region and a gate region of said fourth transistor, the source region of said fourth transistor and said fifth transistor, a gate region and a drain region of said fifth transistor, said sense latch, a drain region and a gate region of said sixth transistor, the source region of said sixth transistor and said seventh transistor, a gate region and a drain region of said seventh transistor, and said second memory mat are arranged in that order in a direction in which said first current line extends, andsaid fourth transistor is used as said first transistor corresponding to said first memory mat, and said sixth transistor is used as said first transistor corresponding to said second memory mat.