Number | Date | Country | Kind |
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1-171283 | Jul 1989 | JPX |
Number | Name | Date | Kind |
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4464750 | Tatematsu | Aug 1984 | |
4899313 | Kumanoya et al. | Feb 1990 | |
4916700 | Ito et al. | Apr 1990 |
Number | Date | Country |
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206486 | Dec 1986 | EPX |
Entry |
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IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988, N.Y., "Repair Calculation For Randon-Access Memory Redundance Using Built-in Logic and Scannable Latches", pp. 424-425. |
IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, N.Y., "A redundancy Test-Time Reduction Technique in 1-Mbits DRAM With a Multibit Test Mode", Y, Nishimura et al., pp. 43-49. |