Embodiments described herein relate to a semiconductor memory device.
In recent years, in order to reduce mutual interference between adjacent memory cells in a NAND flash memory, a structure including air gaps in a word line direction between cells (a word line air gap structure) is starting to be adopted. When using the word line air gap structure, there is a need for securing a degree of distance between air gaps and wirings which are disposed on the air gaps. Meanwhile, in peripheral circuits, there is a need for a reduction in variation of wiring resistance due to the circuit characteristics.
In general, according to one embodiment, a semiconductor device includes a memory cell region and a peripheral circuit region, a plurality of adjacent memory gates that are disposed on the semiconductor substrate via a tunnel insulating film in the memory cell region, a first insulating film covering the memory gates and having air gaps formed therein between the memory gates, a first barrier film on the first insulating film, a second insulating film above the semiconductor substrate in the peripheral circuit region, a second barrier film on the first barrier film and the second insulating film, and a third insulating film on the second barrier film and having a first groove, in which a first wiring is formed above the memory cell region, and a second groove in which a second wiring is formed above the peripheral circuit region. A distance between a lower surface of the first wiring and an upper surface of the semiconductor substrate in the memory cell region is larger than a distance between an upper surface of the first barrier film and the upper surface of the semiconductor substrate in the memory cell region, and a lower surface of the second wiring is closer to the upper surface of the semiconductor substrate in the peripheral circuit region than an upper surface of the second barrier film.
Hereinafter, description will be given of the NAND flash memory device as the semiconductor memory device to which the first embodiment is applied, with reference to
First, description will be given of the configuration of the NAND flash memory device of the semiconductor memory device according to the embodiments.
A plurality of unit memory cells UC are arranged in the memory cell array Ar in the memory cell area M. In the unit memory cells UC, a selection gate transistor STD is provided on a side which is connected to bit lines BL0 to BLn-1, and a selection gate transistor STS is provided on aside of a source line SL. There are m (for example, m=2k) memory cell transistors MT0 to MTm-1 connected in series between the selection gate transistors STD and STS. The memory cell transistors MT make up the memory cells MC.
The plurality of unit memory cells UC form memory cell blocks, and a plurality of the memory cell blocks form the memory cell array Ar. In other words, one block is formed of n columns of the unit memory cells UC arranged in parallel in a row direction (the X direction in
Referring to one unit memory cell UC, a control line SGD is connected to the gate of the selection gate transistor STD which is connected to one of the bit lines BL0 to BLn-1. A word line WLm-1 is connected to the control gate of the m-th memory cell transistor MTm-1. A word line WL2 is connected to the control gate of the third memory cell transistor MT2. A word line WL1 is connected to the control gate of the second memory cell transistor MT1. A word line WL0 is connected to the control gate of the first memory cell transistor MT0. A control line SGS is connected to the gate of the selection gate transistor STS which is connected to the source line SL. The bit lines BL0 to BLn-1 are connected to a sense amplifier (not illustrated).
The selection gate transistors STD of the plurality of unit memory cells UC which are arranged in the row direction are electrically connected to the control line SGD by the gate electrodes thereof. Similarly, the selection gate transistors STS of the plurality of unit memory cells UC which are arranged in the row direction are electrically connected to the control line SGS by the gate electrodes thereof. The sources of the selection gate transistors STS are connected in common to the source line SL. The memory cell transistors MT0 to MTm-1 of the plurality of unit memory cells UC which are arranged in the row direction are electrically connected to the word lines WL0 to WLm-1, respectively, by the gate electrodes thereof.
In
Element isolation areas Sb are formed to extend in the Y direction in the drawings. The element isolation areas Sb have an STI (Shallow Trench Isolation) structure which is formed by filling a trench with an insulating film. A plurality of the element isolation areas Sb are formed at a predetermined interval in the X direction. Due to the element isolation areas Sb, a plurality of element areas Sa, which are formed on a surface layer portion of the semiconductor substrate to extend along the Y direction, are formed to be separated in the X direction. In other words, the element isolation areas Sb are provided between the element areas Sa, and the semiconductor substrate is divided into a plurality of element areas Sa by the element isolation areas Sb.
The word lines WL are formed to extend along a direction orthogonal to the element area Sa (the X direction in
The selection gate transistors STS and STD are disposed at the intersecting portions of the control lines SGS and SGD and the element areas Sa. The selection gate transistors STS and STD are provided to be adjacent to both outer-side memory cell transistors MT in the Y direction of the end portions of the NAND column.
A plurality of the selection gate transistors STS of the source line SL side are provided in the X direction, and the selection gates SG of the plurality of selection gate transistors STS are electrically connected by the control line SGS. The selection gates SG of the selection gate transistors STS are formed at the portions where the control line SGS and the element areas Sa intersect. Source line contacts SLC are provided at intersecting portions of the source line SL and the element areas Sa.
A plurality of the selection gate transistors STD are provided in the X direction in the drawings, and the selection gates SG of the selection gate transistors STD are electrically connected by the control line SGD. The selection gate transistors STD are formed at the portions where the control line SGD and the element areas Sa intersect. Bit line contacts BLC are formed on each of the element areas Sa between the adjacent selection gate transistors STD.
Various commands CMD, addresses ADD, and data DT which control the operation of the NAND flash memory and are supplied from a host or a memory controller HM, are input to a buffer 306. Write data which is input to the buffer 306 is supplied to the bit line BL which is selected by a bit line control circuit 302. In addition, the various commands CMD and addresses ADD are input to a control circuit 308, and the control circuit 308 controls a booster circuit 310, a driver 312 or the like based on the commands CMD and addresses ADD. In addition, control signals ALE (address latch enable), CLE (command latch enable), WE (write enable), and RW (read enable) are also input to the buffer 306. In addition, the control circuit 308 may control an output buffer circuit or the like disposed in the buffer 306.
According to the control of the control circuit 308, the booster circuit 310 generates the voltages which are necessary for writing, reading and erasing, and supplies the voltages to the driver 312. According to the control of the control circuit 308, the driver 312 supplies these voltages to the bit line control circuit 302 and a word line control circuit 304. According to these voltages, the bit line control circuit 302 and the word line control circuit 304 read data from the memory cells MC, write data to the memory cells MC, and perform erasure of the data of the memory cells MC.
The memory cell array Ar is connected to the bit line control circuit 302 for controlling the voltages of the bit lines BL, and the word line control circuit 304 for controlling the voltages of the word lines WL. In addition, the bit line control circuit 302 and the word line control circuit 304 are connected to the driver 312.
In other words, the driver 312 controls the bit line control circuit 302 based on the addresses ADD, and reads the data of the memory cells MC in the memory cell array Ar via the bit lines BL. In addition, the driver 312 controls the bit line control circuit 302 based on the addresses ADD, and writes to the memory cells MC in the memory cell array Ar via the bit lines BL.
In addition, there are cases in which the bit line control circuit 302, the word line control circuit 304, the driver 312, and the control circuit 308 are referred to collectively as the “control circuit”.
A plurality of pads PA are disposed in the buffer 306. Bonding wires, through hole vias and the like are connected to the pads PA. Via the bonding wires, through hole vias and the like, signals such as the data DT are input to the pads PA from the host or memory controller HM. Here, pads to which the data DT, the commands CMD, the addresses ADD and the like are input are pads PA-1 to k (where k is an integer of 1 or greater), and pads to which control signals such as the write enable signal and the chip enable signal are input are pads PA-C1 and C2. Note that, two or more of the pads PA-C1 and C2 may be provided.
Buffer units BF-1 to k are connected to the pads PA-1 to k, respectively. Buffer units BF-C1 and C2 are connected to the pads PA-C1 and C2, respectively.
Note that, pads to which a ground voltage VSS and an external voltage VEXT are supplied are also present in the NAND flash memory device 100. Here, in order to forma current path for allowing surges to escape, a protective element may be connected to the pads which supply the external voltage.
As illustrated in
One end of each of the p-type transistors OB1TP-1 to OB1TP-m is connected to the node N1, and the other end is connected to the power supply voltage VEXT. One end of each of the n-type transistors OB1TN-1 to OB1TN-m is connected to the node N1, and the other end is connected to the ground voltage VSS. In addition, the control circuit 308 controls each of the gate electrodes (the control lines) of the p-type transistors OB1TP-1 to OB1TP-m and the n-type transistors OB1TN-1 to OB1TN-m, and may switch the p-type transistors OB1TP-1 to OB1TP-m and the n-type transistors OB1TN-1 to OB1TN-m between a conductive state and a non-conductive state.
Here, the p-type transistors OB1TP-1 to OB1TP-m may be said to be connected in parallel to the node N1, and the n-type transistors OB1TN-1 to OB1TN-m may be said to be connected in parallel to the node N1.
In addition, a plurality of output buffer circuits OB2-1 to OB2-n (where n is an integer of 2 or greater) are disposed, and an output buffer circuit group B2 is configured. The output buffer circuits OB2-1 to OB2-n are connected in series to the node N1. Each of output buffer circuits OB2-1 to OB2-n includes p-type transistors OB2TP-1 to OB2TP-n and n-type transistors OB2TN2 to OB2TN-n, respectively.
One end of each of the p-type transistors OB2TP-1 to OB2TP-n is connected to the power supply voltage VEXT. One end of each of the n-type transistors OB2TN2 to OB2TN-n is connected to the ground voltage VSS. The other ends of the p-type transistors OB2TP-1 to n of the output buffer circuits OB2-1 to OB2-n are connected to the node N1 via resistors RP1 to RPn, respectively. The other ends of the n-type transistors OB2TN-1 to n of the output buffer circuits OB2-1 to OB2-n are connected to the node N1 via resistors RN1 to RNn, respectively.
Here, the resistors RP1 to RPn and RN1 to RNn2, and R3 are, for example, wiring resistors. A wiring 42 of the ODT circuit unit described hereinafter may use, for example, the resistors RP1 to RPn, RN1 to RNn2, and R3 of the output buffer circuit as the wiring resistors.
In addition, the control circuit 308 controls each of the gate electrodes (the control lines) of the p-type transistors OB2TP-1 to OB2TP-n and the n-type transistors OB2TN2 to OB2TN-n, and may switch the p-type transistors OB2TP-1 to OB2TP-n and the n-type transistors OB2TN2 to OB2TN-n between a conductive state and a non-conductive state.
Here, the p-type transistors OB2TP-1 to OB2TP-n may be said to be connected in parallel to the node N1, and the n-type transistors OB2TN2 to OB2TN-n may be said to be connected in parallel to the node N1.
In addition, the p-type transistors OB1TP-1 to OB1TP-m and OB2TP-1 to OB2TP-n may be said to be connected in parallel to the node N1, and the n-type transistors OB1TN-1 to OB1TN-m and OB2TN-1 to OB1TN-n may be said to be connected in parallel to the node N1.
The above is the general configuration of the NAND flash memory device 100 to which the present embodiment is applied. The configuration is the same for the second embodiment described hereinafter.
The NAND flash memory may be divided largely into the memory cell unit and the peripheral circuit unit. In order to increase the memory capacity per unit area and to reduce the manufacturing cost per bit, the memory cells continue to be miniaturized. The distance between adjacent cells becomes smaller with the miniaturization of the memory cells; however, associated with this is an increase in the mutual interference of adjacent cells (this is referred to as adjacent cell interference). In the NAND flash memory, writing of data is performed in order a page at a time.
For example, a case is assumed in which data 0 is written to a cell in the writing of a certain page, and data 1 is written to a cell adjacent to the cell in the writing of the next page. There is a case in which, due to the electrical coupling of cells via the inter-cell insulating film of both, the potential of the cell to which the data 0 is written is pulled by the potential of the adjacent cell to which the data 1 is written and flips from the data 0 to 1. In this manner, the adjacent cell interference causes a degradation in reliability in the data retention property.
As one of countermeasures, a structure in which air gaps are provided between the word lines (known as the word line air gap structure) is proposed. In comparison to a structure where the space between word lines is filled with an insulating film such as a silicon oxide film, this structure may reduce the permittivity between the word lines. Accordingly, the wiring capacitance between the adjacent cells may be reduced, and the adjacent cell interference may be reduced.
Meanwhile, the air gap structure increases the difficulty of process integration. For example, in normal NAND flash memory, wiring layers are formed on the gate electrodes of the memory cells and the peripheral circuits. Of the wiring layers, as the material of the wiring layer which is disposed on the layer closest to the gate electrodes (for example, the source line SL), mainly metals such as tungsten (W) and aluminum (Al) are used, and is normally formed using a process common with the memory cells and the peripheral circuits. Here, there is a case in which the wiring layer which is disposed on the layer closest to the gate electrodes is referred to as the lowest wiring layer (the lowest wiring level).
The wiring which is formed on the lowest wiring layer is often formed using the so-called damascene process, and the depth of the wiring groove in the formation is controlled such that the wiring groove does not reach the air gaps. When the wiring groove is too deep and the wiring groove reaches the air gaps provided between the word lines, the metal for wiring formation which is subsequently stacked encroaches the inside of the air gaps, causing shorting or the like between the wiring and the gate electrodes of the cells. Therefore, for the wiring groove not to reach the air gaps even if variation in depth occurs, it is necessary to set the height of the bottom of the wiring groove so as to secure a fixed distance between the air gaps and the wiring groove.
Next, description will be given regarding the influence that variations in the resistance of the wiring has on the circuit and the necessity of reducing the variations. In recent years, an On Die Termination (ODT) circuit is implemented in the peripheral circuits of the NAND flash memory. The ODT circuit is a circuit which operates to match the impedance of the NAND flash memory with the impedance of an external circuit such as a controller. Accordingly, signal degradation due to a mismatch in impedance of both is suppressed.
The ODT circuit is configured of only MOSFETs (metal-oxide-semiconductor field-effect transistor) in the related art; however, in recent years a configuration in which MOSFETs and wiring resistors are combined is being proposed. While this is advantageous in comparison to a case in which the ODT circuit is formed using only MOSFETs in that the linearity of the current in relation to the voltage is good, the influence of the impedance due to the wiring resistor is received. Therefore, in order to obtain the desired impedance, there is a need to reduce the variation in the resistances of the wiring resistors which are used in the ODT circuit.
Here, as the wiring layer for the wiring resistor, any of the wiring layers, of which multiple layers are present in the NAND flash memory, may be used; however, there is a case in which a wiring which is formed on the lowest wiring layer is used from the perspective of having excellent EM (Electron Migration) resistance and a high resistance.
In addition, since tungsten is generally used for the wiring which is formed on the lowest wiring layer, the EM resistance is also excellent. In addition, the wiring which is formed on the lowest wiring layer often has the highest resistance, even among the wiring layers, of which multiple layers are present in the NAND flash memory. Therefore, the area of the wiring resistor may be reduced. For example, the ODT circuit may be used for the output buffer circuit described above.
As described above, in the NAND flash memory to which the word line air gap structure is applied, it is necessary to secure a fixed distance from the air gaps such that the wiring, which is formed on the lowest wiring layer which is formed on the air gaps, does not contact the air gaps between the word lines. In addition, in an area which is used as a portion of the ODT circuit, there is demand for the resistance variation of the wiring which is formed on the lowest wiring layer to be small.
Next, description will be given of the configuration of the NAND flash memory device 100 according to the present embodiment with reference to
On the semiconductor substrate 12, the word lines WL are formed to intersect the element areas Sa and the element isolation areas Sb in a perpendicular direction (the X direction). The plurality of word lines WL extend in the X direction, and are lined up in parallel separated by a predetermined interval in the Y direction in the line/space shape. The two control lines SGS of the source line SL side are disposed parallel to the word lines WL, and the source line contact SLC is provided between the adjacent control lines SGS.
The element areas Sa1 and Sa2 are the source and drain areas of the transistor Trp. Contacts C1 are formed on the element areas Sa1 and Sa2. A contact C2 is formed on the gate electrode PG. In
The tunnel film 14a is provided between the memory gate MG and the semiconductor substrate 12. The gate oxide film 14b is provided between the selection gate SG and the semiconductor substrate 12. A silicon oxide film may be used, for example, as the tunnel film 14a and the gate oxide film 14b.
The memory gate MG includes a charge storage layer 16, an insulating film 18, and a control gate 20, which are stacked. In the memory gate MG, the charge storage layer 16 and the control gate 20 are isolated using the insulating film 18. The selection gate SG includes a lower electrode 17, the insulating film 18, and an upper electrode 21 which are stacked.
In the selection gate SG, an opening portion 19 is provided in the center portion of the insulating film 18. Therefore, the lower electrode 17 and the upper electrode 21 are electrically connected, and function as a single, integrated, gate electrode. The upper portions of the memory gate MG and the selection gate SG, the space between adjacent memory gates MG, and the space between the memory gate MG and the selection gate SG are covered by an interlayer insulating film 22. A silicon oxide film may be used, for example, as the interlayer insulating film 22.
Air gaps AG are formed between the adjacent memory gates MG, and between the memory gate MG and the selection gate SG. Providing the air gaps AG enables a reduction in the wiring capacitance between the memory gates MG, and between the memory gate MG and the selection gate SG, and it is possible to reduce the adjacent cell interference. The upper surface of the interlayer insulating film 22 is planarized, and a liner film 26 is provided on the upper portion thereof.
Between the adjacent selection gates SG, a side wall insulating film 24 is provided on the side surface of the selection gate SG, and the liner film 26 and the interlayer insulating film 28 are provided on the semiconductor substrate 12. A silicon nitride film may be used, for example, as the liner film 26. The liner film 26 protects the memory cell area M from impurities and hydrogen during the formation of the upper layer wiring, and serves the role of an etching process stopper for adjusting the depth of the contacts in the formation of the contacts (the source line contact SLC and the like). A silicon oxide film may be used, for example, as the interlayer insulating film 28.
The upper surface of the interlayer insulating film 28 is planarized, and the upper surface thereof may be positioned at substantially the same height as the upper surface of the liner film 26. A barrier film 30 is provided on the upper surface of the interlayer insulating film 28, and an interlayer insulating film 32 is provided further above the barrier film 30. A silicon nitride film may be used, for example, as the barrier film 30. The barrier film 30 also includes the role of blocking impurities and hydrogen during the formation of the upper layer wiring. A silicon oxide film may be used, for example, as the interlayer insulating film 32.
Between adjacent selection gates SG, a contact plug 34 (the source line contact SLC) is formed so as to penetrate from the surface of the interlayer insulating film 32 to the surface of the semiconductor substrate 12, and wiring 36 (the source line SL) is provided on the contact plug 34.
Note that, the wiring 36 is formed using the so-called damascene process, and is formed by filling the inside of a wiring groove 62 which is provided in the interlayer insulating film 32 with a metal film. Here, the lower surface of the wiring 36 (the source line SL) does not contact the barrier film 30, and they are separated in the Z direction in the drawing (the up and down directions). The lower surface of the wiring 36 is present in a higher position than the height of the surface of the barrier film 30.
The contact plug 34 and the wiring 36 are formed of a stacked film of a barrier metal and a metal film, for example. Titanium nitride (TiN) may be used, for example, as the barrier metal, and tungsten may be used, for example, as the metal film.
The liner film 26 is formed on the upper portion of the semiconductor substrate 12, the upper portion of the gate electrode PG, and the surface of the side wall insulating film 24. The interlayer insulating film 28 is provided on the liner film 26 on the semiconductor substrate 12. The upper surface of the interlayer insulating film 28 is planarized, and is positioned at substantially the same height as the upper surface of the gate electrode PG. The barrier film 30 is provided on the upper portion, and the interlayer insulating film 32 is provided further above the barrier film 30.
Contact plugs 38 are provided on both sides of the gate electrode PG so as to penetrate from the surface of the interlayer insulating film 32 to the surface of the semiconductor substrate 12, and the wiring 40 is formed on the contact plugs 38. The wiring 40 is formed using the so-called damascene process, and is formed by filling the inside of a wiring groove 63 which is provided in the interlayer insulating film 32 with a metal film. Here, the lower surface of the wiring 40 does not contact the barrier film 30, and they are separated in the Y direction in the drawing. The lower surface of the wiring 40 is present in a higher position than the height of the surface of the barrier film 30.
The wiring 42 is provided to penetrate from the surface of the interlayer insulating film 32 to the barrier film 30. The wiring 42 is formed using the so-called damascene process, and is formed by filling the inside of a wiring groove 64 which is provided in the interlayer insulating film 32 with a metal film.
The lower surface of the wiring 42 (the wiring groove 64) is positioned below, lower than the height of the lower surface of the barrier film 30. The position of the lower surface of the wiring 42 (the wiring groove 64) may match the position of the lower surface of the barrier film 30. The side surface of the wiring 42 (the wiring groove 64) contacts the barrier film 30.
The liner film 26 is formed between the side wall insulating film 24 and the selection gate SG, or on the semiconductor substrate 12 of the peripheral circuit unit. Conversely, the barrier film 30 is formed after the interlayer insulating film 28 is formed between the selection gates SG and on the peripheral circuit unit. Therefore, the barrier film 30 becomes substantially the same height in the peripheral circuit unit regardless of the presence or absence of the gate electrodes of the lower layer. In other words, in the transistor portion of the peripheral circuit unit and the ODT circuit unit, the height of the barrier film 30 (the height position in the Z direction, the height position in the up and down directions) is substantially the same.
Furthermore, the distance from the surface of the semiconductor substrate 12 to the barrier film 30 is substantially equal to the distance from the surface of the semiconductor substrate 12 to the barrier film 30. In addition, the distance from the surface of the semiconductor substrate 12 to the lower surface of the source line 36 is larger than the distance from the surface of the semiconductor substrate 12 to the lower surface of the wiring 42. In addition, the distance from the surface of the semiconductor substrate 12 to the upper surface of the source line 36 is equal to the distance from the surface of the semiconductor substrate 12 to the upper surface of the wirings 40 and 42.
As illustrated in
Within the peripheral circuit unit, a depth D2 of the wiring 40 (the wiring groove 62) outside of the wiring portions of the ODT circuit unit, for example, in the transistor Trp forming area illustrated in
Next, description will be given of the manufacturing method of the NAND flash memory device 100 according to the present embodiment, with reference to
The planar layout of the NAND flash memory device 100 according to the present embodiment is the same as the planar views illustrated in
The charge storage layer 16 and the lower electrode 17 are formed in the same process, and amorphous silicon may be used, for example. The amorphous silicon may be formed using a CVD method, for example. The insulating film 18 is formed of an ONO (Oxide Nitride Oxide) film, which is a stacked film of silicon oxide film/silicon nitride film/silicon oxide film, for example. The ONO film may be formed using the CVD method, for example.
The control gate 20 and the upper electrode 21 are formed in the same process, and a stacked structure of amorphous silicon and a metal film may be used, for example. Tungsten may be used as the metal film, for example. The tungsten may be formed using a sputtering method, for example. In the area where the selection gate SG is subsequently formed, the opening portion 19 is formed in the insulating film 18, and the lower electrode 17 and the upper electrode 21 are electrically connected at this portion.
In the stacked film of the charge storage layer 16, the insulating film 18, and the upper electrode 21, the memory gate MG and the space between the memory gate MG and the selection gate SG are processes using lithography or an RIE (Reactive Ion Etching) method. In the transistor Trp forming area illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, the barrier film 30 is formed. A silicon nitride film may be used, for example, as the barrier film 30. The silicon nitride film may be formed using the CVD method, for example. Here, a film of the same material as the liner film 26 is formed as the barrier film 30. In the present embodiment, silicon nitride films are used for both.
Next, as illustrated in
Next, as illustrated in
In the etching step of the interlayer insulating film 28, the etching is performed under conditions of a high selection ratio between the silicon oxide film of the interlayer insulating film 28 and the silicon nitride film of the liner film 26, and is performed so as to stop on the liner film 26. In the ODT circuit unit illustrated in
Next, as illustrated in
The entire surface of the upper surface of the ODT circuit unit illustrated in
Next, as illustrated in
In the etching step of the interlayer insulating film 32, the etching is performed under conditions of a high selection ratio between the silicon oxide film of the interlayer insulating film 32 and the silicon nitride film of the barrier film 30, and is performed so as to stop on the barrier film 30. Accordingly, since the lower surface of the wiring groove 64 is substantially matched with the height of the upper surface of the barrier film 30, the variation in the depth of the wiring groove 64 may be reduced.
The memory cell area M and upper surface of the transistor Trp forming area illustrated in
Note that, the order of the process illustrated in
Next, as illustrated in
Next, as illustrated in
As described above, the contact plug 34 and the wiring 36, and the contact plug 38 and the wiring 40 are formed integrally. In addition, the metal film may be a stacked film of titanium nitride and tungsten. In this case, the titanium nitride functions as a barrier metal film.
In the above processes, the NAND flash memory device 100 according to the present embodiment is formed. According to the present embodiment, since the variation in the thickness of the wiring 42 may be reduced, the variation in the resistances of the wiring resistors which are formed by the wiring 42 in the peripheral circuit unit may be reduced. In addition, since the wiring 40 depth may be formed shallower than the wiring 42 depth, a large distance may be secured between the lower surface of the wiring 40 and the air gaps AG in the memory cell area M.
Next, description will be given of, within the peripheral circuit unit, the connection state between the transistor Trp forming area illustrated in
As described above, the depth (the film thickness) of the wiring 40 of the transistor Trp forming area and the depth (the film thickness) of the wiring 42 of the ODT circuit unit differ. Therefore, in a layout where both are simply connected, an area of the interlayer insulating film 32 at the seams which is subjected to etching twice is formed; thus, a groove may be formed on these portions. Thus, as illustrated in
Here, the electrical capacitance of the ODT circuit is calculated as the pin capacitance, and when the capacitance is large, the operation speed decreases. Thus, the gate electrode is not disposed below the wiring 42. In addition, by disposing the element isolation insulating film 13 below the wiring 42, the distance between the wiring 42 and the semiconductor substrate 12 is increased. As a result, the wiring capacitance of the wiring 4 may be decreased.
Hereinafter, description will be given of the NAND flash memory device as the semiconductor memory device to which the second embodiment is applied, with reference to
The layout of the memory cell area M, the transistor Trp forming area and the ODT circuit unit of the peripheral circuit unit of the NAND flash memory device 100 according to the second embodiment is the same as the configuration illustrated in
Here, the distance from the surface of the semiconductor substrate 12 to the lower surface of the barrier film 30 is smaller than the distance from the surface of the semiconductor substrate 12 to the lower surface of the barrier film 30. In addition, the distance from the surface of the semiconductor substrate 12 to the lower surface of the wiring 40 is substantially equal to the distance from the surface of the semiconductor substrate 12 to the lower surface of the wiring 42.
In the second embodiment, the wiring 42 of the ODT circuit unit contacts the barrier film 30 in the same manner as in the first embodiment. However, as illustrated in
In addition, the height H1 from the surface of the semiconductor substrate 12 in the memory cell area M illustrated in
Next, description will be given of the manufacturing method of the NAND flash memory device 100 according to the present embodiment, with reference to
First, the processes illustrated using
Bad coverage conditions are used in the film formation of the silicon oxide film. Accordingly, the air gaps AG are formed between the memory gates MG. In the second embodiment, the film thickness of the interlayer insulating film 22 is formed to be thick in comparison to the first embodiment.
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
In the etching step of the interlayer insulating film 32, the etching is performed under conditions of a high selection ratio between the silicon oxide film of the interlayer insulating film 32 and the silicon nitride film of the barrier film 30, and is performed so as to stop on the barrier film 30. Accordingly, since the lower surface of the wiring groove 64 of the ODT circuit unit illustrated in
The wiring groove 62 of the memory cell area M illustrated in
Next, as illustrated in
In addition, a rut (a concave portion) may be formed in the surface of the semiconductor substrate 12 of the lower portion of the contact holes 60 by over etching in the etching. In addition, a rut (a concave portion) may be formed in the surface of the interlayer insulating film 28 of the lower portion of the wiring groove 64 of the ODT circuit unit by over etching in the etching.
Next, as illustrated in
As described above, the contact plug 34 and the wiring 36, and the contact plug 38 and the wiring 40 are formed integrally. In addition, the metal film may be a stacked film of titanium nitride and tungsten. In this case, the titanium nitride functions as a barrier metal film.
In the above processes, the NAND flash memory device 100 according to the present embodiment is formed. According to the present embodiment, the same effect is obtained as in the first embodiment.
Besides those described in the above embodiments, the following modifications may be made.
Description is given exemplifying an example which uses so-called via-first damascene technology in which, in the formation of the contact plugs and the wirings, the contact holes are formed first; however, instead of this, a so-called trench-first damascene technology in which the contact holes are formed after forming the wiring grooves first may be used.
In addition, the present embodiment may also be applied to a structure in which there is no barrier film 30. For example, the liner film 26 may be used instead of the barrier film 30 as the stopper film of the etching process of the wirings 40 and 42 (the wiring grooves 63 and 64). However, in this case, it is necessary to dispose the gate electrodes and the like below the wirings where depth variation is to be suppressed. The gate electrodes may be dummies.
In addition, in the above embodiments, an example in which the embodiment is applied to a NAND flash memory device is illustrated; however, in addition, the embodiment may be applied to a NOR flash memory device, a nonvolatile semiconductor memory device such as EPROM, semiconductor memory devices such as DRAM or SRAM, or a logical semiconductor device such as a micro computer.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is based upon and claims the benefit of priority from U.S. Provisional Patent Application No. 61/952,348, filed Mar. 13, 2014, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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61952348 | Mar 2014 | US |