Patent Application
20240096416
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-143815, filed Sep. 9, 2022, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor memory device.
A NAND flash memory is known as a semiconductor memory device capable of storing data in a nonvolatile manner. A semiconductor memory device such as a NAND flash memory may adopt a three-dimensional memory structure for higher integration and higher capacity.
In general, according to one embodiment, a semiconductor memory device includes: stacked interconnects including a first interconnect layer and a second interconnect layer, the first interconnect layer including a first area and a second area arranged in a first direction, the second interconnect layer being arranged above the first interconnect layer in a second direction intersecting the first direction, the second interconnect layer not including the first area and including the second area; a first memory pillar arranged in the first area and passing through the first interconnect layer in the second direction; and a second memory pillar arranged in the second area and passing through the first interconnect layer and the second interconnect layer in the second direction.
Hereinafter, an embodiment will be described with reference to the accompanying drawings. The dimensions and ratios in the drawings are not always the same as the actual ones. In the following description, constituent elements having substantially the same function and configuration will be assigned the same reference symbol. In the case where elements having similar configurations are distinguished from each other in particular, their identical reference symbols may be assigned different letters or numbers.
A configuration of a memory system including a semiconductor memory device according to an embodiment will be described with reference to
The memory controller 2 is constituted by an integrated circuit such as a system-on-a-chip (SoC), for example. The memory controller 2 controls the semiconductor memory device 3, based on a request received from the host device. Specifically, for example, the memory controller 2 writes data which is requested to be written by the host device to the semiconductor memory device 3. Furthermore, the memory controller 2 reads data which is requested to be read by the host device from the semiconductor memory device 3 and transmits the read data to the host device.
The semiconductor memory device 3 is a memory configured to store data in a nonvolatile manner. The semiconductor memory device 3 is, for example, a NAND flash memory.
A configuration of the semiconductor memory device 3 will be described by continuously referring to
The semiconductor memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.
The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (where n is an integer equal to or greater than 1). The block BLK is a set of a plurality of memory cell transistors capable of storing data in a nonvolatile manner. The block BLK is used as, for example, a data erase unit. In the memory cell array 10, a plurality of bit lines and a plurality of word lines are provided. Each memory cell transistor is associated with, for example, a single bit line and a single word line. A detailed configuration of the memory cell array 10 will be described later.
The command register 11 is a circuit configured to store commands CMD that the semiconductor memory device 3 receives from the memory controller 2. The command CMD includes, for example, an order to cause the sequencer 13 to execute a read operation, a write operation, an erase operation, etc.
The address register 12 is a circuit configured to store addresses ADD that the semiconductor memory device 3 receives from the memory controller 2. The address ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. The block address BAd, the page address PAd, and the column address CAd are used to select, for example, a block BLK, a word line, and a bit line, respectively.
The sequencer 13 is a circuit configured to control an operation of another circuit in accordance with a predetermined program. The sequencer 13 controls the overall operation of the semiconductor memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc., based on the command CMD stored in the command register 11. For example, the sequencer 13 executes the read operation, the write operation, the erase operation, etc.
The driver module 14 is a circuit configured to generate a voltage for use in the read operation, the write operation, the erase operation, etc. The driver module 14 applies, for example, based on the page address PAd stored in the address register 12, the generated voltage to a signal line corresponding to the selected word line.
The row decoder module 15 is a circuit configured to select, based on the block address BAd stored in the address register 12, one of the blocks BLK in the memory cell array 10. The row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.
The sense amplifier module 16 selects a bit line based on the column address CAd stored in the address register 12. In the write operation, the sense amplifier module 16 applies, to the selected bit line, a voltage based on the write data DAT received from the memory controller 2. In the read operation, the sense amplifier module 16 determines data stored in a memory cell transistor based on a voltage of the selected bit line. The sense amplifier module 16 transfers the determination result as the read data DAT to the memory controller 2.
A circuit configuration of the memory cell array 10 will be described with reference to
The block BLK includes, for example, four string units SU0 to SU3. The string unit SU is a set of NAND strings NS to be described later. For example, in the write operation or the read operation, NAND strings NS in the string unit SU are collectively selected.
Each string unit SU includes a plurality of NAND strings NS (memory strings) respectively associated with bit lines BL0 to BLm (where m is an integer equal to or greater than 1). Each NAND string NS in the string unit SU0 includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1a to ST1d and ST2. Each NAND string NS in the string unit SU1 includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1b to ST1d and ST2. Each NAND string NS in the string unit SU2 includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1c, ST1d, and ST2. Each NAND string NS in the string unit SU3 includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1d and ST2. The memory cell transistor MT stores data in a nonvolatile manner. The memory cell transistor MT includes a control gate and a charge storage layer. The select transistors ST1a to ST1d and ST2 are switching elements. Each of the select transistors ST1a to ST1d and ST2 is used to select a string unit SU in various operations. In the following, the select transistors ST1a to ST1d will be simply referred to as “select transistors ST1” in the case where they are not distinguished from each other.
In each NAND string NS, the memory cell transistors MT0 to MT7 are coupled in series. A source of the select transistor ST1d is coupled to one end of the memory cell transistors MT0 to MT7 coupled in series. A drain of the select transistor ST2 is coupled to the other end of the memory cell transistors MT0 to MT7 coupled in series. A source of the select transistor ST2 is coupled to a source line SL. In each NAND string NS within the string unit SU0, the select transistors ST1a to ST1d are coupled in series between their associated bit line BL and one end of the coupled memory cell transistors MT0 to MT7. A drain of the select transistor ST1a is coupled to the bit line BL associated therewith. In each NAND string NS within the string unit SU1, the select transistors ST1b to ST1d are coupled in series between their associated bit line BL and one end of the coupled memory cell transistors MT0 to MT7. A drain of the select transistor ST1b is coupled to the bit line BL associated therewith. In each NAND string NS within the string unit SU2, the select transistors ST1c and ST1d are coupled in series between their associated bit line BL and one end of the coupled memory cell transistors MT0 to MT7. A drain of the select transistor ST1c is coupled to the bit line BL associated therewith. In each NAND string NS within the string unit SU3, a drain of the select transistor Slid is coupled to the bit line BL associated therewith. That is, the select transistor Slid in each NAND string NS within the string unit SU3 is coupled between its associated bit line BL and one end of the coupled memory cell transistors MT0 to MT7.
As described above, each NAND string NS is coupled between each associated bit line BL and the source line SL. Out of the memory cell transistors MT0 to MT7, those corresponding to each other among the plurality of NAND strings NS coupled to the same single bit line BL have their gates coupled to a common word line WL.
The control gates of the memory cell transistors MT0 to MT7 in the same block BLK are respectively coupled to the word lines WL0 to WL7. A gate of the select transistor ST1a in the string unit SU0 is coupled to a select gate line SGD0. Gates of the select transistors ST1b in the string units SU0 and SU1 are coupled to a select gate line SGD1. Gates of the select transistors ST1c in the string units SU0 to SU2 are coupled to a select gate line SGD2. Gates of the select transistors Slid in the string units SU0 to SU3 are coupled to a select gate line SGD3. Gates of the select transistors ST2 in the string units SU0 to SU3 are coupled to a select gate line SGS.
Of the select transistors ST1a to Slid in the NAND string NS within the string unit SU0, the select transistor ST1a has a threshold voltage greater than those of the select transistors ST1b to Slid. Of the select transistors ST1b to Slid in the NAND string NS within the string unit SU1, the select transistor ST1b has a threshold voltage greater than those of the select transistors ST1c and Slid. Of the select transistors ST1c and Slid in the NAND string NS within the string unit SU2, the select transistor ST1c has a threshold voltage greater than that of the select transistor ST1d.
The select transistor Slid in the NAND string NS within the string unit SU3 has a threshold voltage greater than that of the select transistor Slid in each NAND string NS within the string units SU0 to SU2. The select transistor ST1c in the NAND string NS within the string unit SU2 has a threshold voltage greater than that of the select transistor ST1c in each NAND string NS within the string units SU0 and SU1. The select transistor ST1b in the NAND string NS within the string unit SU1 has a threshold voltage greater than that of the select transistor ST1b in the NAND string NS within the string unit SU0. The threshold voltage of each select transistor ST1 will be described later in detail.
The bit lines BL0 to BLm are respectively assigned different column addresses CAd. Each bit line BL is shared by the NAND strings NS assigned the same column address CAd among a plurality of blocks BLK. Each of word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared by, for example, the plurality of blocks BLK.
A set of memory cell transistors MT commonly coupled to a word line WL in one string unit SU may be referred to as a cell unit CU, for example. For example, the storage capacity of the cell unit CU including the memory cell transistors MT respectively configured to store 1-bit data is defined as “1-page data”. The cell unit CU may have a storage capacity of 2-page data or more based on the number of bits of data stored in the memory cell transistors MT.
The circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string units SU included in each block BLK may be any number. The numbers of memory cell transistors MT, select transistors ST1, and select transistors ST2 included in each NAND string NS may be any number, respectively. For example, the number of select transistors ST1 included in each NAND string NS is one or more and equal to or smaller than the number of string units SU included in each block BLK.
The structure of the memory cell array 10 will be described with reference to
The select gate lines SGD0 to SGD3 may each be one or three or more in number. In the case where the select gate lines SGD0 to SGD3 are each one in number, the select gate line group SGDG0 includes one select gate line SGD0. The select gate line group SGDG1 includes one select gate line SGD1. The select gate line group SGDG2 includes one select gate line SGD2. The select gate line group SGDG3 includes one select gate line SGD3. In the case where the select gate lines SGD0 to SGD3 are each three or more in number, the select gate line group SGDG0 includes three or more select gate lines SGD0. The select gate line group SGDG1 includes three or more select gate lines SGD1. The select gate line group SGDG2 includes three or more select gate lines SGD2. The select gate line group SGDG3 includes three or more select gate lines SGD3.
The memory cell array 10 is divided into a memory area MA and a hookup area HA, for example, in the X direction. The memory area MA is adjacent to the hookup area HA in the X direction. The memory area MA and the hookup area HA include interconnects in which the select gate line SGS, the word lines WL0 to WL7, and the select gate line groups SGDG3 to SGDG0 are stacked with a space therebetween in the Z direction sequentially from a lower layer. Hereinafter, a plurality of interconnect layers 22 to 24 (the select gate line SGS, the word lines WL0 to WL7, and the select gate line groups SGDG0 to SGDG3) in which the select gate line SGS, the word lines WL0 to WL7, and the select gate line groups SGDG3 to SGDG0 are stacked with a space therebetween in the Z direction sequentially from a lower layer will be referred to as “stacked interconnects SI”. The memory area MA is an area including the plurality of NAND strings NS. The hookup area HA is an area for use in coupling between the stacked interconnects SI and the row decoder module 15.
The memory cell array 10 includes a plurality of members SLT.
The plurality of members SLT are each formed into, for example, a line shape extending in the X direction and are arranged side by side in the Y direction. The member SLT crosses the memory area MA and the hookup area HA. In other words, the plurality of members SLT extend in the Z direction and the X direction, and divide the stacked interconnects SI in the Y direction while being spaced apart from each other in the Y direction with the stacked interconnects SI interposed therebetween. One block BLK is arranged between two members SLT adjacent to each other in the Y direction. In other words, the member SLT is provided between two blocks BLK adjacent to each other in the Y direction. The member SLT divides the stacked interconnects SI of two blocks BLK adjacent to each other in the Y direction.
The member SLT includes, for example, a contact plug LI and a spacer SP. The contact plug LI is formed into, for example, a line shape extending in the X direction. The contact plug LI electrically couples, for example, the source line SL to an interconnect provided above the memory cell array 10. The contact plug LI is formed of a conductive material and includes, for example, tungsten. The spacer SP is provided on a side surface of the contact plug LI. In other words, the contact plug LI is surrounded by the spacer SP in a planar view in an XY plane. A contact plug LI is isolated and insulated from the stacked interconnects SI adjacent to the contact plug LI in the Y direction by the spacer SP. The spacer SP is formed of an insulating material and includes, for example, silicon oxide. The member SLT may not include the contact plug LI.
In the memory area MA, the plurality of interconnect layers 24 (the select gate lines groups SGDG0 to SGDG3) respectively have terrace portions. In the memory area MA, the terrace portion of the select gate line group SGDG0 corresponds to the upper surface of the select gate line SGD0b. In the memory area MA, the terrace portion of the select gate line group SGDG1 corresponds to the upper surface of the end portion in the Y direction of the select gate line SGD1b. In the memory area MA, the terrace portion of the select gate line group SGDG2 corresponds to the upper surface of the end portion in the Y direction of the select gate line SGD2b. In the memory area MA, the terrace portion of the select gate line group SGDG3 corresponds to the upper surface of the end portion in the Y direction of the select gate line SGD3b.
Above the terrace portion of the interconnect layer 24 functioning as the select gate line SGD3b, six interconnect layers 24 respectively functioning as the select gate lines SGD0a, SGD0b, SGD1a, SGD1b, SGD2a, and SGD2b are eliminated. Above the terrace portion of the interconnect layer 24 functioning as the select gate line SGD2b, four interconnect layers 24 respectively functioning as the select gate lines SGD0a, SGD0b, SGD1a, and SGD1b are eliminated. Above the terrace portion of the interconnect layer 24 functioning as the select gate line SGD1b, two interconnect layers 24 respectively functioning as the select gate lines SGD0a and SGD0b are eliminated. As described above, the memory area MA has a staircase portion in which the end portions in the Y direction of the plurality of interconnect layers 24 (the select gate line groups SGDG0 to SGDG3) are drawn out in a stepwise manner.
With the structure of the select gate line groups SGDG0 to SGDG3 described above, an area between two members SLT adjacent to each other in the Y direction are divided into an area including the select gate line groups SGDG0 to SGDG3, an area including the select gate line groups SGDG1 to SGDG3 and not including the select gate line group SGDG0, an area including the select gate line groups SGDG2 and SGDG3 and not including the select gate line groups SGDG0 and SGDG1, and an area including the select gate line group SGDG3 and not including the select gate line groups SGDG0 to SGDG2. These areas correspond to the string units SU0 to SU3, respectively.
In each of the blocks BLK0 and BLK1, the string units SU0 to SU3 are arranged in the order of the string unit SU0, the string unit SU1, the string unit SU2, and the string unit SU3 from the side of the member SLT between the block BLK0 and the block BLK1 in the Y direction.
In the memory area MA, the memory cell array 10 includes, for example, a plurality of memory pillars MP, a plurality of contact plugs CV, and a plurality of interconnect layers 25 (bit lines BL).
The memory pillar MP functions as a single NAND string NS. The plurality of memory pillars MP are arranged in, for example, a 16-row staggered pattern in each area between two members SLT adjacent to each other in the Y direction.
The plurality of bit lines BL are each formed into, for example, a line shape extending in the Y direction and are arranged side by side in the X direction. The bit lines BL are arranged in such a manner as to be located above at least one memory pillar MP for each string unit SU. The example in
In the hookup area HA, the plurality of interconnect layers 22 to 24 (the select gate line SGS, the word lines WL0 to WL7, and the select gate line groups SGDG0 to SGDG3) respectively have terrace portions. In the hookup area HA, the terrace portions of the plurality of interconnect layers 22 to 24 (the select gate line SGS, the word lines WL0 to WL7, and the select gate line groups SGDG0 to SGDG3) correspond to the upper surfaces of the end portions in the X direction of the interconnect layers 22 to 24. Each of these terrace portions is an area provided with a contact plug (not shown) for electrically coupling the plurality of interconnect layers 22 to 24 to an interconnect provided above the memory cell array 10. As described above, the hookup area HA has the staircase portion in which the respective end portions in the X direction of the stacked interconnects SI (the select gate line SGS, the word lines WL0 to WL7, and the select gate line group SGDG0 to SGDG3) are drawn out in a stepwise manner. In the hookup area HA, the stacked interconnects SI may not have the staircase portion.
The planar structure of the memory cell array 10 is not limited to the structure described above. For example, the number of select gate line groups SGDG may be any number based on the number of string units SU.
In the memory area MA, the memory cell array 10 further includes, for example, a semiconductor substrate 20, an interconnect layer 21, and insulating layers 30 to 34.
The insulating layer 30 is provided on the semiconductor substrate 20. The insulating layer 30 includes, for example, a circuit (not shown) corresponding to the row decoder module 15, the sense amplifier module 16, etc. The insulating layer 30 is formed of an insulating material and includes, for example, silicon oxide. The interconnect layer 21 is provided on the insulating layer 30. The interconnect layer 21 is formed into, for example, a plate shape extending along the XY plane, and is used as a source line SL. The interconnect layer 21 is formed of a conductive material and includes, for example, silicon doped with phosphorus.
The insulating layer 31 is provided on the interconnect layer 21. The insulating layer 31 is formed of an insulating material and includes, for example, silicon oxide. The interconnect layer 22 is provided on the insulating layer 31. The interconnect layer 22 is formed into, for example, a plate shape extending along the XY plane. The interconnect layer 22 is used as the select gate line SGS. The interconnect layer 22 is formed of a conductive material and includes, for example, tungsten.
A plurality of insulating layers 32 and the plurality of interconnect layers 23 are alternately stacked one by one on the interconnect layer 22. In other words, the plurality of interconnect layers 23 with a space therebetween in the Z direction are provided above the interconnect layer 22. The interconnect layer 23 is formed into, for example, a plate shape extending along the XY plane. The plurality of interconnect layers 23 are respectively used as the word lines WL0 to WL7, in the order from the side of the semiconductor substrate 20. The insulating layer 32 is formed of an insulating material and includes, for example, silicon oxide. The interconnect layer 23 is formed of a conductive material and includes, for example, tungsten.
A plurality of insulating layers 33 and the plurality of interconnect layers 24 are alternately stacked one by one on the uppermost interconnect layer 23 (that is, the word line WL7). In other words, the plurality of interconnect layers 24 with a space therebetween in the Z direction are provided above the uppermost interconnect layer 23. The interconnect layer 24 is formed into, for example, a plate shape extending along the XY plane. The plurality of interconnect layers 24 are respectively used as the select gate lines SGD3a, SGD3b, SGD2a, SGD2b, SGD1a, SGD1b, SGD0a, and SGD0b in the order from the side of the semiconductor substrate 20. The insulating layer 33 is formed of an insulating material and includes, for example, silicon oxide. The interconnect layer 24 is formed of a conductive material and includes, for example, tungsten.
The example in
Furthermore, the string unit SU0 includes the select gate line groups SGDG0 to SGDG3 (the select gate lines SGD0a, SGD0b, SGD1a, SGD1b, SGD2a, SGD2b, SGD3a, and SGD3b). The string unit SU1 includes the select gate line groups SGDG1 to SGDG3 (the select gate lines SGD1a, SGD1b, SGD2a, SGD2b, SGD3a, and SGD3b) and does not include the select gate line group SGDG0. The string unit SU2 includes the select gate line groups SGDG2 and SGDG3 (the select gate lines SGD2a, SGD2b, SGD3a, and SGD3b) and does not include the select gate line groups SGDG0 and SGDG1. The string unit SU3 includes the select gate line group SGDG3 (the select gate lines SGD3a and SGD3b) and does not include the select gate line groups SGDG0 to SGDG2.
In other words, the select gate lines SGD0a and SGD0b are included in the string unit SU0 and are not included in the string units SU1 to SU3. The select gate lines SGD1a and SGD1b are included in the string units SU0 and SU1 and are not included in the string units SU2 and SU3. The select gate lines SGD2a and SGD2b are included in the string units SU0 to SU2 and are not included in the string unit SU3. The select gate lines SGD3a and SGD3b are included in the string units SU0 to SU3.
The insulating layer 33 is provided on the uppermost interconnect layer 24 within each string unit SU. The insulating layer 34 is provided on the uppermost insulating layer 33 within each string unit SU. The insulating layer 34 is formed of an insulating material and includes, for example, silicon oxide.
The interconnect layer 25 is provided on the insulating layer 34. The interconnect layer 25 is formed into, for example, a line shape extending in the Y direction, and is used as the bit line BL. The interconnect layer 25 is formed of a conductive material and includes, for example, copper.
The memory pillar MP extends in the Z direction. The memory pillar MP penetrates (passes through) the insulating layers 31 to 33 and the interconnect layers 22 to 24. The memory pillar MP is formed into, for example, a cylindrical shape. A lower end of the memory pillar MP is in contact with the interconnect layer 21.
A portion (intersecting portion) in which the memory pillar MP intersects the interconnect layer 22 functions as the select transistor ST2. A portion in which the memory pillar MP intersects the single interconnect layer 23 (the interconnect layer arranged below the interconnect layer 24 in the Z direction) functions as the memory cell transistor MT. In other words, the memory cell transistor MT is formed in a portion in which the memory pillar MP (the semiconductor layer 41 to be described later) intersects the single interconnect layer 23. A portion in which the memory pillar MP intersects two interconnect layers 24 (the select gate line groups SGDG) functions as the select transistor ST1. In other words, the select transistor ST1 is formed in the portion in which the memory pillar MP (the semiconductor layer 41 to be described later) intersects two interconnect layers 24 (the select gate line group SGDG). That is, the select transistor ST1a is formed in the portion in which the memory pillar MP intersects the select gate line groups SGDG0. The select transistor ST1b is formed in the portion in which the memory pillar MP intersects the select gate line group SGDG1. The select transistor ST1c is formed in the portion in which the memory pillar MP intersects the select gate line group SGDG2. The select transistor ST1d is formed in the portion in which the memory pillar MP intersects the select gate line group SGDG3.
The memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42.
The core member 40 extends in the Z direction. For example, an upper end of the core member 40 is located above the uppermost interconnect layer 24 within each string unit SU, and a lower end of the core member 40 is located above the interconnect layer 21. The core member 40 is formed of an insulating material and includes, for example, silicon oxide.
The semiconductor layer 41 covers the periphery of the core member 40. In the lower end of the memory pillar MP, the semiconductor layer 41 is partially in contact with the interconnect layer 21. The semiconductor layer 41 penetrates (passes through) the insulating layers 31 to 33 and the interconnect layers 22 to 24 in the Z direction. The semiconductor layer 41 includes, for example, silicon.
The stacked film 42 covers the side and bottom surfaces of the semiconductor layer 41 except for the portion in which the semiconductor layer 41 and the interconnect layer 21 are in contact with each other.
An upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU0 is located above an upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU1 in the Z direction. The upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU1 is located above an upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU2 in the Z direction. The upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU2 is located above an upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU3 in the Z direction.
In other words, the upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU1 is located between the select gate line SGD1b and the select gate line SGD0a (SGD0b) in the Z direction. The upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU0 is located above the select gate line SGD0a (SGD0b). The upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU2 is located between the select gate line SGD2b and the select gate line SGD1a (SGD1b) in the Z direction. The upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU1 is located above the select gate line SGD1a (SGD1b). The upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU3 is located between the select gate line SGD3b and the select gate line SGD2a (SGD2b) in the Z direction. The upper end of the memory pillar MP (the semiconductor layer 41) within the string unit SU2 is located above the select gate line SGD2a (SGD2b).
Furthermore, the memory pillar MP arranged in the string unit SU0 penetrates the select gate lines SGD3a, SGD3b, SGD2a, SGD2b, SGD1a, SGD1b, SGD0a, and SGD0b in the Z direction. The memory pillar MP arranged in the string unit SU1 penetrates the select gate lines SGD3a, SGD3b, SGD2a, SGD2b, SGD1a, and SGD1b and does not penetrate the select gate lines SGD0a SGD0b in the Z direction. The memory pillar MP arranged in the string unit SU2 penetrates the select gate lines SGD3a, SGD3b, SGD2a, and SGD2b and does not penetrate the select gate lines SGD1a, SGD1b, SGD0a and SGD0b in the Z direction. The memory pillar MP arranged in the string unit SU3 penetrates the select gate lines SGD3a and SGD3b and does not penetrate the select gate lines SGD2a, SGD2b, SGD1a, SGD1b, SGD0a, and SGD0b in the Z direction.
The select gate line SGD0b is an interconnect layer 24 positioned first from the upper end of the memory pillar MP within the string unit SU0. The select gate line SGD1b is an interconnect layer 24 positioned first from the upper end of the memory pillar MP within the string unit SU1. The select gate line SGD2b is an interconnect layer 24 positioned first from the upper end of the memory pillar MP within the string unit SU2. The select gate line SGD3b is an interconnect layer 24 positioned first from the upper end of the memory pillar MP within the string unit SU3.
A height from the upper end of the memory pillar MP within the string unit SU1 to the select gate line SGD1b is approximately equal to, for example, a height from the upper end of the memory pillar MP within the string unit SU0 to the select gate line SGD0b. The same applies to a height from the upper end of the memory pillar MP within the string unit SU2 to the select gate line SGD2b, and a height from the upper end of the memory pillar MP within the string unit SU3 to the select gate line SGD3b.
The contact plug CV is provided on the semiconductor layer 41. The contact plug CV is formed into, for example, a columnar shape extending in the Z direction. An upper end of the contact plug CV is in contact with the interconnect layer 25. The contact plug CV electrically couples the memory pillar MP (the semiconductor layer 41) to the interconnect layer 25 provided above the memory cell array 10. A length in the Z direction of the contact plug CV is different for each string unit SU. Specifically, a length in the Z direction of the contact plug CV within the string unit SU0 is smaller than that of the contact plug CV within the string unit SU1. The length in the Z direction of the contact plug CV within the string unit SU1 is smaller than that of the contact plug CV within the string unit SU2. The length in the Z direction of the contact plug CV within the string unit SU2 is smaller than that of the contact plug CV within the string unit SU3. In the cross-sectional structure shown in
The members SLT extend in the Z direction. The member SLT penetrates the insulating layers 31 to 33 and the interconnect layers 22 to 24. A lower end of the member SLT is in contact with the interconnect layer 21. The contact plug LI is provided along the member SLT. An upper end of the contact plug LI is located above the upper end of the memory pillar MP. The upper end of the contact plug LI is not in contact with the interconnect layer 25. A lower end of the contact plug LI is in contact with the interconnect layer 21. The spacer SP covers the periphery of the contact plug LI. The contact plug LI is isolated and insulated from the interconnect layers 22 to 24 by the spacer SP.
With the above structure, the YZ plane of the stacked interconnects SI across two blocks BLK adjacent to each other in the Y direction takes a symmetric shape in which the member SLT provided between these blocks BLK serves the center axis.
The core member 40 is provided in the central portion of the memory pillar MP. The semiconductor layer 41 covers the periphery of the core member 40. The tunnel insulating film 43 covers the periphery of the semiconductor layer 41. The tunnel insulating film 43 is formed of an insulating material and includes, for example, silicon oxynitride (SiON). The insulating film 44 covers the periphery of the tunnel insulating film 43. The insulating film 44 functions as a charge storage layer of the memory cell transistor MT. The insulating film 44 is formed of an insulating material and includes, for example, silicon nitride. The block insulating film 45 covers the periphery of the insulating film 44. The block insulating film 45 is formed of an insulating material and includes, for example, silicon oxide. The interconnect layer 23 covers the periphery of the block insulating film 45. Meanwhile, a metal oxide such as an aluminum oxide may be further provided between the block insulating film 45 and the interconnect layer 23 in the cross-sectional structure shown in
A threshold voltage of the select transistor ST1 will be described with reference to
As described above, the select transistor ST1a is formed in the portion in which the select gate line group SGDG0 intersects with the memory pillar MP. The select transistor SIM is formed in the portion in which the select gate line group SGDG1 intersects the memory pillar MP. The select transistor ST1c is formed in the portion in which the select gate line group SGDG2 intersects the memory pillar MP. The select transistor ST1d is formed in the portion in which the select gate line group SGDG3 intersects the memory pillar MP.
In the string unit SU0, an area corresponding to the select gate line group SGDG0 of each memory pillar MP is doped with boron. In other words, the memory pillar MP (the semiconductor layer 41) has an area surrounded by the select gate lines SGD0a and SGD0b and the insulating layer 33 between the select gate lines SGD0a and SGD0b (for example, the semiconductor layer 41 of the memory pillar MP, surrounded by a layer from a lower end of the select gate line SGD0a to an upper end of the select gate line SGD0b), and this area is doped with boron. Therefore, in the string unit SU0, the area corresponding to the select gate line group SGDG0 is greater in boron concentration than an area corresponding to the select gate line group SGDG1, an area corresponding to the select gate line group SGDG2, and an area corresponding to the select gate line group SGDG3.
In the string unit SU1, an area corresponding to the select gate line group SGDG1 of each memory pillar MP is doped with boron. In other words, the memory pillar MP (the semiconductor layer 41) has an area surrounded by the select gate lines SGD1a and SGD1b and the insulating layer 33 between the select gate lines SGD1a and SGD1b (for example, the semiconductor layer 41 of the memory pillar MP, surrounded by a layer from a lower end of the select gate line SGD1a to an upper end of the select gate line SGD1b), and this area is doped with boron. Therefore, in the string unit SU1, the area corresponding to the select gate line group SGDG1 is greater in boron concentration than an area corresponding to the select gate line group SGDG2, and an area corresponding to the select gate line group SGDG3.
In the string unit SU2, an area corresponding to the select gate line group SGDG2 of each memory pillar MP is doped with boron. In other words, the memory pillar MP (the semiconductor layer 41) has an area surrounded by the select gate lines SGD2a and SGD2b and the insulating layer 33 between the select gate lines SGD2a and SGD2b (for example, the semiconductor layer 41 of the memory pillar MP, surrounded by a layer from a lower end of the select gate line SGD2a to an upper end of the select gate line SGD2b), and this area is doped with boron. Therefore, in the string unit SU2, the area corresponding to the select gate line group SGDG2 is greater in boron concentration than an area corresponding to the select gate line group SGDG3.
In the string unit SU3, an area corresponding to the select gate line group SGDG3 of each memory pillar MP is doped with boron. In other words, the memory pillar MP (the semiconductor layer 41) has an area surrounded by the select gate lines SGD3a and SGD3b and the insulating layer 33 between the select gate lines SGD3a and SGD3b (for example, the semiconductor layer 41 of the memory pillar MP, surrounded by a layer from a lower end of the select gate line SGD3a to an upper end of the select gate line SGD3b), and this area is doped with boron.
A concentration of boron of an area in the memory pillar MP (the semiconductor layer 41) within the string unit SU0, in which the area is surrounded by the select gate lines SGD0a and SGD0b and the insulating layer 33 between the select gate lines SGD0a and SGD0b, is approximately equal to that of an area in the memory pillar MP (the semiconductor layer 41) within the string unit SU1, in which the area is surrounded by the select gate lines SGD1a and SGD1b and the insulating layer 33 between the select gate lines SGD1a and SGD1b. The same applies to a concentration of boron of an area in the memory pillar MP (the semiconductor layer 41) within the string unit SU2, in which the area is surrounded by the select gate lines SGD2a and SGD2b and the insulating layer 33 between the select gate lines SGD2a and SGD2b. The same applies to a concentration of boron of an area in the memory pillar MP (the semiconductor layer 41) within the string unit SU3, in which the area is surrounded by the select gate lines SGD3a and SGD3b and the insulating layer 33 between the select gate lines SGD3a and SGD3b.
As described above, in each string unit SU, each memory pillar MP has an area corresponding to the uppermost select gate line group SGDG, and this area is doped with boron. In other words, in the aforementioned area, the semiconductor layer 41 of the memory pillar MP (a channel area of the select transistor ST1) includes boron. The threshold voltage Vth of the select transistor ST1 varies depending on the concentration of an impurity in the channel area. In the case where the area is doped with boron as the impurity, the threshold voltage Vth of the select transistor ST1 become greater as the concentration of boron increases.
By the area being doped with boron as described above, in the string unit SU0, a threshold voltage Vth of the select transistor ST1a is greater than those of the select transistor ST1b, the select transistor ST1c, and the select transistor ST1d. In the string unit SU1, the threshold voltage Vth of the select transistor ST1b is greater than those of the select transistor ST1c and the select transistor ST1d. In the string unit SU2, the threshold voltage Vth of the select transistor ST1c is greater than that of the select transistor ST1d. In other words, in each string unit SU including the plurality of select gate line groups SGDG, the threshold value Vth of the select transistor ST1 corresponding to the uppermost select gate line group SGDG is greater than those of the select transistors ST1 corresponding to the select gate line groups SGDG lower than the uppermost select gate line group SGDG.
The threshold voltage Vth of the select transistor ST1a within the string unit SU0 is approximately equal to that of the select transistor ST1b within the string unit SU1, for example. The same applies to the threshold value Vth of the select transistor ST1c within the string unit SU2, and the threshold value Vth of the select transistor ST1d within the string unit SU3.
In the select gate line group SGDG1, the threshold voltage Vth of the select transistor ST1b within the string unit SU1 is greater than that of the select transistor SIM within the string unit SU0. In the select gate line group SGDG2, the threshold voltage Vth of the select transistor ST1c within the string unit SU2 is greater than those of the select transistor ST1c within the string unit SU0 and the select transistor ST1c within the string unit SU1. In the select gate line group SGDG3, the threshold voltage Vth of the select transistor ST1d within the string unit SU3 is greater than those of the select transistor ST1d within the string unit SU0, the select transistor ST1d within the string unit SU1, and the select transistor ST1d within the string unit SU2.
The example in
The operation principle of selecting a string unit SU will be described with reference to
In the example shown in
In the string unit SU0, the voltage (=15 V) applied to the select gate line group SGDG0 is smaller than the threshold voltage Vth (=20 V) of the select transistor ST1a corresponding to the select gate line group SGDG0, so that the select transistor ST1a is turned off. The voltage (=15 V) applied to the select gate line group SGDG1 is greater than the threshold voltage Vth (=10 V) of the select transistor ST1b corresponding to the select gate line group SGDG1, so that the select transistor ST1b is turned on. The voltage (=15 V) applied to the select gate line group SGDG2 is greater than the threshold voltage Vth (=10 V) of the select transistor ST1c corresponding to the select gate line group SGDG2, so that the select transistor ST1c is turned on. The voltage (=15 V) applied to the select gate line group SGDG3 is greater than the threshold voltage Vth (=10 V) of the select transistor Slid corresponding to the select gate line group SGDG3, so that the select transistor Slid is turned on. Since the select transistor ST1a is not turned on, the string unit SU0 is not selected.
In the string unit SU1, the voltage (=15 V) applied to the select gate line group SGDG1 is smaller than the threshold voltage Vth (=20 V) of the select transistor ST1b corresponding to the select gate line group SGDG1, so that the select transistor ST1b is turned off. The voltage (=15 V) applied to the select gate line group SGDG2 is greater than the threshold voltage Vth (=10 V) of the select transistor ST1c corresponding to the select gate line group SGDG2, so that the select transistor ST1c is turned on. The voltage (=15 V) applied to the select gate line group SGDG3 is greater than the threshold voltage Vth (=10 V) of the select transistor Slid corresponding to the select gate line group SGDG3, so that the select transistor Slid is turned on. Since the select transistor ST1b is not turned on, the string unit SU1 is not selected.
In the string unit SU2, the voltage (=15 V) applied to the select gate line group SGDG2 is smaller than the threshold voltage Vth (=20 V) of the select transistor ST1c corresponding to the select gate line group SGDG2, so that the select transistor ST1c is turned off. The voltage (=15 V) applied to the select gate line group SGDG3 is greater than the threshold voltage Vth (=10 V) of the select transistor Slid corresponding to the select gate line group SGDG3, so that the select transistor Slid is turned on. Since the select transistor ST1c is not turned on, the string unit SU2 is not selected.
In the string unit SU3, the voltage (=15 V) applied to the select gate line group SGDG3 is smaller than the threshold voltage Vth (=20 V) of the select transistor Slid corresponding to the select gate line group SGDG3, so that the select transistor Slid is turned off. Since the select transistor Slid is not turned on, the string unit SU3 is not selected.
By the operation described above, none of the string units SU is selected.
In the example shown in
In the string unit SU0, the voltage (=25 V) applied to the select gate line group SGDG0 is greater than the threshold voltage Vth (=20 V) of the select transistor ST1a corresponding to the select gate line group SGDG0, so that the select transistor ST1a is turned on. The select transistor SIM corresponding to the select gate line group SGDG1, the select transistor ST1c corresponding to the select gate line group SGDG2, and the select transistor ST1d corresponding to the select gate line group SGDG3 are turned on as with the example shown in
In the string unit SU1, the select transistor ST1b corresponding to the select gate line group SGDG1 is turned off as with the example shown in
In the string unit SU2, the select transistor ST1c corresponding to the select gate line group SGDG2 is turned off as with the example shown in
In the string unit SU3, the select transistor ST1d corresponding to the select gate line group SGDG3 is turned off as with the example shown in
By the operation described above, the string unit SU0 is selected.
In the example shown in
In the string unit SU0, the select transistor ST1a corresponding to the select gate line group SGDG0 is turned off as with the example shown in
In the string unit SU1, the voltage (=25 V) applied to the select gate line group SGDG1 is greater than the threshold voltage Vth (=20 V) of the select transistor ST1b corresponding to the select gate line group SGDG1, so that the select transistor ST1b is turned on. The select transistor ST1c corresponding to the select gate line group SGDG2 and the select transistor ST1d corresponding to the select gate line group SGDG3 are turned on as with the example shown in
In the string unit SU2, the select transistor ST1c corresponding to the select gate line group SGDG2 is turned off as with the example shown in
In the string unit SU3, the select transistor ST1d corresponding to the select gate line group SGDG3 is turned off as with the example shown in
By the operation described above, the string unit SU1 is selected.
In the example shown in
In the string unit SU0, the select transistor ST1a corresponding to the select gate line group SGDG0 is turned off as with the example shown in
In the string unit SU1, the select transistor ST1b corresponding to the select gate line group SGDG1 is turned off as with the example shown in
In the string unit SU2, the voltage (=25 V) applied to the select gate line group SGDG2 is greater than the threshold voltage Vth (=20 V) of the select transistor ST1c corresponding to the select gate line group SGDG2, so that the select transistor ST1c is turned on. The select transistor ST1d corresponding to the select gate line group SGDG3 is turned on as with the example shown in
In the string unit SU3, the select transistor ST1d corresponding to the select gate line group SGDG3 is turned off as with the example shown in
By the operation described above, the string unit SU2 is selected.
In the example shown in
In the string unit SU0, the select transistor ST1a corresponding to the select gate line group SGDG0 is turned off as with the example shown in
In the string unit SU1, the select transistor ST1b corresponding to the select gate line group SGDG1 is turned off as with the example shown in
In the string unit SU2, the select transistor ST1c corresponding to the select gate line group SGDG2 is turned off as with the example shown in
In the string unit SU3, the voltage (=25 V) applied to the select gate line group SGDG3 is greater than the threshold voltage Vth (=20 V) of the select transistor Slid corresponding to the select gate line group SGDG3, so that the select transistor Slid is turned on. As a result, the string unit SU3 is selected.
By the operation described above, the string unit SU3 is selected.
The method of manufacturing the semiconductor device 3 will be described with reference to
As shown in
As a method of forming the interconnect layers 22 to 24, there exists a method of forming the interconnect layers 22 to 24 by forming a structure corresponding to the interconnect layers 22 to 24 using sacrificial layers and thereafter replacing the sacrificial layers with a conductive material (hereinafter referred to as “replacement”). In the present embodiment, a sacrificial layer 52 corresponds to the interconnect layer 22, a sacrificial layer 53 corresponds to the interconnect layer 23, and a sacrificial layer 54 corresponds to the interconnect layer 24. The sacrificial layers 52 to 54 are formed of an insulating material and include, for example, a silicon nitride.
As shown in
Next, the upper surfaces of the stacked portion and the memory pillars MP are processed in a stepwise manner (S101). Specifically, first, as shown in
Next, as shown in
For example, the first and second sacrificial layers, two insulating layers, and the memory pillars MP in the string unit SU3 are processed in such a manner that a height from an upper end of the area corresponding to the string unit SU3 of the stacked portion to the third sacrificial layer 54 and a height from the aforementioned upper end to the fourth sacrificial layer 54 become approximately equal to a height from an upper end of the area corresponding to the string unit SU2 of the stacked portion to the first sacrificial layer 54 and a height from the aforementioned upper end to the second sacrificial layer 54, respectively. At this time, the amount of etching is set such that the third sacrificial layer 54 remains unexposed in the area corresponding to the string unit SU3. In this manner, the layers higher than the insulating layer 33 provided on the third sacrificial layer 54 are partially removed in the area corresponding to the string unit SU3.
Next, as shown in
Next, as shown in
For example, the third and fourth sacrificial layers, two insulating layers, and the memory pillars MP in the string unit SU3 are processed in such a manner that a height from the upper end of the area corresponding to the string unit SU3 of the stacked portion to the fifth sacrificial layer 54 and a height from the aforementioned upper end to the sixth sacrificial layer 54 become approximately equal to a height from an upper end of the area corresponding to the string unit SU1 of the stacked portion to the first sacrificial layer 54 and a height from the aforementioned upper end to the second sacrificial layer 54, respectively. The first and second sacrificial layers, two insulating layers, and the memory pillars MP in the string unit SU2 are processed in such a manner that a height from the upper end of the area corresponding to the string unit SU2 of the stacked portion to the third sacrificial layer 54 and a height from the aforementioned upper end to the fourth sacrificial layer 54 become approximately equal to the height from the upper end of the area corresponding to the string unit SU1 of the stacked portion to the first sacrificial layer 54 and the height from the aforementioned upper end to the second sacrificial layer 54, respectively. At this time, the amount of etching is set such that the third sacrificial layer 54 remains unexposed in the area corresponding to the string unit SU2, and the fifth sacrificial layer 54 remains unexposed in the area corresponding to the string unit SU3. In this manner, the layers higher than the insulating layer 33 provided on the third sacrificial layer 54 are partially removed in the area corresponding to the string unit SU2. The layers higher than the insulating layer 33 provided on the fifth sacrificial layer 54 are partially removed in the area corresponding to the string unit SU3.
Next, as shown in
Next, as shown in
For example, the fifth and sixth sacrificial layers, two insulating layers, and the memory pillars MP in the string unit SU3 are processed in such a manner that a height from the upper end of the area corresponding to the string unit SU3 of the stacked portion to the seventh sacrificial layer 54 and a height from the aforementioned upper end to the eighth sacrificial layer 54 become approximately equal to a height from an upper end of the area corresponding to the string unit SU0 of the stacked portion to the first sacrificial layer 54 and a height from the aforementioned upper end to the second sacrificial layer 54, respectively. The third and fourth sacrificial layers, two insulating layers, and the memory pillars MP in the string unit SU2 are processed in such a manner that a height from the upper end of the area corresponding to the string unit SU2 of the stacked portion to the fifth sacrificial layer 54 and a height from the aforementioned upper end to the sixth sacrificial layer 54 become approximately equal to the height from the upper end of the area corresponding to the string unit SU0 of the stacked portion to the first sacrificial layer 54 and the height from the aforementioned upper end to the second sacrificial layer 54, respectively. The first and second sacrificial layers, two insulating layers, and the memory pillars MP in the string unit SU1 are processed in such a manner that a height from the upper end of the area corresponding to the string unit SU1 of the stacked portion to the third sacrificial layer 54 and a height from the aforementioned upper end to the fourth sacrificial layer 54 become approximately equal to the height from the upper end of the area corresponding to the string unit SU0 of the stacked portion to the first sacrificial layer 54 and the height from the aforementioned upper end to the second sacrificial layer 54, respectively. At this time, the amount of etching is set such that the third sacrificial layer 54 remains unexposed in the area corresponding to the string unit SU1, the fifth sacrificial layer 54 remains unexposed in the area corresponding to the string unit SU2, and the seventh sacrificial layer 54 remains unexposed in the area corresponding to the string unit SU3. In this manner, the layers higher than the insulating layer 33 provided on the third sacrificial layer 54 are partially removed in the area corresponding to the string unit SU1. The layers higher than the insulating layer 33 provided on the fifth sacrificial layer 54 are partially removed in the area corresponding to the string unit SU2. The layers higher than the insulating layer 33 provided on the seventh sacrificial layer 54 are partially removed in the area corresponding to the string unit SU3.
Next, as shown in
Next, as shown in
Specifically, first, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Through the manufacturing process described above, the memory area MA of the semiconductor memory device 3 is formed. The manufacturing process described above is merely an example and is not limited thereto. For example, another step may be inserted between the respective manufacturing steps or a part of the steps may be omitted or integrated. Furthermore, the respective manufacturing steps may be interchanged where possible. For example, after injection of boron ions, the semiconductor layer 41 may be formed on the upper surface of the core member 40 of each memory pillar MP.
According to the present embodiment, the degree of cell integration can be improved. The advantageous effects will be described below.
As a structure in which the select gate line SGD is divided for each string unit SU, there exists a structure in which the select gate line SGD is physically divided for each string unit SU by providing dummy memory pillars MP (hereinafter referred to as “dummy pillars”) in the memory area MA and further providing members (hereinafter referred to as “members SHE”) for dividing the select gate line SGD in such a manner as to overlap the dummy pillars. This structure is provided with the dummy pillars and thus there is a possibility that the degree of cell integration becomes lower.
On the other hand, in the present embodiment, the string unit SU3 includes the select gate line group SGDG3. The string unit SU2 includes the select gate line group SGDG3 and the select gate line group SGDG2 arranged above the select gate line group SGDG3. The string unit SU1 includes the select gate line groups SGDG2 and SGDG3, and the select gate line group SGDG1 arranged above the select gate line group SGDG2. The string unit SU0 includes the select gate line groups SGDG1 to SGDG3, and the select gate line group SGDG0 arranged above the select gate line group SGDG1.
In the string unit SU3, the area corresponding to the select gate line group SGDG3 of the memory pillar MP is doped with boron. In the string unit SU2, the area corresponding to the select gate line group SGDG2 of the memory pillar MP is doped with boron. In the string unit SU1, the area corresponding to the select gate line group SGDG1 of the memory pillar MP is doped with boron. In the string unit SU0, the area corresponding to the select gate line group SGDG0 of the memory pillar MP is doped with boron. The select transistor ST1 in the area doped with boron is greater in threshold voltage than the select transistor ST1 in the area not doped with boron. Therefore, one string unit SU can be selected by controlling the voltage to be applied to each select gate line group SGDG. This enables the select gate line SGD to be electrically divided for each string unit SU. Therefore, the dummy pillars and the members SHE may not be provided in the memory area MA. Thus, according to the present embodiment, the degree of cell integration can be improved.
In the present embodiment, the members SHE is not provided, so that the interconnect layer 24 is not divided by them. Therefore, as shown in
Furthermore, with the aforementioned structure in which the select gate line SGD is physically divided for each string unit SU, the members SHE are formed after formation of the slits SH. The bottom surface of each slit SH reaches the interconnect layer 21. Therefore, as the number of stacked layers for the memory cell array 10 increases, the slits SH increase in aspect ratio. This causes a possibility that an incline will occur in the stacked interconnects SI. In the case where such an incline occurs, displacement may occur in positioning of the members SHE and the dummy pillars at the time of formation of the members SHE.
On the other hand, in the present embodiment, before formation of the slits SH, boron ions are injected into each memory pillar MP to the depth of the lower end of the sacrificial layer 54 positioned second from the upper end of the memory pillar MP in each string unit SU. Thus, according to the present embodiment, the structure in which the select gate line SGD is divided for each string unit SU can avoid an influence of an occurrence of an incline. Furthermore, the members SHE may not be provided in the memory area MA. Thus, according to the present embodiment, the degree of difficulty in process can be reduced.
Furthermore, in a case of electrically dividing the select gate line SGD for each string unit SU by controlling an applied voltage according to a threshold voltage set in the select transistor ST1, in the case where heights of the memory pillars MP are equal among the string units SU, ion injection into each memory pillar MP is executed independently by changing the acceleration voltage for each string unit SU. In this manner, a desired area with a different depth from the upper end of each memory pillar MP for each string unit SU can be doped with boron.
On the other hand, in the present embodiment, in each string unit SU, the depth to the sacrificial layer 54 positioned first from the upper end of the memory pillar MP and the depth to the sacrificial layer 54 positioned second from the upper end of the memory pillar MP are approximately equal to each other. Accordingly, one ion injection using the acceleration voltage of one type enables boron ions to be injected collectively into a desired area in the memory pillars MP to the depth of the lower end of the sacrificial layer 54 positioned second from the upper end of each memory pillar MP. Thus, according to the present embodiment, the process can be simplified.
As described above, a semiconductor memory device according to an embodiment includes: stacked interconnects (SI) including a first interconnect layer (SGD3) and a second interconnect layer (SGD2), the first interconnect layer (SGD3) including a first area (SU3) and a second area (SU2) arranged in a first direction (Y), the second interconnect layer (SGD2) being arranged above the first interconnect layer in a second direction (Z) intersecting the first direction, the second interconnect layer not including the first area and including the second area; a first memory pillar (MP of SU3) arranged in the first area (SU3) and passing through the first interconnect layer (SGD3) in the second direction (Z); and a second memory pillar (MP of SU2) arranged in the second area (SU2) and passing through the first interconnect layer (SGD3) and the second interconnect layer (SGD2) in the second direction (Z).
The embodiments are not limited to the above-described aspects, but can be modified in various ways.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-143815 | Sep 2022 | JP | national |
