SEMICONDUCTOR MEMORY STRUCTURE

BACKGROUND OF THE INVENTION
1. Field of the Invention

The present invention relates to a semiconductor memory structure, and particularly to a semiconductor memory structure which can dramatically reduce the capacitance of DRAM.

2. Description of the Prior Art

Please refer to FIG. 1A which illustrates the conventional DRAM (dynamic random access memory) structure, the data XIO (for example, signal ONE (corresponding to a voltage VCCA (e.g. 1.1V)) or signal High) will be transferred along the data input circuit DI, the global I/O path GIO, the data line sense amplifier 70, the data lines DL&DLB, and then the bit lines BL&BLB, wherein DLB represents a complementary data line and BLB represents a complementary bit line. Furthermore, the data XIO will be stored in a corresponding storage node of the memory array 75 through the bit line BL. In the memory array 75, as shown in FIG. 1B, a sense amplifier 80 is connected to the bit line BL which is coupled to the data line DL through the bit line switch BS100. In addition, the sense amplifier 80 is also connected to the bit line BLB which is coupled to the data line DLB through the bit line switch BS100. A plurality DRAM cells (such as 256, 512, or 1024 DRAM cells) are connected to one bit line BL. The bit line BL has a first terminal end E1 connected to the first DRAM cell of the plurality DRAM cells and a second terminal end E2 connected to the last DRAM cell of the plurality DRAM cells. In addition, the sense amplifier 80 is coupled to a voltage VCCSA though a switch controlled by signal EN2 and coupled to a voltage VSS (e.g. 0V) though another switch controlled by signal EN1. In FIG. 1C, using one DRAM cell which includes an access transistor 11 and a storage capacitor 12 as an example, the gate of the access transistor 11 is coupled to a word line WL and the sense amplifier 22 is coupled to the access transistor 11 through the bit line BL, and one plate of the storage capacitor 12 is coupled to a plate voltage Vpl. The DRAM cell uses the access transistor 11 as a switch to control the charges to be stored from the bit line BL into the capacitor in WRITE mode or to be transferred out to bit line in READ mode.

In summary, (1) a DRAM cell array design shown in FIGS. 1A, 1B, 1C: includes many DRAM cells, such as the most popular 1T1C cell including one access transistor (having threshold voltage Vth, usually around 0.7V nominal) and one storage capacitor (having capacitance Cstorage (usually 17fF typical)); (2) these many 1T1C cells have their drains of the access transistors to be connected respectively on an interconnection which is named as bit line BL; (3) the gates of these 1T transistors are also connected respectively by an interconnection which is named as word line WL. The bit line BL is connected to a sense amplifier 22, for example, which is a CMOS (complementary metal-oxide-semiconductor) cross-couple circuits. Correspondingly, there is another bit line, named as bit line bar BLB which carries a complementary signal to that of bit line and is also connected to the same sense amplifier 22. Along such bit line BL and bit line bar BLB interconnections there are other devices to be connected for performing complete bit line functions in operations, such as bit line equalization devices for equalizing the voltage potentials as needed and bit switch devices for controlling signals in between bit lines to the data lines.

FIG. 1D shows the related signal waveforms during access (READ or WRITE) operations of most current DRAMs. The basic cell access operation for a READ command is described as follows: (1) at a start phase the bit line BL and bit line bar BLB is normally equalized at a Half-VCC level through those bit line equalization devices; (2) when an active READ operation starts, the voltage of the word line WL is raised to a high voltage level such as VPP to fully turn on the access transistor; (3) then the DRAM cell storage charges in the storage capacitor will be transferred through the access transistor to the bit line BL to change the voltage, that is, there appears a small sensing voltage ΔV, about 100 mV, which is either additive above the Half-VCC level (called as initial sensing signal ONE) or subtractive below the Half-VCC level (called as initial sensing signal ZERO); (4) the magnitude of the small sensing voltage ΔV can be calculated as equation (1):

ΔV=½×VCC×[Cstorage/(Cstorage+Cbitline+Csenseamp+Cbitswitch+Ceq] (1)

(5) After most charges have been transferred from the storage capacitor to the bit line BL, then the cross-couple sense-amplifier can be triggered on by the well-designed latch-signals to start amplify the small sensing voltage ΔV to larger signals.

(6) To give a state-of-the-art design on the DRAM cell array, Cstorage˜17fF, Cbitline˜27.5fF (each bit line capacitance per cell˜0.04fF, thus the bit line capacitance of a bit line BL which is connected with 688 cells), (Csenseamp+Cbitswich+Ceq)˜11fF, VCC˜1.1 V, and as a result, ΔV˜168 mV, which is quite sufficient for a successful sensing and amplification. By taking a different perspective on the design of Cstorage or VCC, if the minimum ΔV is required to be 100 mV, then either the minimum Cstorage can be 10fF or the VCC can be 0.67 V.

The typical design flow is to select a cell design, for example, either a stacked-capacitor over the access transistor (stacked capacitor design) or a trench-capacitor connected to the transistor. Then based on the defined process integration, the cell topography can be well defined; then the bit line capacitance per cell can be defined by the capacitance from the cell topography and then the entire Cbitline can be thus defined consequently. In the conventional DRAM, the capacitance of the bit line per DRAM cell (Cbl) made by tens nm technology node (such as 15˜28 nm technology node) is around 40×10⁻³fF by assuming connecting 688 or 512 cells on a bit line, and Table 1 shows a typical example of the capacitances related to the bit line per cell. The technology node could be the minimum feature size of such technology node process or the dimension claimed by the foundry manufacturer in such technology node process.

TABLE 1

Components
×10^−3fF

bit line to bit line
~2

bit line to S-SN (Self storage node)
~13

bit line to O-SN (Other storage nodes)
~12

bit line to word line
~12

bit line to substrate
~1

Total
40

Because the greater the capacitance of the bit line (or the capacitance of the word line) per cell, related to a bit line (or a word line) is, the fewer the number of DRAM cells connected to the bit line (or the word line) can be, how to reduce the total capacitance related to the bit line (or the word line) has become an important issue for a designer of the DRAM cells.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a semiconductor memory structure. The semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM (dynamic random access memory) cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. A rising time or a falling time of a voltage signal in the local word line is less than 4 ns.

According to one aspect of the invention, the rising time or the falling time of the voltage signal in the local word line is less than 1 ns.

According to one aspect of the invention, a random row access time of the semiconductor memory structure is less than 20 ns.

According to one aspect of the invention, a tRCD time of the semiconductor memory structure is less than 10 ns.

According to one aspect of the invention, the tRCD time of the semiconductor memory structure is less than 5 ns.

According to one aspect of the invention, a tRP time of the semiconductor memory structure is less than 10 ns.

According to one aspect of the invention, the tRP time of the semiconductor memory structure is less than 5 ns.

According to one aspect of the invention, an array write cycle time of the semiconductor memory structure is less than 3 ns.

According to one aspect of the invention, a tREF time of the semiconductor memory structure is more than 200 ms.

According to one aspect of the invention, the tREF time of the semiconductor memory structure is more than 250 ms.

According to one aspect of the invention, the bit line is under the top surface of the semiconductor substrate.

Another embodiment of the present invention provides a semiconductor memory structure. The semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. An RC time constant for the local word line is less than 2 ns.

According to one aspect of the invention, the RC time constant for the local word line is between 1.83 ns˜0 ns.

According to one aspect of the invention, a rising time or a falling time of a voltage signal in the local word line is less than 2 ns.

According to one aspect of the invention, the RC time constant for the bit line is less than 1 ns.

According to one aspect of the invention, the RC time constant for the bit line is around 0.211 ns˜0 ns.

According to one aspect of the invention, the bit line is under the top surface of the semiconductor substrate, and a top surface of the gate conductive region is lower than the top surface of the semiconductor substrate.

Another embodiment of the present invention provides a semiconductor memory structure. The semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to more than 1000 access transistors of the plurality of DRAM cells.

According to one aspect of the invention, the local word line connected to more than 2000 access transistors of the plurality of DRAM cells.

Another embodiment of the present invention provides a semiconductor memory structure. The semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM cells, a bit line, a sense amplifier, and a voltage source. The semiconductor substrate has a top surface. The plurality of DRAM cells are formed based on the semiconductor substrate, and each DRAM cell includes an access transistor and a storage capacitor. The bit line is coupled to each access transistor of the plurality of DRAM cells; wherein the bit line is disposed under the top surface of the semiconductor substrate. The sense amplifier is coupled to a first terminal of the bit line. The voltage source is electrically connected to the sense amplifier and the bit line. The voltage source provides not greater than 0.85V to the sense amplifier.

According to one aspect of the invention, the voltage source provides around 0.4V˜0.8V to the sense amplifier.

According to one aspect of the invention, the voltage source provides around 0.38V˜0.6V to the sense amplifier.

According to one aspect of the invention, the bit line is vertically and horizontally spaced apart from each access transistor of the plurality of DRAM cells.

Another embodiment of the present invention provides a semiconductor memory structure. The semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. The plurality of DRAM cells are formed based on the semiconductor substrate, and each DRAM cell comprising an access transistor and a storage capacitor. The bit line is coupled to each access transistor of the plurality of DRAM cells; wherein the bit line is disposed under the top surface of the semiconductor substrate. The sense amplifier is coupled to a first terminal of the bit line. The voltage source is electrically connected to the sense amplifier and the bit line. A tREF time of the semiconductor memory structure is more than 200 ms.

According to one aspect of the invention, the tREF time of the semiconductor memory structure is more than 250 ms.

According to one aspect of the invention, a tRFC time of the semiconductor memory structure is less than 10 ns.

According to one aspect of the invention, the tRFC time of the semiconductor memory structure is not greater than 2 ns.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing (s) will be provided by the Office upon request and payment of the necessary fee.

FIG. 1A illustrates a voltage swing on the data path during a write operation for a conventional lower power DRAM.

FIG. 1B illustrates a schematic circuit for the sense amplifier selectively coupled to two separate voltage sources during WRITE operation of the DRAM cell.

FIG. 1C illustrates commonly used design of the DRAM cell.

FIG. 1D illustrates the related signal waveforms during access (READ or WRITE) operation of most current DRAMs.

FIG. 2A illustrates the relationship between the DRAM cell and the underground bit line (UGBL).

FIG. 2B illustrates TCAD simulation results corresponding to capacitances of underground bit line (UGBL) to storage node (SN), UGBL to word line (WL), and UGBL to substrate.

FIG. 2C illustrates TCAD simulation results corresponding to capacitances of underground bit line (UGBL) to storage node (SN), UGBL to word line (WL), UGBL to substrate, WL to SN, and WL to substrate.

FIG. 2D illustrates TCAD simulation results corresponding to capacitances of WL to WL and WL to O-SN (other storage node).

FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, FIG. 2J illustrate TCAD simulation results corresponding to capacitances of underground bit line (UGBL) to bit line (UGBL).

FIG. 3 is a flowchart illustrating a manufacturing method of semiconductor memory structure having bit line with low capacitance according to an embodiment of the present invention.

FIG. 4, FIG. 5, FIG. 6, FIG. 7 illustrate forming underground bit line.

FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18 illustrate forming a storage capacitor over the access transistors.

FIG. 19 illustrates a storage capacitor (or storage node SN) being formed to cover the U-shaped transistor.

FIG. 20 illustrates the operation speed of the Thunder Array being faster than that of the conventional DRAM.

FIG. 21 illustrates the Thunder Array improving the DRAM array write cycle time.

FIG. 22 illustrates the Thunder Array reducing the RC time constant.

DETAILED DESCRIPTION

By examining the above way of defining the value from a pre-selected cell design structure, then a Cbitline per cell (or Cbl) can be calculated by the cell topography. The inventive design here is focused on a new idea: that is, enable the Cbitline per cell to be at least one fourth of the conventional Cbitline per cell or better, and then the present invention will optimally design a cell configuration in order to achieve a much lower Cbitline. As mentioned, the Cbitline per cell (“Cbl”) made by tens nm technology node is around 40×10⁻³fF for the conventional DRAM structure, and in one embodiment of the present invention, the Cbitline per cell of the new DRAM cell structure could be lower than 30×10⁻³fF, such as 10×10⁻³fF˜20×10⁻³fF. Thus, using ˜10×10⁻³fF (e.g. ¼ of the Cbl in the conventional DRAM structure) as an example, the Cbitline will be ˜5.12fF (for 512 DRAM cells) and ˜6.88fF (for 688 DRAM cells), respectively. In contrast to the bit line design of the conventional DRAM shown in Table 1, which will derive a Cbitline to be 20.48fF (for 512 DRAM cells on a bit line) and 27.52fF (for 688 DRAM cells on a bit line), respectively.

The following present the structure of the new DRAM cell structure having bit line with very low capacitance. As shown in FIG. 2A, the access transistor of the new DRAM cell includes a recess gate 201, a drain 216 and a source 213. The recess gate (e.g., made of Tungsten (W), other metal, or poly-silicon) 201 could be under a top surface or horizontal silicon surface (HSS) of a semiconductor (such as silicon) substrate 200 and has a thickness smaller than and almost equal to 30 nm, and a word line (made of Tungsten or other metal) connected to the recess gate 201 propagates along the Z direction. There is ˜2 nm high-k (Hi-K) insulator layer (or 5 nm oxide layer) 203 as gate dielectric layer surrounding the recess gate 201. Above the recess gate 201, there are ˜25 nm nitride layer 205 and ˜25 nm oxide layer 207 as a composite cap layer which has a width of ˜16 nm. Around sidewalls of the cap layer, there are ˜1 nm nitride layer 209 and ˜2 nm oxide layer 212 as spacers. The source 213 with a width of ˜9 nm and the drain 216 with a width of ˜9 nm are located on two sides (in X-direction) of the recess gate 201.

Next to the drain 216, there is a first hole 220 with width around 18 nm and height around 110 nm˜120 nm. An oxide layer 222 covers a bottom and sidewalls of the first hole 220, and a connecting plug (such as Tungsten, or other metal, or ploy-silicon) 224 is deposited within the first hole 220 and surrounded by the oxide layer 222. The thickness of the oxide layer 222 covering the sidewalls of the first hole 220 could be 2˜6 nm, such as 4 nm. Between the top surface HSS of the semiconductor substrate 200 and the connecting plug 224, there is heavily doped material (such as n+ silicon) 226 covering the connecting plug 224, and the heavily doped material 226 is electrically connected to the connecting plug 224 and the drain 216. On a top of the heavily doped material 226, there is an oxide layer 228 for isolating the drain 216 from the storage capacitor (which will be introduced in FIG. 19).

Under ˜70 nm from the top surface HSS of the semiconductor substrate 200, an underground bit line (“UGBL”) is formed and connected to the connecting plug 224. The height of the bit line UGBL is ˜40 nm and propagates along the X-direction, as marked by dash rectangle shown in FIG. 2A. The bit line UGBL is fully isolated from the semiconductor substrate 200, and a first side surface of the bit line UGBL is isolated from the semiconductor substrate 200 by a first isolating material (such as SiO2), and a second side surface of the bit line UGBL opposite to the first side surface is isolated from the semiconductor substrate 200 by a second isolating material (such as SiOCN or Si3N4). In addition, AQ1, AQ2, AQ3 represent access transistors.

The Technology Computer-Aided Design (TCAD) simulation result in FIG. 2B shows that a capacitance of the bit line UGBL to S-SN (self storage node) 230 per DRAM cell is ˜3.8×10⁻⁴fF, the capacitance of the bit line UGBL to the P-substrate (can be referred to the semiconductor substrate 200 in FIG. 2A) per DRAM cell is around 5×10⁻³fF, and the capacitance of the bit line UGBL to the word line per DRAM cell is around 1.7×10⁻³fF, under the conditions of: word line voltage=0V; a voltage of the connecting plug 231 made of Tungsten which is connected to the bit line UGBL=0V; the thickness of the spacer (can be referred to the oxide layer 222 shown in FIG. 2A) covering the connecting plug 231 made of Tungsten is 4 nm; a voltage of the SN 230=0V; a voltage of the P-substrate=−0.5V; a thickness of the oxide layer 232 for isolating the heavily doped material (can be referred to the heavily doped material 226 shown in FIG. 2A) from the storage capacitor is 20 nm; the doping concentration of the P-substrate=5×10¹⁸/cm³; the electrode of the SN 230 is made of selective growth material (e.g., n+ doped silicon with 2×10²⁰/cm³doping concentration) above the source (such doped silicon electrode will be introduced in FIG. 19), and the top plate 234 of the storage capacitor is made of Tungsten. Due to the increase of depletion region marked by line curve in the P-substrate as shown in FIG. 2B, the bit line to word line capacitance per DRAM cell in the present invention is dramatically reduced (e.g. to 1.7×10⁻³fF), as compared with that (12×10⁻³fF in Table 1) in the conventional DRAM structure.

Moreover, in FIG. 2B, the capacitance of the bit line UGBL to S-SN (Self storage node) is dramatically reduced to ˜3.8×10⁻⁴fF as well, as compared with that (13×10⁻³fF in Table 1) in the conventional DRAM structure. Due to the symmetry of DRAM array, the capacitance of the bit line UGBL to O-SN (other storage node) per DRAM cell will be substantially the same as that of the bit line UGBL to S-SN (Self storage node) per DRAM cell in the present embodiment.

FIG. 2C shows another TCAD simulation result, and the difference of the structures between FIG. 2B and FIG. 2C is that the thickness of the spacer covering the connecting plug made of Tungsten is increased from 4 nm to 6 nm. In such situation, the capacitance of the bit line UGBL to the P-substrate per DRAM cell is reduced from 5×10⁻³fF to 3.5×10⁻³fF, and the capacitance of the bit line UGBL to the word line (WL) per DRAM cell is also reduced from 1.7×10⁻³fF to 1.5×10⁻³fF.

Furthermore, the TCAD simulation result in FIG. 2E describes that the capacitance of the bit line to bit line per DRAM cell is 1.91×10⁻³fF, under the conditions of: a voltage of the word line=0V; the voltage of one major bit line=0.5V and the voltage of the other bit line=0V; the voltage of the P-substrate=−0.5V; the thickness of the SiOCN (e.g., the dielectric constant K˜4.0) covering the second side surface of the bit line is 6 nm; the doping concentration of the P-substrate=5×10¹⁸/cm³. Table 2 summarizes the simulation result for the capacitance of the bit line to bit line per DRAM: cell at different word line voltages and major bit line voltages based on the TCAD simulation results in FIGS. 2F, 2G, 2H, 2I, 2J.

TABLE 2

V_WL(volt)
V_BL(volt)
fF/cell

C_BL-C_BL
1
0
5.5 × 10⁻⁴
(FIG. 2H)

1
0.5
1.96 × 10⁻³
(FIG. 2I)

1
1
2.6 × 10⁻³
(FIG. 2J)

C_BL-C_BL
0
0
5.5 × 10⁻⁴
(FIG. 2F)

0
0.5
1.91 × 10⁻³
(FIG. 2E)

0
1
2.6 × 10⁻³
(FIG. 2G)

According to the above-mentioned topography and calculations, in the proposed DRAM structure having bit line with very low capacitance, the capacitance of the bit line per DRAM cell with the following components in Table 3 is around ˜10.06×10⁻³fF which is approximate to ¼ of the capacitance of the bit line per DRAM cell in the conventional DRAM structure (40×10⁻³fF). The capacitance of the bit line per DRAM cell according to the present invention could be even lower by further modification of the proposed DRAM structure.

TABLE 3

Components
×10^−3fF

bit line to bit line
~2.6

(biggest one in Table 2)

bit line to S-SN (Self storage node)
~0.38 (FIG. 2B)

bit line to O-SN (Other storage nodes)
~0.38 (FIG. 2B)

bit line to word line
~1.7 (FIG. 2B)

bit line to substrate
~5 (FIG. 2B)

Total
10.06

The Cbitline per cell of the present invention could be smaller than ½ of the Cbitline per cell of the conventional DRAM structure, such as ˜10×10⁻³fF (actually only around ¼ of the Cbitline per cell of the conventional DRAM structure) or even lower. Moreover, since the Cbitline per cell could be reduced, according to the above-mentioned equation, there are other choices of the DRAM array design parameters, for example: (1) it is possible to connect more DRAM cells in one bit line such that Cbitline is substantially the same as the conventional value, but ΔV is still maintained within an acceptable range for sensing; or (2) it is possible to reduce the VCC, but ΔV is still maintained within an acceptable range for sensing. For example, as shown in Table 3-1, if Cbitline per cell is reduced from 0.04fF to 0.02fF, 0.01fF, and 0.007fF, the number of cells connected to one bit line could be increased from 688 to 1376, 2752, and 3922, respectively, but ΔV is still maintained at ˜0.168V.

TABLE 3-1

Cbitline
cells

Csenseamp +

ΔV
per cell
per Bit
Cbitline
VCC
Cstorage
others

(v)
(fF)
line
(fF)
(v)
(fF)
( fF)

0.168
0.04
688
27.5
1.1
17
11

0.168
0.02
1376
27.5
1.1
17
11

0.168
0.01
2752
27.5
1.1
17
11

0.168
0.007
3922
27.5
1.1
17
11

As shown in the following Table 3-2, if ΔV could be reduced to 0.1V, Cstorage is 17fF, and Cbitline per cell is reduced to 0.02fF, and 0.007fF, then the number of cells connected to one bit line could be increased to 3280, 6550, and 9371, respectively. However, if ΔV could be reduced to 0.1V, Cstorage is reduced from 17fF to 8fF, and Cbitline per cell is reduced to 0.02fF, 0.01fF, and then the number of cells connected to one bit line could be increased to 1240, 2480, and 3542, respectively.

TABLE 3-2

Cbitline
cells

Csenseamp +

ΔV
per cell
per Bit
Cbitline
VCC
Cstorage
others

(v)
(fF)
line
(fF)
(v)
(fF)
( fF)

0.100
0.02
3280
65.6
1.1
17
11

0.100
0.01
6550
65.6
1.1
17
11

0.100
0.007
9371
65.6
1.1
17
11

0.100
0.02
1240
24.8
1.1
8
11

0.100
0.01
2480
24.8
1.1
8
11

0.100
0.007
3542
24.8
1.1
8
11

Furthermore, as shown in Table 3-3, in the event the Cbitline per cell is reduced from 0.04fF to 0.02fF, 0.01fF, and 0.007fF, the value of VCC could be reduced from 1.1V to 0.8V, 0.65V, and 0.6V, respectively, but ΔV is still maintained within an acceptable range of 0.168V˜0.155V.

TABLE 3-3

Cbitline

(688

Cbitline
cells per

Csenseamp +

per cell
bit line

Cstorage
others

ΔV (v)
(fF)
fF)
VCC (v)
(fF)
(fF)

0.168
0.04
27.5
1.1
17
11

0.163
0.02
13.8
0.8
17
11

0.158
0.01
6.9
0.65
17
11

0.155
0.007
4.8
0.6
17
11

As shown in the following Table 3-4, if ΔV could be reduced to 0.1V, Cstorage is 17fF, there are 688 cells connected to one bit line, and Cbitline per cell is reduced to 0.02fF, 0.01fF, and 0.007fF, then the value of the VCC could be reduced to 0.49V, 0.41V, and 0.385V, respectively. However, if ΔV could be reduced to 0.1V, Cstorage is reduced from 17fF to 8fF, there are 688 cells connected to one bit line, and Cbitline per cell is reduced to 0.02fF, 0.01fF, and 0.007fF, then the value of the VCC could be reduced to 0.82V, 0.65V, and 0.6V, respectively.

TABLE 3-4

Cbitline

(688

Cbitline
cells per

Csenseamp +

ΔV
per cell
bit line
VCC
Cstorage
others

(v)
(fF)
fF)
(v)
( fF)
( fF)

0.100
0.02
13.8
0.49
17
11

0.100
0.01
6.9
0.41
17
11

0.100
0.007
4.8
0.385
17
11

0.100
0.02
13.8
0.82
8
11

0.100
0.01
6.9
0.65
8
11

0.100
0.007
4.8
0.6
8
11

Similarly, a Cwordline per DRAM cell (or a capacitance of the word line per DRAM cell (Cwl)) for the semiconductor memory structure can be calculated by the cell topography based on TCAD simulation according to FIG. 2C and FIG. 2D. The capacitance of the word line per DRAM cell (Cwl) of the present invention in Table 4 is around 5.4×10⁻³fF which is approximate to 0.068 times of a capacitance of the word line per DRAM cell in the referenced conventional DRAM structure (79×10⁻³fF).

TABLE 4

Conventional
The present

Components
(×10⁻³ fF)
invention (×10⁻³ fF)

word line to word
~1
0.63

line

(FIG. 2D, WL to WL result)

word line to S-SN
~4.9
0.6

(Self storage node)

(FIG. 2C, WL to S-SN result)

word line to O-SN
~0.1
0.048

(Other storage nodes)

(FIG. 2D, WL to O-SN result)

word line to bit line
~13
1.72

(FIG. 2C, WL to BL

plug and WL to BL result)

word line to
~60
2.4

substrate

(FIG. 2C, WL to Sub result)

Total
79
~5.4

Please refer to FIG. 3, wherein FIG. 3 is a flowchart illustrating a manufacturing method of semiconductor memory structure having both bit line and word line with low capacitance according to an embodiment of the present invention.

Step 10: Start.

Step 20: Form underground bit lines (UGBL).

Step 30: Form word lines and access transistors of DRAM cells.

Step 40: Form a storage capacitor over the access transistors.

Step 50: End.

Step 20: Form underground bit lines (UGBL):

Detailed description of the aforesaid manufacturing method is as follows. Start with a p-type silicon wafer (i.e. the p-type substrate 202). As shown in FIG. 4(a), the pad-oxide layer 204 is formed above a horizontal surface 208 (i.e. named as a horizontal silicon surface (HSS), or original semiconductor surface (OSS)) and then the pad-nitride layer 206 is deposited above the pad-oxide layer 204.

As shown in FIG. 4(a), the active regions of the DRAM cell array can be defined by the photolithographic mask technique. Because the horizontal silicon surface 208 outside the active region pattern is exposed, the parts of the silicon material corresponding to the horizontal silicon surface 208 outside the active region pattern can be removed by an anisotropic etching technique to create the trench (or canal) 210, wherein for example, the trench 210 can be 250 nm deep below the HSS.

As shown in FIG. 4(a), the oxide layer 214 is deposited to fully fill the trench 210 and then the oxide layer 214 is etched back such that the shallow trench isolation (STI) inside the trench 210 is formed below the HSS. In addition, FIG. 4(b) is a top view corresponding to FIG. 4(a), wherein FIG. 4(a) is a cross-section view along a cutline of an X direction shown in FIG. 4(b). In addition, as shown in FIG. 4(a), for example, the STI has a thickness about and a top of the STI is about 200 nm deep below the HSS if the trench 210 is 250 nm deep below the HSS.

As shown in FIG. 5, then form asymmetric spacers on two symmetrical edges of the trench 210, for example, using the photolithographic mask, the nitride-1 (or other low K dielectric material, such as SiOCN) spacer (e.g. 3 nm) of the asymmetric spacers is first formed along a lower edge of the two symmetrical edges of the trench 210, and then the oxide-1 spacer (e.g. 4 nm) of the asymmetric spacers is formed along an upper edge of the two symmetrical edges of the trench 210. Therefore, as shown in FIG. 5, the nitride-1 spacer and the oxide-1 spacer cover the lower edge and the upper edge of the trench 210, respectively. A structure of the asymmetric spacers (shown in FIG. 5) is named as asymmetric spacers on two symmetrical edges of a trench. In addition, as shown in FIG. the STI may have only much thinner oxide layer (called as an oxide-1/STI layer 504) added over it. In addition, FIG. 5 is a cross-section view along the Y direction.

Afterward, as shown in FIG. 6(a), the metal layer (or a conductive material) which needs to sustain the subsequent processing conditions is deposited to form the underground bit line (“UGBL”) 902 in the trench 210. In addition, in one embodiment of the present invention, the underground bit line (UGBL) 902 can be Tungsten which is abbreviated as W, wherein a top of the underground bit line 902 is much lower than the HSS (e.g., a thickness of the underground bit line 902 is about 40 nm). In addition, as shown in FIG. 6(a), the underground bit line (UGBL) 902 is on the top of the STI and both sidewalls of the underground bit line (UGBL) 902 are bounded by the asymmetric spacers, that is, the lower edge nitride-1 spacer and the oxide-1 spacer, respectively. In addition, FIG. 6(b) is a top view corresponding to FIG. 6(a), wherein FIG. 6(a) is a cross-section view along a cutline of the Y direction shown in FIG. 6(b). It is clear that the underground bit line (“UGBL”) 902 extended along a canal or trench 210 between two active regions covered by the pad-nitride layers 206.

Then, as shown in FIG. 7 (the cross-section view along the Y direction shown in FIG. 6(b)), the oxide-2 layer 1002 (called as CVD-STI-oxide2) needs to be thick enough to fill the trench 210 over the underground bit line 902, and then the oxide-2 layer 1002 is polished back to reserve some part which is leveled as high as the top of the pad-nitride layer 206, wherein the oxide-2 layer 1002 is bounded by the pad nitride layer 206/the pad oxide layer 204 and covers both the lower edge nitride-1 spacer and the oxide-1 spacer. As shown in FIG. 7, the underground bit line 902 (i.e. an interconnection line) can be embedded and bounded by all insulators (i.e. an isolation region) inside the trench 210 (and later the underground bit line 902 will be connected to drains of access transistors of the DRAM cell array) which is named as underground bit-lines (UGBL) surrounded by insulators.

Furthermore, as shown in the following Table 5 (2021 IMEC at IEDM: Buried Power Rail Metal exploration towards the 1 nm Node), to reduce a resistance of the UGBL 902, the conventional conductive material of small grain size Tungsten (labeled as W OLD) for the UGBL 902 could be replaced by large grain size Tungsten (labeled as W Type B), and the resistivity of the UGBL 902 could be reduced from 350 to 125Ω/μm (at the UGBL 902 with width 20 nm and height 80 nm); furthermore, large grain size Tungsten (W Type B) could be replaced by Ruthenium (Ru), and the resistivity of the UGBL 902 could be reduced from 125 to 75Ω/μm. Thus, the resistivity of the UGBL 902 could be improved from 350 to 75Ω/μm.

TABLE 5

W OLD
W Type B
Ru

Resistivity
350
125
75

(Ω/μm)

Step 30: Form word lines and access transistors of DRAM cells:

The following descriptions introduce how to form both the access transistors and word lines of the DRAM cells (1T1C cell) and the word lines connect all associated gate structures of the access transistors simultaneously by a self-alignment method and thus both the gate structures and the word lines are connected as one body of metal such as Tungsten (W).

Then, as shown in FIG. 8(a), first, the thick oxide-3 layer 1102, the thick nitride-2 layer 1104, and the patterned photoresist 1106 are deposited. Then, the unnecessary parts of the oxide-3 layer 1102 and the nitride-2 layer 1104 are removed by using etching technique. A transistor/word line pattern will be defined by the composite layers of the oxide-3 layer 1102 and the nitride-2 layer 1104, wherein the composite layers of the oxide-3 layer 1102 and the nitride-2 layer 1104 includes multiple stripes in a direction perpendicular to a direction of the active region. Therefore, as shown in FIG. 8(a) and FIG. 8(b), longitudinal (the Y direction) stripes (the oxide-3 layer 1102 and the nitride-2 layer 1104) for defining the access transistors and word lines are formed, wherein the active region is located at cross-point square between the longitudinal stripes, wherein FIG. 8(a) is a cross-section view along the cutline of the X direction shown in FIG. 8(b).

As shown in FIG. 8(b), a top view reveals fabric-like checkerboard patterns with the longitudinal stripes of the oxide-3 layer 1102 and the nitride-2 layer 1104 over the pad-nitride layer 206 and the pad-oxide layer 204, and both the active region and the STI are in a horizontal direction (i.e. the X direction shown in FIG. 8(b)). The active region allows the access transistors to be made by a kind of a self-alignment technique.

Then, as shown in FIG. 9, the HSS exposed at the cross-point squares is etched by the anisotropic etching technique to create the concave (such as U-shape), wherein the U-shaped concave is for a U-shaped channel 1302 of the access transistor, and for example, a vertical thickness of the U-shaped concave from the horizontal silicon surface (HSS) can be around 30˜60 nm. Then, form a layer of the high-k insulator layer 1304 as the gate dielectric of the access transistor, select a suitable gate conductive material (Tungsten, W) 1306 that is appropriate for the word line/the gate conducive region and deposit such material in the vacancies between two adjacent longitudinal stripes (the oxide-3 layer 1102 and the nitride-2 layer 1104) to form the word lines and the recess gate (gate conductive region) of the access transistor. In one example, the top of the gate material 1306 or the gate conductive region is lower than the HSS of the p-type substrate 202. Furthermore, sequentially deposit SiOCN layer 1308 and oxide layer 1310 (or other composite dielectric layers) on the gate material 1306 to form the gate cap layer.

As shown in FIG. 9, the newly proposed access transistor (hereafter called as U-transistor) with the U-shaped channel 1302 is different from a recessed transistor commonly used in the state-of-the-art buried word line design. The U-transistor has its body with two sides bounded by the CVD-STI-oxide2 1002 along the Y direction (i.e. a channel width direction) and its channel length including a depth of one edge of the U-shaped channel 1302 on a side corresponding to a drain of the U-transistor, a length of a bottom of the U-shaped channel 1302, and a depth of another edge of the U-shaped channel 1302 on a side corresponding to a source of the U-transistor.

Similarly, to reduce the resistance of the word line, the conventional small grain size Tungsten for word line could also be changed to Ru, and the resistivity thereof will be improved from 350 to 75Ω/μm (see aforesaid Table 5).

As shown in FIG. 10, after formation of word line the nitride-3 layer 1402 (i.e. dielectric cap) is deposited and the oxide-4 layer 1404 is subsequently deposited, wherein the nitride-3 layer 1402 and the oxide-4 layer 1404 are stacked up with total thickness being large enough to fill the vacancy between the two adjacent longitudinal stripes (the oxide-3 layer 1102 and the nitride-2 layer 1104). Then, the oxide-4 layer 1404 is etched back (or polished back) to be leveled off to a top of the nitride-2 layer 1104 so as to form a composite stack composed of the oxide-4 layer 1404 and the nitride-3 layer 1402 directly above the word line (i.e. the gate material 1306).

Then, as shown in FIG. 10, the nitride-2 layer 1104 is etched away by the anisotropic etching technique and the oxide-4 layer 1404/the nitride-3 layer 1402 are left above the word line. Then, the oxide-3 layer 1102 is also etched away by the anisotropic etching to expose the pad-nitride layer 206. The gate structure (such as, the oxide-4 layer 1404/the nitride-3 layer 1402/the gate material 1306) is achieved for both the gate of the U-transistor inside the U-shaped concave and the word line in the longitudinal direction (i.e. the Y direction).

As shown in FIG. 11, the pad-nitride layer 206 is removed everywhere to leave the pad-oxide layer 204. The CVD-STI-oxide2 (i.e., the oxide-2 layer 1002) is etched back to be leveled as high as the top of the pad-oxide layer 204. Then, the nitride-4 layer 1602 is deposited and etched by the anisotropic etching technique to create a nitride-4 spacer with well-designed suitable thickness. Then, the oxide-5 layer 1604 is deposited and etched by the anisotropic etching technique to create an oxide-5 spacer. Then, the polysilicon-1 layer 1606 (i.e. intrinsic and undoped) is deposited over the entire surface and etched by the anisotropic etching technique to create polysilicon-1 spacer to make the polysilicon-1 spacer surround word lines (e.g. word line-1, word line-2, word line-3). Therefore, in summary, there are the polysilicon-1 spacer outside the oxide-5 spacer and the nitride-4 spacer, and all the above-mentioned spacers surround and along the sidewalls of gate structure.

As shown in FIG. 11, for convenience and clarity of describing the DRAM cell array with word lines and bit lines, the word line located at a center is labeled the word line-1 (corresponding to the access transistor AQ1), the word line next to a left side of the word line-1 is labeled the word line-2 (corresponding to an access transistor AQ2 next to a left side of the access transistor AQ1), and drain region (drain-1 and drain-2) between the word line-1 and the word line-2 still covered by the pad-oxide layer 204 are reserved for the drain of the access transistor AQ1 and a drain of the access transistor AQ2. The word line next to a right side of the word line-1 is labeled the word line-3 (corresponding to an access transistor AQ3 next to a right side of the access transistor AQ1), and source region (source-1 and source-3) between the word line-1 and the word line-3 still covered by the pad-oxide layer 204 are reserved for the source of the access transistor AQ1 and a source of the right access transistor AQ3.

Then, deposit a spin-on dielectrics (SOD) which is thick enough to fill into the vacancies (corresponding to the drain region and the source region) among the word lines and then polish back the SOD to a flat level with a top of the oxide-4 layer 1404 by the CMP technique. Then, some upper part of the polysilicon-1 spacer is etched by the anisotropic etching technique. Then, the cap-oxide-1 layer 1704 is deposited to fill in vacancies on top of the polysilicon-1 spacer and then planarized by the CMP technique to be leveled as high as to the top of the oxide-4 layer 1404. Then, as shown in FIG. 12, the SOD is etched away, wherein the SOD has a much higher etching rate than that of deposited or thermally grown oxide layers for them to be kept well. Then, the nitride-5 layer 1802 is deposited over an entire surface shown in FIG. 12.

Then, deposit the SOD 1902 which is thick enough to fill into the vacancies among all word lines and then polish back the SOD 1902 to a flat level with a top of the nitride-5 layer 1802. Then, apply a photoresist layer on the flat surface to cover an area reserved for the drain region (i.e. the drain-1 and the drain-2) and to expose an area reserved for the source region (i.e. the source-1 and the source-3). Then, remove the SOD 1902 corresponding to the areas reserved for the source region by utilizing the nitride-5 layer 1802 surrounding all word lines as a self-alignment mask.

Then, the exposed nitride-5 layer 1802 and the pad-oxide layer 204 at a center of the source region between two word lines (the word line-1 and the word line-3) are etched away so as to expose the HSS. Because the exposed HSS is located between the source-1 of the access transistor AQ1 and the source-3 of the access transistor AQ3, the exposed HSS between the source-1 and the source-3 can be called as HSS-1/3.

As shown in FIG. 13, utilize anisotropic etching technique to dig and remove the silicon material (corresponding to the center of the source region) below the HSS-1/3 to generate the hole-⅓ which is surrounded by the lower edge nitride-1 spacer and the oxide-1 spacer on two opposite sides (not shown in FIG. 13) and by the p-type substrate 202 on the other two opposite sides, respectively.

Then, remove the photoresist, thermally grow the oxide-7 layer 2102 to fill the hole-⅓ (or deposit suitable dielectric material), and the oxide-7 layer 2102 could be also grown partially on a top of the cap-oxide-1 layer 1704 and not elsewhere because of no growth of oxide on the nitride-5 layer 1802. The oxide-7 layer 2102 filling the hole-⅓ is called as oxide-7 plug which has a smooth surface leveled as high as the top of the pad-oxide layer 204.

As shown in FIG. 14, deposit the another SOD layer 2202, wherein the another SOD layer 2202 is thick enough to fill into the vacancy on a top of the oxide-7 layer 2102 in the hole-⅓, and top material of the another SOD layer 2202 is removed by the CMP technique until a top of the another SOD layer 2202 is leveled off as high as a top of the nitride-5 layer 1802.

Use the photolithography masking technique to cover the area corresponding to the source region and to expose the area reserved for the drain region, wherein a mask utilized in the photolithography masking technique is not a critical mask and the only function is to allow processing on the HSS-1/2 separately from the processing over the HSS-⅓. Then, the exposed SOD 1902, the exposed nitride-5 layer 1802, and the exposed pad-oxide layer 204 underneath are removed in order to expose the HSS (i.e. the HSS-½). Then, the silicon material corresponding to the HSS-1/2 is dug and removed by the anisotropic etching to generate the hole-½, wherein the hole-½ is physically surrounded by two opposite sides of the p-type substrate 202, respectively, the third side by the lower edge nitride-1 spacer, and the fourth side by the oxide-1 spacer, and both the third side and the fourth side are further bounded outside by the CVD-STI-oxide2.

Then, as shown in FIG. 14, remove the photoresist and the oxide-8 layer 2402 is thermally grown to generate an oxide-8 spacer to cover three inner sidewalls of four sidewalls of the hole-½ and a bottom of the hole-½ except the third sidewall covered by the lower edge nitride-1 spacer. In addition, the oxide-8 layer 2402 is grown partially on the top of the cap-oxide-1 layer 1704. In addition, FIG. 15 is a diagram illustrating a cross-section view of the DRAM cell array along a Y2 direction which is extended along the center of the hole-½ and perpendicular to the X direction, wherein as shown in FIG. 15, the active region is sandwiched by the CVD-STI-oxide2 1002, the bit line (UGBL), the oxide-1 spacer, and the lower edge nitride-1 spacer.

Thereafter, remove lower edge nitride-1 spacer on the third sidewall inside the hole-½ by the isotropic etching technique and the nitride-5 layer 1802 is removed at the same time (since the lower edge nitride-1 spacer is so thin so that the isotropic etching technique should not hurt the other structures over the HSS, and should neither remove the oxide-8 layer 2402 inside the hole-½).

As shown in FIG. 16, deposit the conductive layer (such as, polysilicon, or metal layer, e.g. Tungsten) 2802, wherein the conductive or metal layer 2802 is thick enough to fill in the hole-½ and then all the metal layer 2802 over the HSS is etched back by the isotropic etching technique to leave conductive or Tungsten plug inside the hole-½, and the conductive or Tungsten plug is connected with the UGBL through its opening at the third sidewall of the hole-½ which was originally covered by the lower edge nitride-1 spacer. Then, the nitride-6 layer 2804 is deposited and etched by the anisotropic etching technique to create the nitride-6 spacer surrounding the polysilicon-1 spacer corresponding to the reserved drain regions.

Then, as shown in FIG. 17, etch back some upper portion of the Tungsten plug below the HSS, wherein as shown in FIG. 17, the Tungsten plug is connected to the UGBL from its sidewall of the Tungsten plug to a sidewall of the UGBL inside the hole-½.

Then, as shown in FIG. 18, utilize the anisotropic etching technique to remove the upper portion of the oxide-8 layer 2402 in the Hole-½ by a well-designed amount, resulting in the oxide-8 spacer inside the Hole-½ having a lower height than a height of the Tungsten plug accordingly. Some of the cap-oxide-1 layer 1704 may be etched as well.

Then, as shown in FIG. 18, utilize the selective epitaxy growth technique to laterally grow the n+ in-situ doped silicon layer from the two exposed silicon edges (above and adjacent to the oxide-8 layer 2402 and the Tungsten plug), thus resulting in a necklace-type conductive n+ silicon drain (named as n+ silicon drain-collar) 226 connecting to the HSS on two sides of the hole-½ as the drain-1 and the drain-2 of the access transistors AQ1, AQ2, respectively, and also as a conductive bridge (i.e. bridge contact) between the UGBL and the access transistors AQ1, AQ2.

Then, as shown in FIG. 18, the oxide-9 layer 3302 with a well-designed thickness is thermally grown locally over the n+ silicon drain-collar to cap the HSS-1/2 (and such oxide-9 layer 3302 may cover the cap-oxide-1 layer 1704). In addition, LDD regions and/or other highly doped regions could be formed in the drain region and the source region. Therefore, the word line, UGBL, and the U-shaped transistor are completely formed.

In addition, further processes could be introduced to form the structure similarly shown in FIG. 2A. For example, etch back some of the oxide-9 layer 3302 covering the n+ silicon drain-collar in a thickness with its height as that of the pad-oxide 204, and the oxide-9 layer 3302 covering the cap-oxide-1 layer 1704 is etched away. Then, deposit the thick intrinsic polysilicon-a layer 3402 inside the vacancy above the oxide-9 layer 3302 which is above the hole-1/2 and etch back the polysilicon-a layer 3402. Remove the nitride-6 spacer (the nitride-6 layer 2804) by the isotropic etching technique. Deposit the intrinsic polysilicon-b layer 3502 and then use the anisotropic etching technique to etch back the polysilicon-b layer 3502 to leave some residues to fill into the vacancies right adjacent to the polysilicon-a layer 3402 and form almost the same thickness of both the polysilicon-a layer 3402 and the polysilicon-b layer 3502. Then, all the SODs (i.e. the SOD layer 1902 and the another SOD layer 2202) are removed and the nitride-5 layer 1802 are removed by the isotropic etching technique.

Step 40: Form a storage capacitor over the access transistors:

As shown in FIG. 19, a storage capacitor (or storage node SN) then could be formed to cover the U-shaped transistor, wherein one electrode of the storage capacitor made of silicon/heavily doped silicon is electrically connected to the source region, and the other electrode of the storage capacitor made of Tungsten (or other conductive material) is the counter electrode shared by all storage capacitors. A Hi-K dielectric insulator is formed between two electrodes. The exemplary processes to form the storage capacitor FIG. 19 may refer to the U.S. patent application Ser. No. 17/337,391 filed on Jun. 2, 2021 (Title: MEMORY CELL STRUCTURE), all contents of which is incorporated by reference.

After completion of the storage capacitor, the new DRAM cell (having the above-mentioned semiconductor memory structure) with underground bit line has smaller dimension (almost 4F˜7.5F, F is the minimum feature size). Therefore, the size of one DRAM: bank with the new DRAM cells according to the present invention could be shrunk as well, so is the length of the bit line and local word line in that shrunk DRAM bank. Further consideration of the reduction of resistivity due to the replacement of W by Ru, the bit line resistance/um of the present invention could be reduced to ⅓˜¼ of that of the conventional DRAM structure, and the word line resistance/um of the present invention could be reduced to ½˜⅓ of that of the conventional DRAM structure.

According to the above-mentioned, the new DRAM array (having the above-mentioned new DRAM cell, called Thunder Array) of the present invention effectively reduces capacitance and resistance of the bit line and word line (or the local word line). The bit line resistance/um of the Thunder Array at least could be reduced to ⅓˜¼ and the bit line capacitance/um is also reduced to ⅓˜¼. Thus, the RC time constant for the bit line in the Thunder Array is reduced to 1/9˜ 1/16. Moreover, the word line resistance/um of the Thunder Array could be at least reduced to ½˜⅓, and the word line capacitance/um is also reduced to 0.068, taking example of reduction to ⅓˜¼, the RC time constant for the word line in the Thunder Array could be reduced to ⅙˜ 1/12. For example, according to 6 sigma calculation, the RC time constant of the local word line is around 1.831 ns˜0 ns (based on the RC time constant of the local word line is reduced to ⅙ of the RC time constant of the conventional DDR3/DDR4 DRAM) and the RC time constant of the bit Line is around 0.211 ns˜0 ns (based on the RC time constant of the bit line is reduced to 1/9 of the RC time constant of the conventional DDR3/DDR4 DRAM), as shown in the following Table 6 & Table 7:

RC time constant of Thunder Array Local Word Line (S: Standard Deviation)

TABLE 6

Final choosing

⅙ LWL RC
Mean (u)
0.875

S
0.159

u + 3S
1.353

u − 3S
0.396

u + 6S
1.831

u − 6S (Max. of 0, u − 6S)
0

RC Time Constant of Thunder Array LWL is

1.831 ns~0 ns

(PS: in the event u − 6S <= 0, then u − 6S is set to 0)

RC time constant of Thunder Array bit Line (S: Standard Deviation)

TABLE 7

Final choosing

1/9 BL RC
Mean (u)
0.078

S
0.022

u + 3S
0.144

u − 3S
0.011

u + 6S
0.211

u − 6S (Max. of 0, u − 6S)
0

RC Time Constant of Thunder Array Bit line

(BL) is 0.211 ns~0 ns

(PS: in the event u − 6S <= 0, then u − 6S is set to 0)

Therefore, the operation speed of the Thunder Array is faster than that of the conventional DRAM, even compatible with that of commercial SRAM. Since the RC time constant for the bit line of the Thunder Array is reduced to 1/9˜ 1/16, the small signal develop voltage could be improved about 2˜3 times, and the refresh time could be improved 2˜3 times as well. Since the RC time constant for the local word line (LWL) of the Thunder Array is reduced to ⅙˜ 1/12, the rising time of a voltage signal in LWL could be reduced from 11 ns to 0.5˜0.9 ns (or less than 4 ns, such as less than 2 ns), and the falling time of a voltage signal in LWL could also be reduced from 11 ns to 0.5˜0.9 ns (or less than 4 ns, such as less than 2 ns), as shown in FIG. 20, wherein the bottom voltage of the LWL signal in FIG. 20 is −0.2˜0V and top voltage of the LWL signal is 2˜2.8V.

Using Joint Electron Device Engineering Council (JEDEC) DDR(Double-Data-Rate)3 or DDR4 at 1066 MHz as example, the DRAM array write cycle time could be improved to 2.75 ns (compared with 3.75 ns of JEDEC Array Write Cycle Time in DDR3 or DDR4 at 1066 MHz, there is 26% improvement), as shown in FIG. 21.

Furthermore, using JEDEC DDR3 or DDR4 as example again, the random row access time could be improved from 25˜27.87 ns to 14.93˜18.71 ns at different operation frequencies, as shown in the following Table 8:

TABLE 8

Conventional

DDR3/DDR4 DRAM
Thunder Array

Random Row
Thunder Array Range

Access Time
(LWL RC)

tRCD + CL
LWL ⅙ RC
LWL 1/12 RC

tRCD + CL 800
25.00 ns
15.84 ns
14.93 ns

5-5-5

tRCD + CL 1066
26.25 ns
17.09 ns
16.18 ns

7-7-7

tRCD + CL 1600
27.50 ns
18.34 ns
17.43 ns

11-11-11

tRCD + CL 1866
27.87 ns
18.71 ns
17.80 ns

13-13-13

Under LWL
Under LWL

Rise
Rise

Time is 1.83 ns
Time is 0.92 ns

The tRCD could be improved from 12.5˜13.94 ns to 2.42˜4.77 ns at different operation frequencies, as shown in the following Table 9:

TABLE 9

Thunder Array

Thunder Array tRCD Range

Conventional
(LWL RC)

DDR3/DDR4 DRAM
LWL ⅙ RC
LWL 1/12 RC

tRCD + CL 800
12.50 ns
3.33 ns
2.42 ns

5-5-5

tRCD + CL 1066
13.13 ns
3.96 ns
3.04 ns

7-7-7

tRCD + CL 1600
13.75 ns
4.58 ns
3.67 ns

11-11-11

tRCD + CL 1866
13.94 ns
4.77 ns
3.85 ns

13-13-13

The tRP could be improved from 12.5˜13.94 ns to 1.54˜3.93 ns at different operation frequencies, as shown in the following Table 10:

TABLE 10

Thunder Array

Thunder Array tRP Range

(LWL RC + BL RC)

Conventional
LWL ⅙ RC plus
LWL 1/12 RC

DDR3/DDR4 DRAM
BL 1/9 RC
plus BL 1/16 RC

tRP 800
12.50 ns
2.50 ns
1.54 ns

5-5-5

tRP 1066
13.13 ns
3.12 ns
2.16 ns

7-7-7

tRP 1600
13.75 ns
3.75 ns
2.79 ns

11-11-11

tRP 1866
13.94 ns
3.93 ns
2.97 ns

13-13-13

The tREF (refresh time) can be improved from 64 ms to 256 ms when Bit line capacitance is reduced to ¼, as shown in the following Table 11:

TABLE 11

Conventional

DDR3/DDR4 DRAM
Thunder Array

Cbl (aF)/bit
40.16
10.04

1 Sigma (aF/bit)
1.336
0.33

tREF SPEC
4K 64 ms
4K 256 ms

In consideration of the improvement of the lower RC time constant of the local word line and lower RC time constant of the bit line (and others, such as, small signal developed speed and developed voltage is improved, sensing speed is improved, equalization speed is improved as well), the refresh operation may be further improved. For example, the Refresh Cycle Time (tRFC) could be improved less than 10 ns, such as to 2 ns, in the present invention.

Other JEDEC specification parameters, such as Bit Line Loading, Bit Line Write Speed, tRC, tRAS, tRFC, etc., could be improved as well according to the present Thunder Array invention.

Furthermore, as shown in FIG. 22, since the RC time constant is reduced, one local word line could be connected to more access transistors (from 1000 to 2000˜3000) and therefore the number of the local word line driver could be reduced as well. That is, two sub-arrays with two local word lines (LWL) could be merged into a new sub-array in which the new LWL length of the new sub-array is 2 times of the original LWL length (left portion of FIG. 22), and it is also possible that three sub-arrays with three local word lines (LWL) could be merged into a new sub-array in which the new LWL length of the new sub-array is 3 times of the original LWL length (right portion of FIG. 22). The conventional LWL length in one sub-array of the DRAM is 85.25 um, and the conventional LWLDRV (LWL driver) Height in one sub-array of the DRAM is 6.11 um. Therefore, Thunder Array of the present invention with merged 2 or 3 sub-arrays could reduce 3.34% or 4.46% area respectively, but still has better AC performance than conventional DRAM array, as shown in FIG. 22.

In summary, the new DRAM (the Thunder Array DRAM) with untra-low bit line RC time constant and word line RC time constant is proposed. The RC time constant for the bit line is reduced to 1/9˜ 1/16, and the RC time constant for the word line is at least reduced to ⅙˜ 1/12, as compared with the conventional DRAM made by tens nm technology node (such as 15˜28 nm technology node). Thus, the signals in bit line and word line could be developed more and transmitted faster, and the voltage swing for the signals in bit line and word line could be reduced accordingly. For example, the Vpp level in word line to turn on the access transistor could be lower than 2V (such as 1.5˜1.8V), the VCC level in bit line corresponding to signal ONE could be as low as 0.6˜0.8V, and the voltage level stored in capacitor of the DRAM cell could be almost the same as the VCC level in bit line corresponding to the signal ONE, as compared with the conventional DRAM only 80˜85% of the VCC level in bit line is stored in the capacitor (of course, a voltage drop due to the threshold voltage of the access transistor shall be deducted in real case). Moreover, the power consumption of the DRAM could be dramatically improved due to the reduction of the capacitance for bit line and word line and the reduction of the voltage swing for the signals in bit line and word line.

In addition, the Thunder Array DRAM can help synchronous DRAM AC parameters improvement, and the Thunder Array DRAM can also improve pseudo SRAM (static random-access memory) AC parameters. Since the pseudo SRAM needs to insert Refresh command to satisfy its refresh time, the conventional DRAM design has reserved a tRFC before starting to decode Address and Read/Write data. However, the above-mentioned issue shown in the conventional DRAM design becomes very minor due to improvement of rise time and fall time of local word line in the Thunder Array DRAM. In other word, tRFC is now much smaller in the Thunder Array DRAM. As a result, the pseudo SRAM AC parameters like tAA/tAADV/tBA/tRC can be improved from 70 ns to 35 ns.

Although the present invention has been illustrated and described with reference to the embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

SEMICONDUCTOR MEMORY STRUCTURE

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