Claims
- 1. An integrated circuit including a memory, comprising:
- a plurality of memory cells arranged in rows and columns;
- a row decoder for selecting a row of said memory cells responsive to a row address;
- a data line associated with a column of said memory cells for communicating a data state presented thereupon by a memory cell in the selected row;
- a sense amplifier for amplifying the data state presented upon said data line; and
- an inverting circuit, having an input coupled to said sense amplifier, and having an output coupled to said data line, for selectably driving said data line, responsive to a test mode control signal, with a data signal which is the logical complement of the data state presented upon said data line, so that the memory cell in the selected column and in the selected row is written with its logical complement.
- 2. The circuit of claim 1, further comprising:
- an output buffer, coupled to said sense amplifier, for driving an output terminal with a signal corresponding to the data state presented on said data line by the memory cell in the selected row.
- 3. The circuit of claim 2, further comprising:
- a column decoder for selecting, responsive to a column address, a column of said memory cells for association with said data line.
- 4. The circuit of claim 3, further comprising:
- a special mode enabling circuit, having an input for receiving a special mode enable signal, and having an output coupled to said inverting circuit, for generating the test mode control signal to said inverting circuit responsive to the special mode enable signal.
- 5. The circuit of claim 1, further comprising:
- a plurality of bit line pairs, each associated with a column of memory cells, for communicating a differential signal from the memory cell in its associated column which is in the selected row; and
- a column decoder, for selecting a pair of bit lines to be coupled to said data line for communication with said sense amplifier.
- 6. The circuit of claim 1, wherein each of said plurality of memory cells comprises a static random access memory cell.
- 7. The circuit of claim 6, wherein each of said plurality of memory cells stores a preferred logic state when powered-up.
- 8. The circuit of claim 7, wherein each of said memory cells is of the type that draws less current when storing its preferred logic state than when storing the complement of its preferred logic state.
- 9. The circuit of claim 7, wherein each of said memory cells is of the type that is less susceptible to being upset by noise when storing its preferred logic state than when storing the complement of its preferred logic state.
- 10. The circuit of claim 1, further comprising:
- an input terminal for receiving input data to be written to said inverting circuit; and
- a special mode enabling circuit, having an input for receiving a special mode enable signal, and having an output coupled to said inverting circuit;
- and wherein said inverting circuit has a first input coupled to said data line, a second input coupled to said input terminal, and a control input coupled to the output of said special mode enabling circuit, in such a manner that said inverting circuit drives said data line with a data signal which is the logical complement of the sensed data state responsive to receipt of said special mode enable signal, and in such a manner that said inverting circuit drives said data line with a data signal corresponding to said input data responsive to the special mode enabling circuit not receiving said special mode enable signal.
- 11. The circuit of claim 10, further comprising:
- a plurality of bit line pairs, each associated with a column of memory cells, for communicating a differential signal from the memory cell in its associated column which is in the selected row; and
- a column decoder, for selecting a pair of bit lines to be coupled to said data line for communication with said sense amplifier.
- 12. The circuit of claim 1, wherein said memory is embedded within a logic circuit.
- 13. The circuit of claim 12, wherein said logic circuit is a microprocessor.
- 14. The circuit of claim 12, wherein said logic circuit is a logic array.
Parent Case Info
This is a division of application Ser. No. 07/620,835, filed Nov. 29, 1990, now U.S. Pat. No. 5,289,475.
US Referenced Citations (10)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0234937 |
Sep 1987 |
EPX |
0399207 |
Nov 1990 |
EPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
620835 |
Nov 1990 |
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