Claims
- 1. A semiconductor device, comprising:
- a semiconductor mesa adjacent an insulating layer and having a sidewall;
- at least one transistor structure formed in said semiconductor mesa;
- a sidewall spacer adjacent the sidewall of the mesa; and
- an undercut region adjacent the sidewall spacer on the side of the sidewall spacer opposite the sidewall of the semiconductor mesa, said undercut region not extending beneath said mesa.
- 2. The semiconductor device of claim 1 wherein said sidewall spacer comprises a sidewall spacer having a foot portion extending away from the mesa and adjacent the insulating layer.
- 3. The semiconductor device of claim 1 and further comprising an insulator region between the sidewall spacer and the sidewall of the mesa.
- 4. The semiconductor device of claim 3 wherein said insulator region comprises an oxide region.
- 5. The semiconductor device of claim 1 wherein said sidewall spacer comprises a non-oxidizable sidewall spacer.
- 6. The semiconductor device of claim 5 wherein said sidewall spacer comprises a nitride sidewall spacer.
- 7. The device of claim 1 and further comprising:
- a gate oxide layer formed over said semiconductor mesa; and
- a gate conductor formed over said gate oxide layer.
- 8. The device of claim 7 wherein said gate conductor comprises a polysilicon gate.
- 9. A semiconductor device, comprising:
- a semiconductor mesa having sidewalls and adjacent an insulating layer;
- at least one transistor structure formed in said semiconductor mesa;
- first sidewall spacers along the sidewalls of the mesa; and
- second sidewall spacers along the first sidewall spacers on the side of the first sidewall spacer opposite the mesa, the second sidewall spacers each having a respective foot portion extending away from the mesa and adjacent the insulating layer such that undercut areas are defined between the second sidewall spacers foot portion and the insulating layer.
- 10. The semiconductor device of claim 10 wherein said first sidewall spacers comprise grown insulator regions along the sidewalls of the mesa.
- 11. The semiconductor device of claim 9 wherein said first sidewall spacers comprises oxidizable sidewall spacers and wherein said second sidewall spacers comprise non-oxidizable sidewall spacers.
RELATED APPLICATIONS
This is a continuation of application Ser. No. 07/534,920, filed 06/08/90, now U.S. Pat. No. 5,039,621.
This application is related to co-pending U.S. Pat. Ser. No. 07/269,803 now U.S. Pat. No. 4,956,307, entitled "Thin Oxide Sidewall Insulators For Silicon Over Insulator Transistors", by Pollack, et al., filed Nov. 10, 1988.
This invention relates in general to semiconductor devices and more particularly to an improved semiconductor over insulator mesa and the method of forming the same.
Semiconductor over insulator (SOI) devices provide numerous benefits in contemporary integrated circuit technology. An SOI device includes a semiconductor mesa overlying a buried insulating layer, which itself overlies a semiconductor substrate. Typically, a transistor is formed within the semiconductor mesa. During oxide deglaze cycles, which are a normal part of integrated circuit processing of mesa isolated SOI transistors, it is difficult to avoid etching of the exposed buried insulating layer. The etching of the exposed buried layer causes unwanted oxide undercutting of the SOI mesa. This undercutting has been shown to cause numerous problems with the devices ultimately constructed within the mesa. For example, the undercutting region has been shown to degrade gate oxide integrity at the bottom corner of the semiconductor mesa. Additionally, the undercutting causes a decrease in the radiation hardness of the device.
The prior art methodologies for forming a semiconductor mesa in a SOI architecture result in the above-mentioned undercut regions. Accordingly, the undesirable results of degradation of gate oxide integrity and increased susceptibility to the effects of radiation currently exist in contemporary SOI mesa devices. Therefore, a need has risen for an SOI mesa architecture and methodology which significantly reduces or eliminates the effects of undercutting discussed above.
In accordance with the present invention, an SOI mesa structure and methodology for forming the same are provided which substantially eliminate and prevent disadvantages and problems associated with prior mesa structures.
The method of the present invention includes forming a semiconductor mesa having sidewalls and adjacent an insulating layer. First sidewall spacers are formed adjacent the sidewalls of the mesa. Further, second sidewall spacers are formed adjacent the first sidewall spacers and opposite the mesa.
In accordance with the present invention, the second sidewall spacers may be formed to include foot portions extending away from the mesa and adjacent the insulating layer.
The present invention provides numerous technical advantages over prior SOI mesa configurations. An SOI mesa constructed in accordance with the present invention includes undercutting regions significantly removed from the semiconductor mesa, thereby reducing the detrimental effects of undercutting heretofore associated with semiconductor mesas in SOI technology. A particular technical advantage is that gate oxide integrity at the bottom corners of the semiconductor mesa is significantly improved. Further, through experimental use of the present invention, the technical advantage of increased radiation hardness of the device to total gamma dose has been observed. Additionally, there is the technical advantage that the undercutting regions associated with SOI processes may be shifted laterally away from the semiconductor mesa at a distance which is both variable and selectable for a given implementation of the present invention.
Government Interests
The United States government has a paid up license in this invention and the rights in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract No. DNA 001-86-C-0090 awarded by the Defense Nuclear Agency.
US Referenced Citations (12)
Foreign Referenced Citations (3)
| Number |
Date |
Country |
| 56-6474 |
Jan 1981 |
JPX |
| 63-257231 |
Oct 1988 |
JPX |
| 2-125433 |
May 1990 |
JPX |
Divisions (1)
|
Number |
Date |
Country |
| Parent |
534920 |
Jun 1990 |
|
Patent Grant
5162882
