SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0067777, filed on Jun. 2, 2022, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a semiconductor package and a method of fabricating the same, and more particularly, to a semiconductor package including an image sensor and a method of fabricating the same.

In general, an image sensor is a semiconductor device that converts optical images into electrical signals. The image sensor is broadly classified into a charge coupled device (CCD) type image sensor and a complementary metal oxide silicon (CMOS) type image sensor (also referred to as CIS).

Recent advances in computer and communication industries have led to strong demands in high performances image sensors in various consumer electronic devices such as digital cameras, camcorders, PCSs (Personal Communication Systems), game devices, security cameras, medical micro cameras, etc. A plurality of image sensors have recently been used in portable electronic devices, and thus the plurality of image sensors are integrated and utilized in the devices.

In the semiconductor industry, high capacity, thinness, and compactness of semiconductor devices and electronic products using the same have been demanded and thus various package techniques have been suggested.

SUMMARY

Some embodiments of the inventive concepts provide a semiconductor package with improved electrical properties and a method of fabricating the same.

Some embodiments of the inventive concepts provide a semiconductor package with improved structural stability and a method of fabricating the same.

According to some embodiments of the inventive concepts, a semiconductor package may include: a first semiconductor chip; a second semiconductor chip below the first semiconductor chip; and a third semiconductor chip below the second semiconductor chip. The second semiconductor chip may include: a semiconductor substrate; a first wiring layer on a first surface of the semiconductor substrate; a second wiring layer on a second surface of the semiconductor substrate; and a through via that penetrates the semiconductor substrate and electrically connects the first wiring layer and the second wiring layer. The semiconductor substrate and the through via may be spaced apart from each other across a spacer structure. The spacer structure may include: a first liner layer in contact with the semiconductor substrate; a second liner layer in contact with the through via; an air gap between the first liner layer and the second liner layer; and a capping layer that seals the air gap on the first liner layer and the second liner layer.

According to some embodiments of the inventive concepts, a semiconductor package may include: an image sensor chip including a first pad; a logic chip below the image sensor chip and including a second pad, wherein the first pad and the second pad are in direct contact with each other on an interface between the image sensor chip and the logic chip; and a memory chip below the logic chip. The logic chip may include: a semiconductor substrate; a conductive pattern on an active surface of the semiconductor substrate; a first dielectric layer that covers the conductive pattern on the active surface of the semiconductor substrate; a through hole that vertically penetrates the semiconductor substrate and at least a portion of the first dielectric layer and exposes the conductive pattern; a first liner layer that conformally covers an inner side surface and at least a portion of bottom surface of the through hole; a capping layer that covers at least a portion of the through hole and an inactive surface of the semiconductor substrate; a second dielectric layer that covers the capping layer on the inactive surface of the semiconductor substrate; and a through via in the through hole, the through hole penetrating at least a portion of the second dielectric layer and the first liner layer and connecting the first pad to the conductive pattern. In the through hole, an air gap may be defined by the through via, the first liner layer, and the capping layer.

According to some embodiments of the inventive concepts, a method of fabricating a semiconductor package may include: forming a logic chip; directly bonding an image sensor chip onto the logic chip, wherein a first pad of the logic chip is directly bonded to a second pad of the image sensor chip; and bonding a memory chip below the logic chip. The step of forming the logic chip may include: forming a conductive pattern on an active surface of a semiconductor substrate; forming a first dielectric layer on the active surface of the semiconductor substrate, the first dielectric layer covering the conductive pattern; forming a first through hole that penetrates the semiconductor substrate and the first dielectric layer and exposes the conductive pattern; forming a first liner layer that conformally covers an inactive surface of the semiconductor substrate, an inner lateral surface of the first through hole, and a bottom surface of the first through hole; forming a through via in the first through hole, the through via penetrating the first liner layer to come into connection with the conductive pattern, and the through via being spaced apart from the inner lateral surface of the first through hole; in the first through hole, allowing a decomposition layer to fill a space between the first liner layer and the through via; forming a capping layer on the inactive surface of the semiconductor substrate, the capping layer covering the decomposition layer and the through via; removing the decomposition layer to form an air gap; forming the first pad on the through via; and forming a second dielectric layer on the inactive surface of the semiconductor substrate, the second dielectric layer partially surrounding the through via.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the inventive concepts.

FIGS. 2 to 4 are enlarged views illustrating section A of FIG. 1.

FIG. 5 is a plan view illustrating a spacer structure.

FIGS. 6 to 8 are enlarged views illustrating section A of FIG. 1.

FIG. 9 is a plan view illustrating a spacer structure.

FIG. 10 is a cross-sectional view illustrating a semiconductor module according to some embodiments of the inventive concepts.

FIGS. 11A to 25A are cross-sectional views illustrating a method of fabricating a semiconductor package according to some embodiments of the inventive concepts.

FIGS. 11B to 25B are enlarged views illustrating section B of FIGS. 11A to 25A, respectively.

FIGS. 14C, 16C, 18C, and 19C are enlarged views of section B respectively depicted in FIGS. 14A, 16A, 18A, and 19A, illustrating other examples of FIGS. 14B, 16B, 18B, and 19B, respectively.

DETAILED DESCRIPTION

The following will now describe semiconductor packages and methods of fabricating the same according to the present inventive concepts with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the inventive concepts. FIGS. 2 to 4 are enlarged views illustrating section A of FIG. 1. FIG. 5 is a plan view illustrating a spacer structure. FIG. 1 omits a configuration of the spacer structure, and the spacer structure will be discussed in detail in FIGS. 2 to 4.

Referring to FIGS. 1 to 5, a semiconductor package 10 may include a first semiconductor chip 100, a second semiconductor chip 200 mounted below the first semiconductor chip 100, and a third semiconductor chip 300 mounted below the second semiconductor chip 200. The first, second, and third semiconductor chips 100, 200, and 300 may have different functions from each other. The first and second semiconductor chips 100 and 200 may have the same width as each other. The first and second semiconductor chips 100 and 200 may have their sidewalls coplanar or vertically aligned with each other. The first and second semiconductor chips 100 and 200 may be in contact with each other. The second and third semiconductor chips 200 and 300 may have the same width as each other. The second and third semiconductor chips 200 and 300 may have their sidewalls coplanar or vertically aligned with each other. The second and third semiconductor chips 200 and 300 may be in contact with each other.

The first semiconductor chip 100 may have a first top surface 101a and a first bottom surface 101b. The first semiconductor chip 100 may include a first upper conductive pad 180 disposed on the first top surface 101a. The first semiconductor chip 100 may include a first lower conductive pad 190 disposed adjacent to the first bottom surface 101b. The first upper conductive pad 180 and the first lower conductive pad 190 may be formed of metal, such as copper (Cu). The first semiconductor chip 100 may be, for example, an image sensor chip.

The second semiconductor chip 200 may have a second top surface 201a in contact with the first semiconductor chip 100 and a second bottom surface 201b directed toward or facing the third semiconductor chip 300. The second semiconductor chip 200 may include a second upper conductive pad 280 disposed adjacent to the second top surface 201a. The second semiconductor chip 200 may include a second lower conductive pad 290 disposed adjacent to the second bottom surface 201b. The second upper conductive pad 280 may be in contact with the first lower conductive pad 190. The second upper conductive pad 280 and the second lower conductive pad 290 may be formed of metal, such as copper (Cu). For example, the second semiconductor chip 200 may be a logic chip that drives the first semiconductor chip 100.

A direct bonding may be used to bond the second semiconductor chip 200 to the first semiconductor chip 100. For example, an intermetallic hybrid bonding may be made between the second upper conductive pad 280 of the second semiconductor chip 200 and the first lower conductive pad 190 of the first semiconductor chip 100. In this disclosure, the hybrid bonding may mean that two components including the same material are merged with each other at an interface between the two components or that a first component including a first material and a second component including a second material (or a compound of the first material) are merged with each other at an interface between the first component and the second component. For example, the second upper conductive pad 280 and the first lower conductive pad 190 may be in direct contact with each other, the second upper conductive pad 280 and the first lower conductive pad 190 may have a continuous configuration, and an invisible interface may be provided between the second upper conductive pad 280 and the first lower conductive pad 190. No passivation layer may be interposed between the first semiconductor chip 100 and the second semiconductor chip 200.

The third semiconductor chip 300 may have a third top surface 301a in contact with the second semiconductor chip 200. The third semiconductor chip 300 may include a third upper conductive pad 380 disposed adjacent to the third top surface 301a. The third upper conductive pad 380 may be in contact with the second lower conductive pad 290. The third upper conductive pad 380 and the second lower conductive pad 290 may be formed of metal, such as copper (Cu). The third semiconductor chip 300 may be, for example, a memory chip that stores data produced from the second semiconductor chip 200. For example, the third semiconductor chip 300 may be a dynamic random-access memory (DRAM) chip.

A direct bonding may be used to bond the third semiconductor chip 300 to the second semiconductor chip 200. For example, an intermetallic hybrid bonding may be made between the third upper conductive pad 380 of the third semiconductor chip 300 and the second lower conductive pad 290 of the second semiconductor chip 200. For example, the third upper conductive pad 380 and the second lower conductive pad 290 may be in direct contact with each other, the third upper conductive pad 380 and the second lower conductive pad 290 may have a continuous configuration, and an invisible interface may be provided between the third upper conductive pad 380 and the second lower conductive pad 290. No passivation layer may be interposed between the second semiconductor chip 200 and the third semiconductor chip 300.

FIG. 1 depicts that a direct bonding is made between the second semiconductor chip 200 and the third semiconductor chip 300, but the present inventive concepts are not limited thereto. The third semiconductor chip 300 may be flip-chip bonded to the second bottom surface 201b of the second semiconductor chip 200. For example, the second and third semiconductor chips 200 and 300 may be spaced apart from each other, and the second lower conductive pad 290 of the second semiconductor chip 200 and the third upper conductive pad 380 of the third semiconductor chip 300 may be electrically connected through connection means such as solder balls. A passivation may be provided to cover the third top surface 301a of the third semiconductor chip 300.

Hereinafter, a configuration of the first, second, and third semiconductor chips 100, 200, and 300 will be described in detail based on the embodiment of FIG. 1.

The first semiconductor chip 100 may include a first semiconductor substrate 110 and a first dielectric layer 120 disposed on the first semiconductor substrate 110. The first semiconductor chip 100 may be turned upside down to allow the first semiconductor substrate 110 to reside on the first dielectric layer 120. The first semiconductor substrate 110 may have a top surface that corresponds to the first top surface 101a. The first dielectric layer 120 may have a bottom surface that corresponds to the first bottom surface 101b.

The first semiconductor substrate 110 may include a semiconductor material. For example, the first semiconductor substrate 110 may be a silicon (Si) substrate.

The first semiconductor substrate 110 may be provided therein with deep device isolation layers DTI that separate a plurality of unit pixels UP from each other. Although not shown, the first semiconductor substrate 110 may include therein a plurality of photodiode regions each of which is disposed on a corresponding one of the unit pixels UP.

The first top surface 101a may be covered with a first passivation layer 114. The first passivation layer 114 may include, for example, a silicon nitride (SiN) layer or a polyimide (PI) layer.

The first passivation layer 114 may be provided thereon with color filters 150 that correspond to the unit pixels UP. A micro-lens array 140 may be disposed on the color filters 150. The first top surface 101a may be provided on its outer portion with the first upper conductive pad 180 spaced apart from the color filters 150. The first semiconductor substrate 110 may be provided thereon with a transfer gate TG which transfers charges created from the photodiode region.

The first dielectric layer 120 may cover a bottom surface of the first semiconductor substrate 110. The first dielectric layer 120 may be formed of a multiple layer including, for example, at least one selected from a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, and a porous low-k dielectric layer. The first dielectric layer 120 may include therein multi-layered first wiring patterns 122. The first wiring patterns 122 may be electrically connected to the first lower conductive pad 190. A portion of the first lower conductive pad 190 may be exposed on and coplanar with the first bottom surface 101b, or a bottom surface of the first dielectric layer 120.

The first semiconductor substrate 110 may include a first through via TSV1 that penetrates the first semiconductor substrate 110. The first through via TSV1 may penetrate a portion of the first dielectric layer 120 to come into electrical connection with the first wiring patterns 122 or the first lower conductive pad 190. The first through via TSV1 may be coupled to the first upper conductive pad 180.

A first via dielectric layer 112 may be disposed adjacent to the first through via TSV1. The first via dielectric layer 112 may be spaced apart from the first through via TSV1. Although not shown, when viewed in plan, the first via dielectric layer 112 may surround the first through via TSV1. The first via dielectric layer 112 may insulate the first through via TSV1 from the first semiconductor substrate 110. The first via dielectric layer 112 may penetrate the first semiconductor substrate 110.

The second semiconductor chip 200 may include a second semiconductor substrate 210, a second dielectric layer 220 on the second semiconductor substrate 210, and a third dielectric layer 230 below the second semiconductor substrate 210. The second dielectric layer 220 may have a top surface that corresponds to the second top surface 201a. The third dielectric layer 230 may have a bottom surface that corresponds to the second bottom surface 201b.

The second semiconductor substrate 210 may include a semiconductor material. For example, the second semiconductor substrate 210 may be a silicon (Si) substrate. The second semiconductor substrate 210 may have a first surface 211a directed toward or facing the first semiconductor chip 100 and a second surface 211b directed toward or facing the third semiconductor chip 300.

A plurality of first transistors TR1 may be disposed on the second semiconductor substrate 210. For example, the first transistors TR1 may be formed on the second surface 211b of the second semiconductor substrate 210. The first transistors TR1 may include logic transistors. The logic transistors may include a reset transistor, a selection transistor, and a drive transistor.

The second dielectric layer 220 may cover the first surface 211a of the second semiconductor substrate 210. The second dielectric layer 220 may be formed of a multiple layer including, for example, at least one selected from a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, and a porous low-k dielectric layer. The second dielectric layer 220 may include therein multi-layered second wiring patterns 222. The second wiring patterns 222 may be electrically connected to the second upper conductive pad 280. A portion of the second upper conductive pad 280 may be exposed on and coplanar with the second top surface 201a, or the top surface of the second dielectric layer 220.

The third dielectric layer 230 may cover the second surface 211b of the second semiconductor substrate 210, and may cover the first transistors TR1 on the second surface 211b of the second semiconductor substrate 210. The third dielectric layer 230 may be formed of a multiple layer including, for example, at least one selected from a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, and a porous low-k dielectric layer. The third dielectric layer 230 may include therein multi-layered third wiring patterns 232. The first transistors TR1 may be electrically connected to the third wiring patterns 232 in the third dielectric layer 230. For example, the third wiring patterns 232 may be connected to the first transistors TR1 through connection contacts CNT. The third wiring patterns 232 may be electrically connected to the second lower conductive pad 290. A portion of the second lower conductive pad 290 may be exposed on and coplanar with the second bottom surface 201b, or the bottom surface of the third dielectric layer 230.

The second semiconductor substrate 210 may include a second through via TSV2 that penetrates the second semiconductor substrate 210. The second through via TSV2 may penetrate a portion of the second dielectric layer 220 to come into electrical connection with the second wiring patterns 222 or the second upper conductive pad 280. The second through via TSV2 may penetrate a portion of the third dielectric layer 230 to come into electrical connection with the third wiring patterns 232. The first transistors TR1 may be electrically connected to the first semiconductor chip 100 through the connection contacts CNT, the third wiring patterns 232, the second through via TSV2, and the second upper conductive pad 280.

A configuration of the second through via TSV2 will be discussed in detail below with reference to FIG. 2.

Referring to FIGS. 2 to 5, the second semiconductor substrate 210 may have an opening OP that vertically penetrates the second semiconductor substrate 210. The opening OP may completely penetrate the second semiconductor substrate 210, and may penetrate a portion of the third dielectric layer 230 to expose a top surface 234a of one 234 of the third wiring patterns 232. The third wiring pattern 234 exposed by the opening OP may be connected through the connection contact CNT to the first transistors TR1. In this case, the second through via TSV2 may be a vertical connection terminal that directly connects the first semiconductor chip 100 to the first transistors TR1 of the second semiconductor chip 200. The first transistor TR1 connected to the second through via TSV2 may be a selection transistor SX. Differently from that shown in FIG. 2, the third wiring pattern 234 exposed by the opening OP may not be connected to the first transistors TR1. In this case, the second through via TSV2 may be a vertical connection terminal that directly connects the first semiconductor chip 100 to the third semiconductor chip 300.

The second through via TSV2 may be disposed in the opening OP. The second through via TSV2 may completely penetrate the second semiconductor substrate 210, and may penetrate a portion of the third dielectric layer 230 and a portion of the second dielectric layer 220. For example, the second through via TSV2 may extend along the opening OP to be coupled to the third wiring pattern 234, and may penetrate a portion of the second dielectric layer 220 to be coupled to the second upper conductive pad 280. The second through via TSV2 may be spaced apart from an inner lateral surface or inner side surface of the opening OP. For example, the second through via TSV2 may be spaced apart from the second semiconductor substrate 210 and the third dielectric layer 230. The second through via TSV2 may include a metallic material, such as tungsten (W).

A spacer structure SS may be provided adjacent to the second through via TSV2. The spacer structure SS may separate the second through via TSV2 from the second semiconductor substrate 210 and the third dielectric layer 230. The spacer structure SS may include a first liner layer LL1, a capping layer CL, and an air gap AG.

The first liner layer LL1 may conformally cover bottom and inner lateral or side surfaces of the opening OP. For example, the first liner layer LL1 may have a hollow cylindrical shape. As shown in FIG. 2, the second through via TSV2 may penetrate the first liner layer LL1 positioned on the bottom surface of the opening OP, thereby being coupled to the third wiring pattern 234. Alternatively, as shown in FIG. 3, the second through via TSV2 may penetrate the first liner layer LL1 positioned on the bottom surface of the opening OP, and may also penetrate a portion of the third wiring pattern 234. For example, the second through via TSV2 may be inserted into the third wiring pattern 234. The first liner layer LL1 positioned on the inner lateral surface of the opening OP may be spaced apart from the second through via TSV2. When viewed in plan as shown in FIG. 5, the first liner layer LL1 positioned on the inner lateral surface of the opening OP may surround the second through via TSV2. For example, the second through via TSV2 may vertically penetrate an inner space of the first liner layer LL1 shaped like a cylinder. The first liner layer LL1 may extend onto the first surface 211a of the second semiconductor substrate 210. On the first surface 211a of the second semiconductor substrate 210, the first liner layer LL1 may be interposed between the second semiconductor substrate 210 and the second dielectric layer 220. The first liner layer LL1 may include a dielectric material. The first liner layer LL1 may include a different material from that of the third dielectric layer 230. The first liner layer LL1 may include, for example, silicon nitride (SiN). Alternatively, the first liner layer LL1 may include silicon oxide (SiO) or silicon oxynitride (SiON).

The capping layer CL may be provided on a bottom surface of the second dielectric layer 220. Between the first surface 211a of the second semiconductor substrate 210 and the bottom surface of the second dielectric layer 220, the capping layer CL may be interposed between the first liner layer LL1 and the second dielectric layer 220. The capping layer CL may extend between the second dielectric layer 220 and the second through via TSV2. For example, the capping layer CL may cover the first liner layer LL1 on the first surface 211a of the second semiconductor substrate 210. The capping layer CL may separate the second through via TSV2 from the second dielectric layer 220. The capping layer CL may include a dielectric material. The capping layer CL may include a different material from that of the first liner layer LL1. The capping layer CL may include silicon oxide (SiO). Alternatively, the capping layer CL may include silicon nitride (SiN) or silicon oxynitride (SiON).

The air gap AG may be defined by the first liner layer LL1, the second through via TSV2, and the capping layer CL. For example, the air gap AG may be provided by the first liner layer LL1 shaped like a cylinder and the capping layer CL that covers an inner space of the first liner layer LL1, and the second through via TSV2 may vertically penetrate a center of the air gap AG. In this configuration, the capping layer CL may extend from the first surface 211a of the second semiconductor substrate 210 through an upper side of the air gap AG to between the second dielectric layer 220 and a lateral or side surface of the second through via TSV2. The air gap AG may be filled with vacuum or air. When viewed in a direction from the second through via TSV2 toward the first liner layer LL1, the air gap AG may have a width ranging from about 10 nm to about 10 μm. For example, the width of the air gap AG may range from about 10 nm to about 1 μm.

FIGS. 2 and 3 depict that a flat shape is given to the capping layer CL positioned on the bottom surface of the second dielectric layer 220, but the present inventive concepts are not limited thereto. As shown in FIG. 4, a portion CLP of the capping layer CL may extend into the air gap AG. For example, on the air gap AG, the portion CLP of the capping layer CL may protrude in a direction toward the third dielectric layer 230. The portion CLP of the capping layer CL may have a bottom end located at a lower vertical level than that of the first surface 211a of the second semiconductor substrate 210.

According to some embodiments of the present inventive concepts, the second through via TSV2 may penetrate the second semiconductor substrate 210 formed of silicon (Si), and the second through via TSV2 and the second semiconductor substrate 210 may be electrically insulated through the air gap AG whose dielectric constant is 1 or almost 1, which may result in achievement of superior electrical properties, compared to a case where the second through via TSV2 and the second semiconductor substrate 210 are electrically insulated from each other through a silicon oxide layer whose dielectric constant ranges from about 3.8 to about 4.2. For example, there may be a reduction in tunneling effect or parasitic capacitance between the second through via TSV2 and the second semiconductor substrate 210. Accordingly, the semiconductor package 10 may improve in electrical properties.

In addition, when the second through via TSV2 and the second semiconductor substrate 210 are formed of different materials from each other, a coefficient of thermal expansion (CTE) mismatch may cause distortion of the second through via TSV2. In this case, because the first liner layer LL1 and the air gap AG are present between the second through via TSV2 and the second semiconductor substrate 210, there may be essentially no risk of direct contact of the second through via TSV2 with the second semiconductor substrate 210. As discussed above, as the air gap AG can serve as a stress buffer, a stress may be vanished or reduced to a level which is insufficient to influence one or both of the second through via TSV2 and the second semiconductor substrate 210. As a result, the semiconductor package 10 may increase in structural stability.

Referring back to FIGS. 1 to 5, the third semiconductor chip 300 may include a third semiconductor substrate 310 and a fourth dielectric layer 320 on the third semiconductor substrate 310. The fourth dielectric layer 320 may have a top surface that corresponds to the third top surface 301a.

The third semiconductor substrate 310 may include a semiconductor material. For example, the third semiconductor substrate 310 may be a silicon (Si) substrate.

A plurality of second transistors TR2 may be disposed on the third semiconductor substrate 310. For example, the second transistors TR2 may be formed on a top surface of the third semiconductor substrate 310. The second transistors TR2 may include memory transistors.

The fourth dielectric layer 320 may cover a top surface of the third semiconductor substrate 310. The fourth dielectric layer 320 may be formed of a multiple layer including, for example, at least one selected from a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, and a porous low-k dielectric layer. The fourth dielectric layer 320 may be provided therein with multi-layered fourth wiring patterns 322 and capacitors including bottom electrodes. The second transistors TR2 may be electrically connected to the fourth wiring patterns 322 in the fourth dielectric layer 320. The fourth wiring patterns 322 may be electrically connected to the third upper conductive pad 380. A portion of the third upper conductive pad 380 may be exposed on and coplanar with the third top surface 301a, or the top surface of the fourth dielectric layer 320.

In the embodiments that follow, a detailed description of technical features repetitive to those discussed with reference to FIGS. 1 to 4 may be omitted for convenience of description and in the interest of brevity, and a difference thereof will be discussed in detail. The same reference numerals may be allocated to the same components as those of the semiconductor package according to some embodiments of the present inventive concepts.

FIGS. 6 to 8 are enlarged views illustrating section A of FIG. 1. FIG. 9 is a plan view illustrating a spacer structure.

Referring to FIGS. 1 and 6 to 9, a spacer structure SS' may be provided adjacent to the second through via TSV2. The spacer structure SS' may separate the second through via TSV2 from the second semiconductor substrate 210 and the third dielectric layer 230. The spacer structure SS' may include a first liner layer LL1, a second liner layer LL2, a capping layer CL, and an air gap AG.

The first liner layer LL1 may conformally cover the bottom and inner lateral or side surfaces of the opening OP. As shown in FIG. 6, the second through via TSV2 may penetrate the first liner layer LL1 positioned on the bottom surface of the opening OP, thereby being coupled to the third wiring pattern 234. Alternatively, as shown in FIG. 7, the second through via TSV2 may penetrate the first liner layer LL1 positioned on the bottom surface of the opening OP, thereby being inserted into the third wiring pattern 234. The first liner layer LL1 positioned on the inner lateral surface of the opening OP may be spaced apart from the second through via TSV2. When viewed in plan as shown in FIG. 9, the first liner layer LL1 positioned on the inner lateral surface of the opening OP may surround the second through via TSV2. The first liner layer LL1 may extend onto the first surface 211a of the second semiconductor substrate 210.

The second liner layer LL2 may cover the lateral surface of the second through via TSV2. As shown in FIG. 9, the second liner layer LL2 may surround the second through via TSV2 and may contact the lateral surface of the second through via TSV2. In the second dielectric layer 220, the second liner layer LL2 may be interposed between the second dielectric layer 220 and the second through via TSV2. As shown in FIG. 6, the second liner layer LL2 may penetrate the first liner layer LL1 positioned on the bottom surface of the opening OP, thereby being coupled to the third wiring pattern 234. Alternatively, as shown in FIG. 7, the second liner layer LL2 may penetrate the first liner layer LL1 positioned on the bottom surface of the opening OP, thereby being inserted into the third wiring pattern 234. A bottom end of the second liner layer LL2 may be located at the same vertical level as that of a bottom end of the second through via TSV2. The second liner layer LL2 may be spaced apart from the first liner layer LL1 positioned on the inner lateral surface of the opening OP. The second liner layer LL2 may include a dielectric material. The second liner layer LL2 may include a different material from that of the third dielectric layer 230. The second liner layer LL2 may include, for example, silicon nitride (SiN). Alternatively, the second liner layer LL2 may include silicon oxide (SiO) or silicon oxynitride (SiON).

According to some embodiments, the first liner layer LL1 and the second liner layer LL2 may be provided as a single layer. As shown in FIG. 8, a liner layer LL may conformally cover the first surface 211a of the second semiconductor substrate 210, the bottom and inner lateral surfaces of the opening OP, and the lateral surface of the second through via TSV2. On the first surface 211a of the second semiconductor substrate 210, the liner layer LL may be interposed between the second semiconductor substrate 210 and the second dielectric layer 220. In the second dielectric layer 220, the liner layer LL may be interposed between the capping layer CL and the second through via TSV2. The following description will focus on the embodiment of FIG. 6.

The capping layer CL may be provided on a bottom surface of the second dielectric layer 220. Between the first surface 211a of the second semiconductor substrate 210 and the bottom surface of the second dielectric layer 220, the capping layer CL may be interposed between the first liner layer LL1 and the second dielectric layer 220. The capping layer CL may extend between the second dielectric layer 220 and the second through via TSV2, for example, between the second dielectric layer 220 and the second liner layer LL2. For example, the capping layer CL may cover the first liner layer LL1 on the first surface 211a of the second semiconductor substrate 210. The capping layer CL and the second liner layer LL2 may separate the second through via TSV2 from the second dielectric layer 220.

The air gap AG may be defined by the first liner layer LL1, the second liner layer LL2, and the capping layer CL. For example, the air gap AG may be provided by the first liner layer LL1 shaped like a cylinder and the capping layer CL that covers an inner space of the first liner layer LL1, and the second through via TSV2 and the second liner layer LL2 may vertically penetrate a center of the air gap AG. In this configuration, the capping layer CL may extend from the first surface 211a of the second semiconductor substrate 210 through an upper side of the air gap AG to between the second dielectric layer 220 and the second liner layer LL2. The air gap AG may be filled with vacuum or air. When viewed in a direction from the second through via TSV2 toward the first liner layer LL1, the air gap AG may have a width ranging from about 10 nm to about 1 μm.

FIGS. 6 and 7 depict that a flat shape is given to the capping layer CL positioned on the bottom surface of the second dielectric layer 220, but the present inventive concepts are not limited thereto. A portion of the capping layer CL may extend into the air gap AG. For example, on the air gap AG, the portion of the capping layer CL may protrude in a direction toward the third dielectric layer 230. The portion of the capping layer CL may have a bottom end located at a lower vertical level than that of the first surface 211a of the second semiconductor substrate 210.

According to some embodiments of the present inventive concepts, as the second through via TSV2 and the second semiconductor substrate 210 are electrically insulated from each other through the air gap AG, extremely excellent electrical properties may be achieved. Moreover, when the second through via TSV2 formed of tungsten (W) or copper (Cu) which is easily and extremely diffusive, the second liner layer LL2 including nitride (e.g., silicon nitride (SiN)) may additionally serve as a barrier that prevents diffusion of tungsten (W) or copper (Cu). Furthermore, when the second through via TSV2 is remarkably distorted, the second liner layer LL2 may usually be preferentially fractured. As discussed above, as the second liner layer LL2 serves as a stress buffer, a stress may disappear or be reduced to a level which is insufficient to influence one or both of the second through via TSV2 and the second semiconductor substrate 210.

FIG. 10 is a cross-sectional view illustrating a semiconductor module according to some embodiments of the inventive concepts.

Referring to FIG. 10, a semiconductor module 20 according to the present embodiment may be configured such that the semiconductor package 10 of FIG. 1 may be attached through an adhesion layer to a package substrate 400. The adhesion layer may be interposed between the third semiconductor chip 300 and the package substrate 400. A wire 410 may be provided to connect the package substrate 400 to the first upper conductive pad 180 of the first semiconductor chip 100. A holder 420 may be disposed on the package substrate 400. The holder 420 may be spaced apart from the semiconductor package 10. The holder 420 may be attached through an adhesion layer to the package substrate 400. The holder 420 may have a closed loop shape when viewed in plan. The holder 420 may have a hollow structure adjacent to an edge of the semiconductor package 10. The holder 420 may be formed of a polymeric material, such as polyamide. A transparent substrate 430 may be attached through an adhesion layer to the holder 420. The transparent substrate 430 may be formed of transparent glass or plastic. The transparent substrate 430 may be spaced apart from the semiconductor package 10, providing an empty space S. Although not shown, external connection terminals, such as solder bumps, may be attached to a lower portion of the package substrate 400. FIG. 10 depicts that the semiconductor package 10 of FIG. 1 is attached, but the semiconductor package 10 may be one of the semiconductor packages discussed with reference to FIGS. 2 to 9. Alternatively, the semiconductor package 10 may include a combination of the semiconductor packages discussed above.

FIGS. 11A to 20A are cross-sectional views illustrating a method of fabricating a semiconductor package according to some embodiments of the inventive concepts. FIGS. 11B to 20B are enlarged views illustrating section B of FIGS. 11A to 20A, respectively. FIGS. 14C, 16C, 18C, and 19C are enlarged views of section B respectively depicted in FIGS. 14A, 16A, 18A, and 19A, illustrating other examples of FIGS. 14B, 16B, 18B, and 19B, respectively. FIGS. 11A to 20A, 11B to 20B, 14C, 16C, 18C, and 19C explain a method of fabricating a semiconductor package, for example, a method of forming a second semiconductor chip. FIGS. 11A to 20A omit a configuration of a spacer structure, and the spacer structure will be discussed in detail in FIGS. 11B to 20B, 14C, 16C, 18C, and 19C.

Referring to FIGS. 1, 11A, and 11B, a second semiconductor substrate 210 may be provided. The second semiconductor substrate 210 may include a semiconductor material. The second semiconductor substrate 210 may have a first surface 211a and a second surface 211b that are opposite to each other. First transistors TR1 may be formed on the second surface 211b of the second semiconductor substrate 210.

A third dielectric layer 230 and third wiring patterns 232 may be formed on the second semiconductor substrate 210. For example, a dielectric material covering the first transistors TR1 may be coated on the second surface 211b of the second semiconductor substrate 210, thereby forming one dielectric layer. A conductive layer may be formed on the dielectric layer, and then the conductive layer may be patterned to form one wiring layer. The formation of the dielectric layer and the conductive layer may be repeated to form the third dielectric layer 230 and the third wiring patterns 232. A second lower conductive pad 290 may be formed on a lowermost dielectric layer, and the second lower conductive pad 290 may be connected to the third wiring patterns 232 and surrounded by the third dielectric layer 230. The third wiring patterns 232 may be connected to the first transistors TR1. The third dielectric layer 230 may include silicon oxide (SiO).

Afterwards, a first opening OP1 may be formed on the second semiconductor substrate 210. The first opening OP1 may correspond to the opening OP discussed with reference to FIG. 2. For example, a mask pattern may be formed on the first surface 211a of the second semiconductor substrate 210, and then the mask pattern may be used as an etching mask to etch the second semiconductor substrate 210. In this step, a portion of the third dielectric layer 230 may be etched together with the second semiconductor substrate 210. Therefore, the first opening OP1 may completely penetrate the second semiconductor substrate 210, and may penetrate a portion of the third dielectric layer 230 to expose the third wiring pattern 234.

Referring to FIGS. 1, 12A, and 12B, a first liner layer LL1 may be formed on the second semiconductor substrate 210. For example, the first liner layer LL1 may be formed by depositing a dielectric material on the first surface 211a of the second semiconductor substrate 210. The first liner layer LL1 may conformally cover the first surface 211a of the second semiconductor substrate 210, an inner lateral or side surface of the first opening OP1, and a bottom surface of the first opening OP1. The first liner layer LL1 may include silicon nitride (SiN) or silicon oxynitride (SiON).

Referring to FIGS. 1, 13A, and 13B, a sacrificial layer 500 may be formed on the second semiconductor substrate 210. For example, the sacrificial layer 500 may be formed by coating or depositing a dielectric material on the first surface 211a of the second semiconductor substrate 210. The dielectric material may cover the first liner layer LL1. For example, the dielectric material may cover the first surface 211a of the second semiconductor substrate 210 and may fill the first opening OP1. The dielectric material may have an etch selectivity with respect to the first liner layer LL1. For example, the dielectric material may include silicon oxide (SiO).

Referring to FIGS. 1, 14A, and 14B, the sacrificial layer 500 may be etched to form a second opening OP2. For example, a mask pattern may be formed on the sacrificial layer 500, and then the mask pattern may be used as an etching mask to etch the sacrificial layer 500. The second opening OP2 may be positioned within the first opening OP1. The second opening OP2 may be spaced apart from the first liner layer LL1 positioned on the inner lateral surface of the first opening OP1. For example, the sacrificial layer 500 may remain between the second opening OP2 and the first liner layer LL1 positioned on the inner lateral surface of the first opening OP1. On the bottom surface of the first opening OP1, a portion of the first liner layer LL1 may be etched together with the sacrificial layer 500. Therefore, the second opening OP2 may expose the third wiring pattern 234.

FIG. 14B depicts that, on the third wiring pattern 234, the portion of the first liner layer LL1 is etched together with the sacrificial layer 500, but the present inventive concepts are not limited thereto. As shown in FIG. 14C, on the bottom surface of the first opening OP1, a portion of the third wiring pattern 234 may be etched together with the sacrificial layer 500 and the portion of the first liner layer LL1. For example, the second opening OP2 may penetrate the sacrificial layer 500 and the first liner layer LL1 to extend into the third wiring pattern 234. According to FIG. 14C, a semiconductor package may be fabricated as is discussed with reference to FIG. 3. The following will further describe the embodiment of FIG. 14B.

Referring to FIGS. 1, 15A, and 15B, a second through via TSV2 may be formed in the second opening OP2. For example, the second opening OP2 may be filled with a conductive material to form the second through via TSV2. For more detail, a conductive layer may be formed on the sacrificial layer 500. The conductive layer may cover a top surface of the sacrificial layer 500 and may fill the second opening OP2. Thereafter, a planarization process may be performed on the sacrificial layer 500 until the top surface of the sacrificial layer 500 is exposed. After the planarization process, the conductive layer remaining in the second opening OP2 may be formed into the second through via TSV2. The second through via TSV2 may be coupled to the third wiring pattern 234.

FIGS. 15A and 15B depict that the second liner layer (see LL2 of FIG. 6) is not formed, and that the first liner layer LL1 and the second through via TSV2 are formed, but the present inventive concepts are not limited thereto.

Referring to FIGS. 1, 16A, and 16B, a second liner layer LL2 may be formed on the second opening OP2 in the resultant structure of FIGS. 14A and 14B. For example, a dielectric layer may be conformally deposited to the top surface of the sacrificial layer 500 and on bottom and inner lateral or side surfaces of the second opening OP2, and then the dielectric layer may undergo an anisotropic etching process to form the second liner layer LL2. Therefore, the second liner layer LL2 may remain only on the inner lateral surface of the second opening OP2, and the third wiring pattern 234 may be exposed. The second liner layer LL2 may include silicon nitride (SiN) or silicon oxynitride (SiON).

In some embodiments, as shown in FIG. 14C, the second opening OP2 may penetrate the sacrificial layer 500 and the first liner layer LL1 to extend into the third wiring pattern 234. In this case, as shown in FIG. 16C, the second liner layer LL2 may also extend into the third wiring pattern 234. According to FIG. 16C, a semiconductor package may be fabricated which is discussed with reference to FIG. 7. The following will further describe the embodiment of FIG. 16B.

Referring to FIGS. 1, 17A, and 17B, a second through via TSV2 may be formed in the second opening OP2. For example, the second opening OP2 may be filled with a conductive material to form the second through via TSV2. For more detail, a conductive layer may be formed on the second liner layer LL2. The conductive layer may cover a top surface of the second liner layer LL2 and may fill the second liner layer LL2 in the second opening OP2. After that, a planarization process may be performed on the sacrificial layer 500 until the top surface of the sacrificial layer 500 is exposed. After the planarization process, the conductive layer remaining in the second opening OP2 may be formed into the second through via TSV2. The second through via TSV2 may be coupled to the third wiring pattern 234. According to FIGS. 16A, 16B, 17A, and 17B, a semiconductor package may be fabricated as is discussed with reference to FIG. 6. The following will further describe the embodiment of FIGS. 15A and 15B.

Referring to FIGS. 1, 18A, and 18B, the sacrificial layer 500 may be removed. Therefore, the first liner layer LL1 may be exposed, and the first opening OP1 may have an empty space other than a space occupied by the first liner layer LL1 and the second through via TSV2.

Afterwards, a decomposition layer 600 may be formed in the first opening OP1. For example, a decomposition material layer may be formed on the first liner layer LL1. The decomposition material layer may cover a top surface of the first liner layer LL1, and may fill the first opening OP1 (e.g., the empty space other than the space occupied by the first liner layer LL1 and the second through via TSV2). After that, an etch-back process may be performed on the decomposition material layer. The etch-back process may continue until the decomposition material layer remains only in the first opening OP1. The decomposition material layer may include a material which can be decomposed with heat or ultraviolet light. FIG. 18B depicts that the decomposition layer 600 is formed to have a top surface at the same vertical level as that of the top surface of the first liner layer LL1, but the present inventive concepts are not limited thereto. As shown in FIG. 18C, depending on an etchant used in the etch-back process, the decomposition layer 600 may have a top surface at a lower vertical level than that of the top surface of the first liner layer LL1, and in this case, the top surface of the decomposition layer 600 may have a downwardly concave shape.

Referring to FIGS. 1, 19A, and 19B, a capping layer CL may be formed on the first surface 211a of the second semiconductor substrate 210. For example, the capping layer CL may be formed by depositing a dielectric layer on the second through via TSV2 and the top surface of the first liner layer LL1. The capping layer CL may conformally cover the top surface of the first liner layer LL1 and lateral and top surfaces of the second through via TSV2. In this step, the capping layer CL may cover the top surface of the decomposition layer 600, and the decomposition layer 600 may be surrounded by the capping layer CL, the first liner layer LL1, and the second through via TSV2. The capping layer CL may include silicon oxide (SiO).

In some embodiments, as shown in FIG. 18C, the decomposition layer 600 may be formed to have a concave shape on its top surface. In this case, as shown in FIG. 19C, the capping layer CL may fill a concave portion of the top surface thereof. For example, a portion of the capping layer CL may have a shape that protrudes either toward the decomposition layer 600 or into the first opening OP1. According to FIGS. 18C and 19C, a semiconductor package may be fabricated as is discussed with reference to FIG. 4. The following will further describe the embodiment of FIGS. 19A and 19B.

Referring to FIGS. 1, 20A, and 20B, the decomposition layer 600 may be removed. For example, heat or ultraviolet light may be provided onto the second semiconductor substrate 210. The heat or ultraviolet light may eliminate the decomposition layer 600, and an empty inner space may be formed surrounded by the first liner layer LL1, the second through via TSV2, and the capping layer CL. The inner space may be an air gap AG filled with vacuum or air.

According to some embodiments of the present inventive concepts, the decomposition layer 600 may be used to form the air gap AG between the second semiconductor substrate 210 and the second through via TSV2. Therefore, the air gap AG may be formed only on a required region. In addition, the first liner layer LL1 may be formed thin enough to allow the air gap AG to have a sufficient thickness, and increased insulation may be provided between the second semiconductor substrate 210 and the second through via TSV2. As a result, it may be possible to fabricate a semiconductor package 10 with improved electrical properties.

Thereafter, a second dielectric layer 220 and second wiring patterns 222 may be formed. For example, one dielectric layer may be formed by coating a dielectric material on the first surface 211a of the second semiconductor substrate 210. A conductive layer may be formed on the dielectric layer, and then the conductive layer may be patterned to form one wiring layer. The formation of the dielectric layer and the conductive layer may be repeated to form the second dielectric layer 220 and the second wiring patterns 222. A second upper conductive pad 280 may be formed in an uppermost dielectric layer, and the second upper conductive pad 280 may be connected to the second through via TSV2 or the second wiring patterns 222 and may be surrounded by the second dielectric layer 220. The second dielectric layer 220 may include silicon oxide (SiO).

Through the processes mentioned above, a second semiconductor chip 200 may be formed.

Referring to FIGS. 1 and 2, a first semiconductor chip 100 may be provided. The first semiconductor chip 100 may be the same as that discussed with reference to FIG. 1. For example, the first semiconductor chip 100 may include a first upper conductive pad 180 disposed on a first top surface 101a thereof. The first semiconductor chip 100 may include a first lower conductive pad 190 disposed adjacent to a first bottom surface 101b thereof. The first semiconductor chip 100 may be, for example, an image sensor chip.

The first semiconductor chip 100 may be mounted on the second semiconductor chip 200. For example, the first semiconductor chip 100 and the second semiconductor chip 200 may be aligned to allow the first lower conductive pad 190 of the first semiconductor chip 100 to face the second upper conductive pad 280 of the second semiconductor chip 200. After the first and second semiconductor chips 100 and 200 are in contact with each other, an annealing process may be performed on the first and second semiconductor chips 100 and 200. The annealing process may cause bonding between the first lower conductive pad 190 and the second upper conductive pad 280. For example, the first lower conductive pad 190 and the second upper conductive pad 280 may be combined into a single unitary body. Automatic bonding may be carried out between the first lower conductive pad 190 and the second upper conductive pad 280. For example, the first lower conductive pad 190 and the second upper conductive pad 280 may be formed of the same material (e.g., copper (Cu)), and may be bonded due to an intermetallic hybrid bonding process resulting from surface activation on an interface between the first lower conductive pad 190 and the second upper conductive pad 280 that are in contact with each other. The annealing process may induce bonding between the first dielectric layer 120 and the second dielectric layer 220.

A third semiconductor chip 300 may be provided. The third semiconductor chip 300 may be the same as that discussed with reference to FIG. 1. For example, the third semiconductor chip 300 may include a third upper conductive pad 380 disposed adjacent to a third top surface 301a thereof. The third semiconductor chip 300 may be, for example, a memory chip that stores data produced from the second semiconductor chip 200.

The third semiconductor chip 300 may be mounted below the second semiconductor chip 200. For example, the second semiconductor chip 200 and the third semiconductor chip 300 may be aligned to allow the second lower conductive pad 290 of the second semiconductor chip 200 to face the third upper conductive pad 380 of the third semiconductor chip 300. After the second and third semiconductor chips 200 and 300 are in contact with each other, an annealing process may be performed on the second and third semiconductor chips 200 and 300. The annealing process may cause bonding between the second lower conductive pad 290 and the third upper conductive pad 380. For example, the second lower conductive pad 290 and the third upper conductive pad 380 may be combined into a single unitary body. Automatic bonding may be carried out between the second lower conductive pad 290 and the third upper conductive pad 380. For example, the second lower conductive pad 290 and the third upper conductive pad 380 may be formed of the same material (e.g., copper (Cu)), and may be bonded due to an intermetallic hybrid bonding process resulting from surface activation on an interface between the second lower conductive pad 290 and the third upper conductive pad 380 that are in contact with each other. The annealing process may induce bonding between the third dielectric layer 230 and the fourth dielectric layer 320.

FIGS. 21A to 25A illustrate cross-sectional views showing a method of fabricating a semiconductor package according to some embodiments of the present inventive concepts. FIGS. 21B to 25B illustrate enlarged views showing section B of FIGS. 21A to 25A, respectively. FIGS. 21A to 25A and 21B to 25B explain a method of fabricating a semiconductor package, for example, a method of forming a second semiconductor chip. FIGS. 21A to 25A omit a configuration of a spacer structure, and the spacer structure will be discussed in detail in FIGS. 21B to 25B.

Referring to FIGS. 1, 21A, and 21B, a sacrificial layer 500 may be formed on the second semiconductor substrate 210 in a resultant structure of FIGS. 11A and 11B. For example, the sacrificial layer 500 may be formed by coating or depositing a dielectric material on the first surface 211a of the second semiconductor substrate 210. The dielectric material may cover the first surface 211a of the second semiconductor substrate 210 and may fill the first opening OP1. The dielectric material may have an etch selectivity with respect to the second semiconductor substrate 210.

The sacrificial layer 500 may be etched to form a second opening OP2. For example, a mask pattern may be formed on the sacrificial layer 500, and then the mask pattern may be used as an etching mask to etch the sacrificial layer 500. The second opening OP2 may be positioned within the first opening OP1. The second opening OP2 may be spaced apart from an inner lateral or side surface of the first opening OP1. For example, the sacrificial layer 500 may remain between the second opening OP2 and the inner lateral surface of the first opening OP1. The second opening OP2 may expose the third wiring pattern 234.

Referring to FIGS. 1, 22A, and 22B, a second through via TSV2 may be formed in the second opening OP2. For example, the second opening OP2 may be filled with a conductive material to form the second through via TSV2. For more detail, a conductive layer may be formed on the sacrificial layer 500. The conductive layer may cover a top surface of the sacrificial layer 500 and may fill the second opening OP2. Thereafter, a planarization process may be performed on the sacrificial layer 500 until the top surface of the sacrificial layer 500 is exposed. After the planarization process, the conductive layer remaining in the second opening OP2 may be formed into the second through via TSV2. The second through via TSV2 may be coupled to the third wiring pattern 234.

The sacrificial layer 500 may be removed. Therefore, the second semiconductor substrate 210 may be exposed, and the first opening OP1 may have an empty space other than a space occupied by the second through via TSV2.

Referring to FIGS. 1, 23A, and 23B, a liner layer LL may be formed on the second semiconductor substrate 210. For example, the liner layer LL may be formed by depositing a dielectric material on the first surface 211a of the second semiconductor substrate 210. The liner layer LL may conformally cover the first surface 211a of the second semiconductor substrate 210, an inner lateral or side surface of the first opening OP1, a bottom surface of the first opening OP1, and lateral and top surfaces of the second through via TSV2. The liner layer LL may include silicon nitride (SiN) or silicon oxynitride (SiON).

Referring to FIGS. 1, 24A, and 24B, a decomposition layer 600 may be formed in the first opening OP1. For example, a decomposition material layer may be formed on the liner layer LL. The decomposition material layer may cover a top surface of the liner layer LL, and may fill the first opening OP1 (e.g., the empty space other than the space occupied by the second through via TSV2). After that, an etch-back process may be performed on the decomposition material layer. The etch-back process may continue until the decomposition material layer remains only in the first opening OP1. The decomposition material layer may include a material which can be decomposed with heat or ultraviolet light. FIG. 24B depicts that the decomposition layer 600 is formed to have a top surface located at the same vertical level as that of the top surface of the liner layer LL positioned on the first surface 211a of the second semiconductor substrate 210, but the present inventive concepts are not limited thereto. Depending on an etchant used in the etch-back process, the top surface of the decomposition layer 600 may have a downwardly concave shape.

A capping layer CL may be formed on the first surface 211a of the second semiconductor substrate 210. For example, the capping layer CL may be formed by depositing a dielectric layer on the second through via TSV2 and the top surface of the liner layer LL. The capping layer CL may conformally cover the top surface of the liner layer LL and the top surface of the decomposition layer 600. In this case, the decomposition layer 600 may be surrounded by the capping layer CL and the liner layer LL. The capping layer CL may include silicon oxide (SiO).

Referring to FIGS. 1, 25A, and 25B, the decomposition layer 600 may be removed. For example, heat or ultraviolet light may be provided onto the second semiconductor substrate 210. The heat or ultraviolet light may eliminate the decomposition layer 600, and an empty space may be formed surrounded by the liner layer LL and the capping layer CL. The inner space may be an air gap AG filled with vacuum or air.

Through the processes mentioned above, a second semiconductor chip 200 may be formed.

Referring to FIGS. 1 and 2, a first semiconductor chip 100 may be provided. The first semiconductor chip 100 may include a first upper conductive pad 180 disposed on a first top surface 101a thereof. The first semiconductor chip 100 may include a first lower conductive pad 190 disposed adjacent to a first bottom surface 101b thereof. The first semiconductor chip 100 may be, for example, an image sensor chip. The first semiconductor chip 100 may be mounted on the second semiconductor chip 200.

A third semiconductor chip 300 may be provided. The third semiconductor chip 300 may include a third upper conductive pad 380 disposed adjacent to a third top surface 301a thereof. The third semiconductor chip 300 may be, for example, a memory chip that stores data produced from the second semiconductor chip 200. The third semiconductor chip 300 may be mounted below the second semiconductor chip 200.

A semiconductor package according to some embodiments of the present inventive concepts may be configured such that a through via may penetrate a semiconductor substrate formed of silicon (Si), and that the through via and the semiconductor substrate may be electrically insulated through an air gap whose dielectric constant is 1 or almost 1, which may result in achievement of remarkably excellent electrical properties, compared to a case where the through via and the semiconductor substrate are electrically insulated through a silicon oxide layer. For example, there may be a reduction in tunneling effect or parasitic capacitance between the through via and the semiconductor substrate. As a result, there may be provided a semiconductor package whose electrical properties are improved.

Further, when the through via and the semiconductor substrate are formed of different materials from each other, a coefficient of thermal expansion (CTE) mismatch may cause distortion of the through via. In this case, as a liner layer and an air gap are present between the through via and the semiconductor substrate, there may be essentially no risk of direct contact of the through via with the semiconductor substrate. As discussed above, as the air gap can serve as a stress buffer, a stress may be vanished or reduced to a level which is insufficient to influence one or both the through via and the semiconductor substrate. As a result, the semiconductor package may be provided to have increased structural stability.

Although the present inventive concepts have been described in connection with some embodiments of the present inventive concepts illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the scope of the present inventive concepts. The above disclosed embodiments should thus be considered illustrative and not restrictive.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

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