Patent Application
20250226366
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0003612, filed on Jan. 9, 2024 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.
Example embodiments relate to a semiconductor package. More particularly, example embodiments relate to a semiconductor package including a plurality of stacked chips.
A high bandwidth memory (HBM) package may include a plurality of memory chips stacked on a logic chip in a vertical direction, and the number of through electrodes in the logic chip increases and the pitch between the through electrodes decreases so that the HBM package may have a high capacity. Thus, a space for a passive element such as a capacitor in the logic chip may not be sufficient.
Example embodiments provide a semiconductor package having enhanced electrical characteristics.
According to example embodiments, there is provided a semiconductor package. The semiconductor package may include a logic chip, a redistribution wiring structure, memory chips and a molding member. The logic chip may include a first substrate and a passive element on a portion of the first substrate. The redistribution wiring structure may be on the logic chip, and may be electrically connected to the passive element. The memory chips may be sequentially stacked on the redistribution wiring structure in a vertical direction. The molding member may be on the logic chip, and may extend on sidewalls of the redistribution wiring structure and the memory chips. The passive element may not overlap the memory chips in the vertical direction.
According to example embodiments, there is provided a semiconductor package. The semiconductor package may include a logic die, a redistribution wiring structure, memory dies and a molding member. The logic die may include a substrate, a through electrode structure, a protective pattern structure and a capacitor. The substrate may include first and second surfaces opposite to each other in a vertical direction. The through electrode structure may extend through the substrate, and may include a protrusion portion protruding beyond the second surface of the substrate. The protective pattern structure may be on the second surface of the substrate, and may extend on a sidewall of the protrusion portion of the through electrode structure. A lower portion of the capacitor may extend into a portion of the substrate adjacent to the second surface thereof, and an upper portion of the capacitor may have the protective pattern structure thereon. The redistribution wiring structure may be on the logic die, and may be electrically connected to the capacitor. The memory dies may be sequentially stacked on the redistribution wiring structure. The molding member may be on the logic die, and may extend on sidewalls of the redistribution wiring structure and the memory dies. Each of the memory dies may not overlap the capacitor in the vertical direction.
According to example embodiments, there is provided a semiconductor package. The semiconductor package may include a buffer die, a redistribution wiring structure, core dies, an adhesion layer and a molding member. The buffer die may include a first substrate, a logic device, a first wiring structure, a first through electrode structure, a first protective pattern structure and a capacitor. The first substrate may include first and second surfaces opposite to each other in a vertical direction. The logic device may be provided in the first substrate. The first wiring structure may be electrically connected to the logic device. The first through electrode structure may extend through the first substrate in the vertical direction, and may include a first protrusion portion protruding beyond the second surface of the first substrate. The first protective pattern structure may be on the second surface of the first substrate, and may extend on a sidewall of the first protrusion portion of the first through electrode structure. A lower portion of the capacitor may extend into a portion of the first substrate adjacent to the second surface thereof, and an upper portion of the capacitor may have the first protective pattern structure thereon. The redistribution wiring structure may be disposed on the buffer die, and may be electrically connected to the capacitor. The core dies may be sequentially stacked on the redistribution wiring structure in the vertical direction. Adhesion layers may be provided between the redistribution wiring structure and a lowermost one of the core dies, and between respective ones of the core dies that are sequentially stacked. The molding member may be on the buffer die, and may extend on sidewalls of the redistribution wiring structure, the core dies, and the adhesion layers. The capacitor may not overlap the core dies in the vertical direction.
The semiconductor package in accordance with example embodiments may have sufficient passive elements even without an additional space for the passive elements, and thus the semiconductor package may have enhanced electrical characteristics and an enhanced integration degree.
The above and other aspects and features of the semiconductor package and the methods of manufacturing the same in accordance with example embodiments will become readily understood from detail descriptions that follow, with reference to the accompanying drawings. It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structure and/or processes, these various materials, layers, regions, pads, electrodes, patterns, structure and/or processes should not be limited by these terms. These terms are only used to distinguish one material, layer, region, pad, electrode, pattern, structure or process from another material, layer, region, pad, electrode, pattern, structure or process. Thus, “first”, “second” and/or “third” may be used selectively or interchangeably in describing each material, layer, region, electrode, pad, pattern, structure or process.
Hereinafter, a direction substantially perpendicular to an upper surface of a substrate may be referred to as a vertical direction, and a direction substantially parallel to the upper surface of the substrate may be referred to as a horizontal direction. The terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated elements, but do not preclude the presence of additional elements. The term “and/or” includes any and all combinations of one or more of the associated listed items. The term “connected” may be used herein to refer to a physical and/or electrical connection. When components or layers are referred to herein as “directly” on, or “in direct contact” or “directly connected,” no intervening components or layers are present.
Referring to
In example embodiments, the first semiconductor chip 100 may be a buffer die, and may include a logic device, e.g., a controller. Each of the second and third semiconductor chips 200 and 300 may be a core die, and may include a volatile memory device, e.g., DRAM device, SRAM device, etc., or a non-volatile memory device, e.g., flash memory device, EEPROM device, etc. Each of the second semiconductor chips 200 may be a middle core die, and the third semiconductor chip 300 may be a top core die.
The first semiconductor chip 100 may also be referred to as a logic chip or logic die, and each of the second and third semiconductor chips 200 and 300 may also be referred to as a memory chip or a memory die.
The first semiconductor chip 100 may include a first substrate 110 having first and second surfaces 112 and 114 opposite to each other in the vertical direction, a first through electrode structure 120 extending through the first substrate 110, a first insulating interlayer and a second insulating interlayer 130 sequentially stacked in the vertical direction beneath the first surface 112 of the first substrate 110, a first conductive pad 140 beneath the second insulating interlayer 130, a first conductive connection member 150 beneath the first conductive pad 140, and a first protective pattern structure 160 on the second surface 114 of the first substrate 110.
The first substrate 110 may include a semiconductor material, e.g., silicon, germanium, silicon-germanium, or a III-V group compound semiconductor, e.g., GaP, GaAs, GaSb, etc. In example embodiments, the first substrate 110 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.
A circuit device, e.g., a logic device may be disposed beneath the first surface 112 of the first substrate 110. The circuit device may include circuit patterns, which may be covered by the first insulating interlayer. The terms “surround” or “cover” or “fill” as may be used herein may not require completely surrounding or covering or filling the described elements or layers, but may, for example, refer to partially surrounding or covering or filling the described elements or layers, for example, with one or more discontinuities therein.
The second insulating interlayer 130 may contain a first wiring structure therein. The first wiring structure may include, e.g., wirings, vias, contact plugs, etc.
The first insulating interlayer and the second insulating interlayer 130 may include, e.g., silicon oxide or a low-k dielectric material, e.g., an oxide doped with carbon or fluorine. The wirings, the vias, the contact plugs, etc., may include a conductive material, e.g., a metal, a metal nitride, a metal silicide, etc.
The first conductive pad 140 may be disposed under the second insulating interlayer 130, and may contact the first wiring structure to be electrically connected thereto. In example embodiments, a plurality of first conductive pads 140 may be spaced apart from each other in the horizontal direction.
In example embodiments, the first conductive pad 140 may include a first seed pattern and a first conductive pattern sequentially stacked in the vertical direction downwardly from the second insulating interlayer. The first seed pattern may include, e.g., titanium, and the first conductive pattern may include, e.g., nickel, copper, gold, etc.
The first conductive connection member 150 may contact a lower surface of the first conductive pad 140. The first conductive connection member 150 may be, e.g., a conductive bump. The first conductive connection member 150 may include a metal, e.g., tin, or a tin alloy including, e.g., tin/silver, tin/copper, tin/indium, tin/silver/copper, etc.
The first through electrode structure 120 may extend through the first substrate 110 in the vertical direction. A protrusion portion of the first through electrode structure 120 may protrude upwardly (i.e., beyond the second surface 114 of the first substrate 110) in the vertical direction, and may be covered by the first protective pattern structure 160. A plurality of first through electrode structures 120 may be spaced apart from each other in the horizontal direction. In example embodiments, the first through electrode structure 120 may include a first through electrode extending in the vertical direction, a first barrier pattern covering a sidewall of the first through electrode, and a first insulation pattern covering an outer sidewall of the first barrier pattern.
The first through electrode may include a metal, e.g., copper, aluminum, etc., the first barrier pattern may include a metal nitride, e.g., titanium nitride, tantalum nitride, etc., and the first insulation pattern may include an oxide, e.g., silicon oxide or an insulating nitride, e.g., silicon nitride.
In an example embodiment, the first through electrode structure 120 may extend through the first protective pattern structure 160, the first substrate 110 and the first insulating interlayer to contact the first wiring structure, and may be electrically connected to the first conductive pad 140 by the first wiring structure.
Alternatively, the first through electrode structure 120 may extend through the first protective pattern structure 160, the first substrate 110 and the first insulating interlayer and the second insulating interlayer 130 to contact the first conductive pad 140, and may be electrically connected thereto. Alternatively, the first through electrode structure 120 may extend through the first protective pattern structure 160 and the first substrate 110 to contact one of the circuit patterns included in the circuit device covered by the first insulating interlayer, and may be electrically connected to the first conductive pad 140 by the one of the first circuit patterns and the first wiring structure.
The first protective pattern structure 160 may be disposed on the second surface 114 of the first substrate 110, and may surround an upper portion of the first through electrode structure 120.
In example embodiments, the first protective pattern structure 160 may include a first protective pattern and a second protective pattern sequentially stacked in the vertical direction on the second surface 114 of the first substrate 110. A portion of the first protective pattern adjacent to the first through electrode structure 120 may protrude upwardly in the vertical direction, and an upper surface of the portion of the first protective pattern may be substantially coplanar with an upper surface of the first through electrode structure 120. An outer sidewall of the portion of the first protective pattern may be covered by the second protective pattern.
The first protective pattern may include an oxide, e.g., silicon oxide, and the second protective pattern may include an insulating nitride, e.g., silicon nitride.
A passive element may be disposed at an upper portion of the first semiconductor chip 100, e.g., at a portion adjacent to the second surface 114 of the first semiconductor chip 100. In example embodiments, the passive element may not overlap the second and third semiconductor chips 200 and 300 in the vertical direction. Components or layers described with reference to “overlap” in a particular direction may be at least partially obstructed by one another when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction. The passive element may include, e.g., a capacitor, an inductor, a resistor, etc. Hereinafter, the capacitor 850 as the passive element is described.
In example embodiments, a lower portion of the capacitor 850 may extend through a portion of the first semiconductor chip 100 adjacent to the second surface 114, and an upper portion of the capacitor 850 may protrude upwardly over the second surface 114 to be covered by the first protective pattern structure 160.
In example embodiments, the capacitor 850 may include a lower electrode 820, a dielectric pattern 830 and an upper electrode 840 sequentially stacked in the vertical direction, and a lower surface of the lower electrode 820 may be covered by a pad 810. In an example embodiment, the pad 810, the lower electrode 820 and the dielectric pattern 830 may be conformally stacked on an inner wall of a trench 115, which may be disposed on a portion of the first semiconductor chip 100 adjacent to the second surface 114, and the second surface 114 of the first semiconductor chip 100, and the upper electrode 840 may be disposed on the dielectric pattern 830 to fill a remaining portion of the trench 115.
In example embodiments, a portion of an upper surface of the lower electrode 820 may not be covered by the dielectric pattern 830 and the upper electrode 840, but may be at least partially exposed thereby. The term “exposed” may be used to describe relationships between elements and/or certain intermediate processes in fabricating a completed semiconductor device, but may not necessarily require exposure of the particular region, layer, structure or other element in the context of the completed device.
The pad 810 may include an oxide, e.g., silicon oxide, each of the lower and upper electrodes 820 and 840 may include, e.g., a metal, a metal nitride, a metal silicide, doped polysilicon, and the dielectric pattern 830 may include a metal oxide having a high dielectric constant, e.g., hafnium oxide, zirconium oxide, etc.
The first RDL 860 may be disposed on the first protective pattern structure 160 and the first through electrode structure 120, and the redistribution wiring structure 880 may be disposed on the first RDL 860. The redistribution wiring structure 880 may include first to third redistribution wirings 882, 884 and 886.
In example embodiments, a via structure 870 may extend through the first protective pattern structure 160 and the first RDL 860. The via structure 870 may include first to third vias 872, 874 and 876.
The first via 872 may contact an upper surface of the lower electrode 820 of the capacitor 850 and a lower surface of the first redistribution wiring 882 of the redistribution wiring structure 880, the second via 874 may contact an upper surface of the upper electrode 840 of the capacitor 850 and a lower surface of the second redistribution wiring 884 of the redistribution wiring structure 880, and the third via 876 may contact an upper surface of the first through electrode structure 120 and a lower surface of the third redistribution wiring 886 of the redistribution wiring structure 880.
In example embodiments, a plurality of third vias 876 may be spaced apart from each other in the horizontal direction, which may correspond to the plurality of first through electrode structures 120 spaced apart from each other in the horizontal direction. Some of the plurality of third vias 876 may contact the upper surface of the first through electrode structure 120 and the lower surface of the first redistribution wiring 882 of the redistribution wiring structure 880.
That is, the first redistribution wiring 882 may commonly contact upper surfaces of the first and third vias 872 and 876, the second redistribution wiring 884 may contact an upper surface of the second via 874, and the third redistribution wiring 886 may contact an upper surface of the third via 876. Thus, the lower electrode 820 of the capacitor 850 may be electrically connected to the first through electrode structure 120 by the first via 872, the first redistribution wiring 882 and the third via 876, and the upper electrode 840 of the capacitor 850 may be electrically connected to the second redistribution wiring 884 by the second via 874.
However, the inventive concept may not be limited thereto, and in some embodiments, the upper electrode 840 of the capacitor 850 may be electrically connected to the first through electrode structure 120 by the first via 872, the first redistribution wiring 882 and the third via 876, and the lower electrode 820 of the capacitor 850 may be electrically connected to the second redistribution wiring 884 by the second via 874.
Some of the first and second redistribution wirings 882 and 884 included in the redistribution wiring structure 880 and the third redistribution wiring 886 may serve as a second conductive pad.
In an example embodiment, the first RDL 860 may include an organic insulating material. Alternatively, the first RDL 860 may include an inorganic insulating material, e.g., silicon oxide, silicon nitride, etc.
Each of the first to third vias 872, 874 and 876 and the first to third redistribution wirings 882, 884 and 886 may include a conductive material, e.g., a metal, a metal nitride, a metal silicide, etc.
Each of the second semiconductor chips 200 may include a second substrate 210 having first and second surfaces 212 and 214 opposite to each other in the vertical direction, a second through electrode structure 220 extending through the second substrate 210, a third insulating interlayer and a fourth insulating interlayer 230 sequentially stacked in the vertical direction beneath the first surface 212 of the second substrate 210, a third conductive pad 240 beneath the fourth insulating interlayer 230, a second protective pattern structure 260 on the second surface 214 of the second substrate 210, and a fourth conductive pad 270 on the second protective pattern structure 260 and contacting an upper surface of the second through electrode structure 220.
The second substrate 210 may include a semiconductor material, e.g., silicon, germanium, silicon-germanium, or a III-V group compound semiconductor, e.g., GaP, GaAs, GaSb, etc. In example embodiments, the second substrate 210 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.
A circuit device, e.g., a volatile memory device such as DRAM device, SRAM device, etc., or a non-volatile memory device such as flash memory device, EEPROM device, etc., may be disposed on or beneath the first surface 212 of the second substrate 210. The circuit device may include circuit patterns, which may be covered by the third insulating interlayer.
The fourth insulating interlayer 230 may contain a second wiring structure therein. The second wiring structure may include, e.g., wirings, vias, contact plugs, etc.
The third insulating interlayer and the fourth insulating interlayer 230 may include, e.g., silicon oxide or a low-k dielectric material, e.g., an oxide doped with carbon or fluorine. The wirings, the vias, the contact plugs, etc., may include a conductive material, e.g., a metal, a metal nitride, a metal silicide, etc.
The third conductive pad 240 may be disposed under the fourth insulating interlayer 230, and may contact the second wiring structure to be electrically connected thereto. In example embodiments, a plurality of third conductive pads 240 may be spaced apart from each other in the horizontal direction.
In example embodiments, the third conductive pad 240 may include a second seed pattern and a second conductive patterns sequentially stacked downwardly in the vertical direction from the fourth insulating interlayer 230. The second seed pattern may include, e.g., titanium, and the second conductive pattern may include, e.g., nickel and gold.
The second through electrode structure 220 may extend through the second substrate 210 in the vertical direction. A protrusion portion of the second through electrode structure 220 may protrude upwardly in the vertical direction (i.e., beyond the second surface 214 of the second substrate 210), and may be covered by the second protective pattern structure 260. A plurality of second through electrode structures 220 may be spaced apart from each other in the horizontal direction. In example embodiments, the second through electrode structure 220 may include a second through electrode extending in the vertical direction, a second barrier pattern covering a sidewall of the second through electrode, and a second insulation pattern covering an outer sidewall of the second barrier pattern.
The second through electrode may include a metal, e.g., copper, aluminum, etc., the second barrier pattern may include a metal nitride, e.g., titanium nitride, tantalum nitride, etc., and the second insulation pattern may include an oxide, e.g., silicon oxide or an insulating nitride, e.g., silicon nitride.
In an example embodiment, the second through electrode structure 220 may extend through the second protective pattern structure 260, the second substrate 210 and the third insulating interlayer to contact the second wiring structure, and may be electrically connected to the third conductive pad 240 by the second wiring structure.
Alternatively, the second through electrode structure 220 may extend through the second protective pattern structure 260, the second substrate 210 and the third insulating interlayer and the fourth insulating interlayer 230 to contact the third conductive pad 240, and may be electrically connected thereto. Alternatively, the second through electrode structure 220 may extend through the second protective pattern structure 260 and the second substrate 210 to contact one of the circuit patterns included in the circuit device covered by the third insulating interlayer, and may be electrically connected to the third conductive pad 240 by one of the circuit patterns and the second wiring structure.
The second protective pattern structure 260 may be disposed on the second surface 214 of the second substrate 210, and may surround an upper portion of the second through electrode structure 220. In example embodiments, the second protective pattern structure 260 may include a third protective pattern and a fourth protective pattern sequentially stacked in the vertical direction on the second surface 214 of the second substrate 210. A portion of the third protective pattern adjacent to the second through electrode structure 220 may protrude upwardly in the vertical direction, and an upper surface of the portion of the second protective pattern structure 260 may be substantially coplanar with an upper surface of the second through electrode structure 220. An outer sidewall of the portion of the third protective pattern may be covered by the fourth protective pattern.
The third protective pattern may include an oxide, e.g., silicon oxide, and the fourth protective pattern may include an insulating nitride, e.g., silicon nitride.
The fourth conductive pad 270 may be electrically connected to the third conductive pad 240 by the second through electrode structure 220 and the second wiring structure. In example embodiments, a plurality of fourth conductive pads 270 may be spaced apart from each other in the horizontal direction.
In example embodiments, the fourth conductive pad 270 may include a third seed pattern and a third conductive pattern sequentially stacked upwardly in the vertical direction from the second protective pattern structure 260. The third seed pattern may include, e.g., titanium, and the third conductive pattern may include, e.g., nickel, copper, gold, etc.
In example embodiments, the second conductive connection member 250 included in a lowermost one of the second semiconductor chips 200 may contact a lower surface of the third conductive pad 240 and an upper surface of the second conductive pad included in the redistribution wiring structure 880, and the second conductive connection member 250 included in other ones of the second semiconductor chips 200 may contact lower and upper surfaces of the third and fourth conductive pads 240 and 270, respectively.
The second conductive connection member 250 may be, e.g., a conductive bump. The second conductive connection member 250 may include a metal, e.g., tin, or solder.
The adhesion layer 700 be disposed between the second semiconductor chip 200 and the first RDL 860 and the redistribution wiring structure 880, and may bond the second semiconductor chip 200 and the first RDL 860 and the redistribution wiring structure 880 with each other. The adhesion layer 700 may surround a structure including the second conductive pad, the third conductive pad 240 and the second conductive connection member 250, or a structure including the third and fourth conductive pads 240 and 270 and the second conductive connection member 250. The adhesion layer 700 may include a non-conductive film (NCF), e.g., thermosetting resin.
The third semiconductor chip 300 may be stacked on the second semiconductor chip 200, and the adhesion layer 700 may be disposed therebetween.
The third semiconductor chip may have a structure substantially the same as or similar to that of the second semiconductor chip 200, and thus repeated explanations of common or similar elements are omitted herein.
The third semiconductor chip 300 may include a third substrate 310 having first and second surfaces 312 and 314 opposite to each other in the vertical direction, a fifth insulating interlayer and a sixth insulating interlayer 330 sequentially stacked in the vertical direction beneath the first surface 312 of the third substrate 310, a fifth conductive pad 340 beneath the sixth insulating interlayer 330 and a third conductive connection member 350.
A circuit device, e.g., a memory device may be disposed on or beneath the first surface 312 of the third substrate 310. The circuit device may include circuit patterns, which may be covered by the fifth insulating interlayer. The sixth insulating interlayer 330 may contain a third wiring structure therein.
The fifth conductive pad 340 may be disposed under the sixth insulating interlayer 330, and may contact the third wiring structure to be electrically connected thereto. In example embodiments, a plurality of fifth conductive pads 340 may be spaced apart from each other in the horizontal direction.
In example embodiments, the fifth conductive pad 340 may include a fourth seed pattern and a fourth conductive pattern sequentially stacked downwardly in the vertical direction from the sixth insulating interlayer 330. The fourth seed pattern may include, e.g., titanium, and the fourth conductive pattern may include, e.g., nickel, copper, gold, etc.
The third conductive connection member 350 contact upper and lower surfaces of the fourth and fifth conductive pads 270 and 340, respectively.
The adhesion layer 700 may be disposed between an uppermost one of the second semiconductor chips 200 and the third semiconductor chip 300, and may bond the uppermost one of the second semiconductor chips 200 and the third semiconductor chip 300 with each other. The adhesion layer 700 may surround the fourth and fifth conductive pads 270 and 340 and the third conductive connection member 350.
The molding member 600 may cover sidewalls of the second and third semiconductor chips 200 and 300 on the first RDL 860 and the redistribution wiring structure 880, and an upper surface of the molding member 600 may be substantially coplanar with an upper surface of the third semiconductor chip 300. The molding member 600 may include a polymer, e.g., epoxy molding compound (EMC).
In the semiconductor package, one or more passive elements such as the capacitor 850 may be disposed at a portion of the first semiconductor chip 100 adjacent to the second surface 114 of the first substrate 110, and may not overlap the second and third semiconductor chips 200 and 300 in the vertical direction.
That is, for example, if the first through electrode structures 120, which may be disposed in the first substrate 110 of the first semiconductor chip 100 and transfer electrical signals to the second and third semiconductor chips 200 and 300, are disposed by a small pitch, space for a passive element may be insufficient.
However, in example embodiments, a passive element may be disposed at an edge portion of the first semiconductor chip 100, that is, a portion of the first semiconductor chip 100 that does not overlap (in the vertical direction) with the second and third semiconductor chips 200 and 300 stacked on the first semiconductor chip 100, and the first through electrode structures 120 for transferring electrical signals to the second and third semiconductor chips 200 and 300 are not disposed at the non-overlapping portion so that sufficient space for the passive elements may be provided.
Accordingly, the semiconductor package may include passive elements without an increase in size or otherwise without requiring additional space for the passive elements, and thus the electrical characteristics of the semiconductor package may be enhanced.
The passive elements may be electrically connected to the first through electrode structure 120 by the redistribution wiring structure 880 and the via structure 870 on the first semiconductor chip 100.
Referring to
In example embodiments, the first wafer W1 may include a first substrate 110 having first and second surfaces 112 and 114 opposite to each other in the vertical direction. Additionally, the first wafer W1 may include a plurality of die regions DA and a scribe lane region SA surrounding each of the die regions DA. The first wafer W1 may be cut along the scribe lane region SA by a sawing process to be singulated into a plurality of first semiconductor chips.
In the die region DA, a circuit device may be formed on the first surface 112 of the first substrate 110. The circuit device may include a logic device. The circuit device may include circuit patterns, and a first insulating interlayer may be formed on the first surface 112 of the first substrate 110 to cover the circuit patterns.
A second insulating interlayer 130 may be formed on the first insulating interlayer, and may contain a first wiring structure therein. The first wiring structure may include, e.g., wirings, vias, contact plugs, etc.
A first conductive pad 140 may be formed on second insulating interlayer 130 to contact the first wiring structure to be electrically connected thereto. In example embodiments, a plurality of first conductive pads 140 may be spaced apart from each other in the horizontal direction.
In an example embodiment, the first conductive pad 140 may be formed by following processes.
A first seed layer may be formed on the second insulating interlayer 130, a first photoresist pattern including a first opening partially exposing an upper surface of the first seed layer may be formed on the first seed layer, and an electroplating process or an electroless plating process may be performed to form a first conductive pattern in the first opening.
The first photoresist pattern may be removed by, e.g., an ashing process and/or a stripping process to expose a portion of the first seed layer, the exposed portion of the first seed layer may be removed to form a first seed pattern.
Thus, a first conductive pad 140 including the first seed pattern and the first conductive pattern sequentially stacked in the vertical direction may be formed.
A first conductive connection member 150 may be formed on the first conductive pad 140.
In an example embodiment, the first conductive connection member 150 may be formed by following processes.
A second photoresist pattern including a second opening exposing an upper surface of the first conductive pad 140 may be formed on the second insulating interlayer 130, and an electroplating process or an electroless plating process may be performed to form a preliminary first conductive connection member in the second opening. After removing the second photoresist pattern, a reflow process may be performed so that the preliminary first conductive connection member may be transformed into a first conductive connection member 150.
In example embodiments, the first conductive connection member 150 may have a shape of, e.g., a semi-circle or a semi-ellipse.
In example embodiments, a first through electrode structure 120 extending in the vertical direction through an upper portion of the first substrate 110, that is, a portion of the first substrate 110 adjacent to the first surface 112 thereof may be formed. In example embodiments, a plurality of first through electrode structures 120 may be spaced apart from each other in the horizontal direction.
In an example embodiment, the first through electrode structure 120 may include a first through electrode extending in the vertical direction, a first barrier pattern covering a sidewall and a lower surface of the first through electrode, and a first insulation pattern covering a sidewall and a lower surface of the first barrier pattern.
Referring to
The first temporary adhesion layer 910 may include a material that is configured to lose adhesion by or responsive to irradiation of light, e.g., UV light or heat. In an example embodiment, the first temporary adhesion layer 910 may include glue.
After flipping the first wafer W1, a portion of the first substrate 110 adjacent to the second surface 114 of the first substrate 110 may be removed by, e.g., a grinding process to expose an upper portion of the first through electrode structure 120.
A first protective layer structure may be formed on the second surface 114 of the first substrate 110 to cover the first through electrode structure 120, and a planarization process may be performed on the first protective layer structure until an upper surface of the first through electrode of the first through electrode structure 120 is exposed to form a first protective pattern structure 160.
In example embodiments, the planarization process may include a chemical mechanical polishing (CMP) process and/or an etch back process.
In example embodiments, the first protective layer structure may include first to third protective layers sequentially stacked in the vertical direction, and during the planarization process, the third protective layer may be removed and the second protective layer may partially remain. Thus, the first protective pattern structure 160 may include first and second protective patterns sequentially stacked in the vertical direction. An upper outer sidewall of a portion of the first protective pattern adjacent to the first through electrode structure 120 may be covered by the second protective pattern.
Referring to
In example embodiments, the third opening 165 and the trench 115 may be formed at a portion of the die region DA adjacent to the scribe lane region SA of the first wafer W1.
A pad layer and a lower electrode layer may be conformally stacked on inner walls of the trench 115 and the third opening 165, an upper surface of the first protective pattern structure 160 and an upper surface of the first through electrode structure 120, and may be patterned to form a pad 810 and a lower electrode 820, respectively. In example embodiments, the pad 810 and the lower electrode 820 may be formed on the inner wall of the trench 115 and a bottom of the third opening 165.
Referring to
In example embodiments, the upper electrode 840 and the dielectric pattern 830 may be formed in the trench 115 and the third opening 165, and may partially expose a portion of the upper surface of the lower electrode 820.
The lower electrode 820, the dielectric pattern 830 and the upper electrode 840 sequentially stacked may collectively form a capacitor 850.
Referring to
In example embodiments, the filling pattern may include a material substantially the same as that of the first protective pattern structure 160, particularly, the second protective pattern, and thus may be merged with the second protective pattern.
A first RDL 860 may be formed on the first protective pattern structure 160 and the first through electrode structure 120, and may be partially removed to form fourth to sixth openings exposing upper surfaces of the capacitor 850 and the first through electrode structure 120.
Particularly, the fourth opening may expose an upper surface of the lower electrode 820 of the capacitor 850, the fifth opening may expose an upper surface of the upper electrode 840 of the capacitor 850, and the sixth opening may expose an upper surface of the first through electrode structure 120.
A via layer may be formed on the first RDL 860 to fill the fourth to sixth openings, and a planarization process may be performed on the via layer until an upper surface of the via layer is exposed to form first to third vias 872, 874 and 876 in the fourth to sixth openings, respectively, which may collectively form a via structure 870.
Referring to
In example embodiments, the redistribution wiring structure 880 may include first to third wirings 882, 884 and 886. The first redistribution wiring 882 may commonly contact upper surfaces of the first and third vias 872 and 876, the first redistribution wiring 884 may contact an upper surface of the second via 874, and the third redistribution wiring 886 may contact an upper surface of the third via 876.
A portion of each of the first and second redistribution wirings 882 and 884 included in the redistribution wiring structure 880 may serve as a second conductive pad.
Referring to
In example embodiments, the second wafer W2 may include a second substrate 210 having first and second surfaces 212 and 214 opposite to each other in the vertical direction. Additionally, the second wafer W2 may include a plurality of die regions DA and a scribe lane region SA surrounding each of the die regions DA. The second wafer W2 may be cut along the scribe lane region SA by a sawing process to be singulated into a plurality of second semiconductor chips.
In the die region DA, a circuit device may be formed on the first surface 212 of the second substrate 210. The circuit device may include a memory device. The circuit device may include circuit patterns, and a third insulating interlayer may be formed on the first surface 212 of the second substrate 210 to cover the circuit patterns.
A fourth insulating interlayer 230 may be formed on the third insulating interlayer, and may contain a second wiring structure therein. The second wiring structure may include, e.g., wirings, vias, contact plugs, etc.
A third conductive pad 240 may be formed on fourth insulating interlayer 230 to contact the second wiring structure to be electrically connected thereto. In example embodiments, a plurality of third conductive pads 240 may be spaced apart from each other in the horizontal direction.
In an example embodiment, the third conductive pad 240 may be formed by processes substantially the same as or similar to those of the first conductive pad 140. Thus, the third conductive pad 240 may be formed to include a second seed pattern and a second conductive pattern sequentially stacked in the vertical direction.
A second conductive connection member 250 may be formed on the third conductive pad 240. In an example embodiment, the second conductive connection member 250 may be formed by processes substantially the same as or similar to those of the first conductive connection member 150. Thus, the second conductive connection member 250 may have a shape of, e.g., a semi-circle or a semi-ellipse.
In example embodiments, a second through electrode structure 220 extending through the second substrate 210 in the vertical direction may be formed. In example embodiments, a plurality of second through electrode structures 220 may be spaced apart from each other in the horizontal direction.
In an example embodiment, the second through electrode structure 220 may include a second through electrode extending in the vertical direction, a second barrier pattern covering a sidewall and a lower surface of the second through electrode, and a second insulation pattern covering a sidewall and a lower surface of the second barrier pattern.
Referring to
Particularly, a second temporary adhesion layer 920 may be attached to a second carrier substrate C2, and the second temporary adhesion layer 920 may be bonded with an upper surface of the fourth insulating interlayer 230 including the second wiring structure to cover the second conductive connection member 250 and the third conductive pad 240 on the second wafer W2 so that the second carrier substrate C2 may be bonded with the second wafer W2. The second temporary adhesion layer 920 may include a material that is configured to lose adhesion by or responsive to irradiation of light, e.g., UV light or heat. In an example embodiment, the second temporary adhesion layer 920 may include glue.
After flipping the second wafer W2, a portion of the second substrate 210 adjacent to the second surface 214 of the second substrate 210 may be removed by, e.g., a grinding process to expose an upper portion of the second through electrode structure 220. A second protective layer structure may be formed on the second surface 214 of the second substrate 210 to cover the second through electrode structure 220, and a planarization process may be performed on the second protective layer structure until an upper surface of the second through electrode of the second through electrode structure 220 is exposed to form a second protective pattern structure 260. In example embodiments, the second protective pattern structure 260 may include third and fourth protective patterns sequentially stacked in the vertical direction.
A fourth conductive pad 270 may be formed on the second protective pattern structure 260 and the second through electrode structure 220. The fourth conductive pad 270 may include a third seed pattern and a third conductive pattern sequentially stacked in the vertical direction.
Referring to
The release tape may contact upper surfaces of the fourth conductive pad 270 and the second filling pattern structure 260 on the second surface 214 of the second wafer W2.
The second temporary adhesion layer 920 attached to the second carrier substrate C2 may be separated from the second conductive connection member 250, the third conductive pad 240 and the fourth insulating interlayer 230 so that the second carrier substrate C2 may be separated from the second wafer W2.
After cutting the second wafer W2 along the scribe lane region SA by a sawing process into second semiconductor chips 200, an adhesion layer 700 may be formed on the fourth insulating interlayer 230 of each of the second semiconductor chips 200.
The adhesion layer 700 may be formed on the fourth insulating interlayer 230 to cover the third conductive pad 240 and the second conductive connection member 250. The adhesion layer 700 may include a NCF, e.g., thermosetting resin.
In some embodiments, the adhesion layer 700 may be formed on the fourth insulating interlayer 230 of the second wafer W2, before the sawing process.
Each of the second semiconductor chips 200 may be separated from the release tape, and the adhesion layer 700 on each of the second semiconductor chips 200 may be attached to upper surfaces of the redistribution wiring structure 880 and the first RDL 860 so that each of the second semiconductor chips 200 may be mounted onto the first wafer W1. The second semiconductor chips 200 may be disposed on the respective die regions DA of the first wafer W1, and the second conductive connection member 250 of the second semiconductor chip 200 may contact the upper surface of the second conductive pad of the redistribution wiring structure 880.
In example embodiments, each of the second semiconductor chips 200 may not overlap the capacitor 850 on the first wafer W1.
A thermal compression bonding (TCB) process may be performed at a temperature equal to or less than about 400° C. so that the second semiconductor chips 200 may be bonded to the first wafer W1.
During the thermal compression process, the NCF included in the adhesion layer 700 may be melted to have fluidity, may flow into a space between each of the second semiconductor chips 200 and the first wafer W1 to cover sidewalls of the second conductive pad, the second conductive connection member 250 and the third conductive pad 240, and may be cured.
Referring to
The third semiconductor chip 300 may be stacked on the uppermost one of the second semiconductor chips 200 by following processes.
Particularly, a third wafer may be provided. In example embodiments, the third wafer may include a third substrate 310 having first and second surfaces 312 and 314 opposite to each other in the vertical direction. Additionally, the third wafer may include a plurality of die regions and a scribe lane region surrounding each of the die regions. The third wafer may be cut along the scribe lane region by a sawing process to be singulated into a plurality of third semiconductor chips.
In the die region, a circuit device may be formed on the first surface 312 of the third substrate 310. The circuit device may include a memory device. The circuit device may include circuit patterns, and a fifth insulating interlayer may be formed on the first surface 312 of the third substrate 310 to cover the circuit patterns.
A sixth insulating interlayer 330 may be formed on the fifth insulating interlayer, and may contain a third wiring structure therein. The third wiring structure may include, e.g., wirings, vias, contact plugs, etc.
A fifth conductive pad 340 may be formed on sixth insulating interlayer 330 to contact the third wiring structure to be electrically connected thereto. In example embodiments, a plurality of fifth conductive pads 340 may be spaced apart from each other in the horizontal direction.
In an example embodiment, the fifth conductive pad 340 may be formed by processes substantially the same as or similar to those of the third conductive pad 240. Thus, the fifth conductive pad 340 may be formed to include a fourth seed pattern and a fourth conductive pattern sequentially stacked in the vertical direction.
A third conductive connection member 350 may be formed on the fifth conductive pad 340. In an example embodiment, the third conductive connection member 350 may be formed by processes substantially the same as or similar to those of the second conductive connection member 250. Thus, the third conductive connection member 350 may have a shape of, e.g., a semi-circle or a semi-ellipse.
A third temporary adhesion layer may be attached to a third carrier substrate, and the third temporary adhesion layer may be bonded with an upper surface of the sixth insulating interlayer 330 including the third wiring structure to cover the third conductive connection member 350 and the fifth conductive pad 340 on the third wafer so that the third carrier substrate may be bonded with the third wafer. The third temporary adhesion layer may include a material that is configured to lose adhesion by or responsive to irradiation of light, e.g., UV light or heat. In an example embodiment, the third temporary adhesion layer may include glue.
After flipping the third wafer, the third wafer may be attached to an upper surface of a release tape on a frame having a shape of, e.g., a ring. The third temporary adhesion layer attached to the third carrier substrate may be separated from the third conductive connection member 350, the fifth conductive pad 340 and the sixth insulating interlayer 330 so that the third carrier substrate may be separated from the third wafer.
After cutting the third wafer along the scribe lane region by a sawing process into third semiconductor chips 300, the adhesion layer 700 may be formed on the sixth insulating interlayer 330 of each of the third semiconductor chips 300. The adhesion layer 700 may cover the fifth conductive pad 340 and the third conductive connection member 350.
In some embodiments, the adhesion layer 700 may be formed on the sixth insulating interlayer 330 of the third wafer, before the sawing process.
Each of the third semiconductor chips 300 may be separated from the release tape, and the adhesion layer 700 on each of the third semiconductor chips 300 may be attached to upper surfaces of the fourth conductive pad 270 and the second protective pattern structure 260 of the second semiconductor chip 200 so that each of the third semiconductor chips 300 may be mounted onto the second semiconductor chip 200. The third conductive connection member 350 of the third semiconductor chip 300 may contact the upper surface of the fourth conductive pad 270 of the second semiconductor chip 200.
In example embodiments, each of the third semiconductor chips 300 may not overlap the capacitor 850 on the first wafer W1.
A TCB process may be performed so that each of the third semiconductor chips 200 may be bonded to the second semiconductor chip 200.
Referring to
In example embodiments, the molding member 600 may expose an upper surface of the third semiconductor chip 300.
The first wafer W1 may be cut along the scribe lane region SA by, e.g., a sawing process to be singulated into a plurality of first semiconductor chips 100.
During the sawing process, the molding member 600 may also be cut to cover sidewalls of the second and third semiconductor chips 200 and 300 on each of the first semiconductor chips 100.
The first temporary adhesion layer 910 and the first carrier substrate C1 may be separated from each of the first semiconductor chips 100 to complete manufacturing the semiconductor package.
Referring to
Particularly, the first and second semiconductor chips 100 and 200 may be bonded with each other by an HCB process. Thus, a second RDL 865 covering a sidewall of the redistribution wiring structure 880 may be formed on the first RDL 860, and a first bonding layer 180 containing a first bonding pattern 185 therein may be formed on the redistribution wiring structure 880 and the second RDL 865. Additionally, a second bonding layer 280 containing a second bonding pattern 285 therein may be formed beneath the fourth insulating interlayer 230 of the second semiconductor chip 200, instead of the third conductive pad 240 and the second conductive connection member 250. Thus, the first and second bonding layers 180 and 280 may be bonded with each other to form a first bonding layer structure, and the first and second bonding patterns 185 and 285 may be bonded with each other to form a first bonding pattern structure.
Additionally, the second semiconductor chips 200 may be bonded with each other by an HCB process. Thus, a third bonding layer 290 containing a third bonding pattern 295 therein may be formed on the second protective pattern structure 260 and the second through electrode structure 220 of the second semiconductor chip 200, instead of the fourth conductive pad 270. The third bonding layer 290 of one of the second semiconductor chips 200 disposed at a lower level may be bonded with the second bonding layer 280 of one of the second semiconductor chips 200 disposed at an upper level to form a second bonding layer structure, and the second and third bonding patterns 285 and 295 may form a second bonding pattern structure.
Furthermore, the second and third semiconductor chips 200 and 300 may be bonded with each other by an HCB process. Thus, a fourth bonding layer 380 containing a fourth bonding pattern 385 therein may be formed beneath the sixth insulating interlayer 330 of the third semiconductor chip 300, instead of the fifth conductive pad 340 and the third conductive connection member 350. The fourth bonding layer 380 of the third semiconductor chip 300 may be bonded with the third bonding layer 290 of the second semiconductor chip 200 to form a third bonding layer structure, and the third and fourth bonding patterns 295 and 385 may be bonded with each other to form a third bonding pattern structure.
However, in some embodiments, some of the first and second semiconductor chips 100 and 200, the semiconductor chips 200, and the second and third semiconductor chips 200 and 300 may be bonded with each other by a TCB process, and others may be bonded with each other by an HCB process.
In example embodiments, each of the first to fourth bonding layers 180, 280, 290 and 380 may include, e.g., silicon carbonitride, silicon oxide, and each of the first to fourth bonding patterns 185, 285, 295 and 385 may include a metal, e.g., copper.
This electronic device may include the semiconductor package shown in
Referring to
In example embodiments, the electronic device 10 may be a memory module having a 2.5D package structure, and thus may include the interposer 30 for electrically connecting the first and second semiconductor devices 40 and 50 to each other.
In example embodiments, the first semiconductor device 40 may include a logic device, and the second semiconductor device 50 may include a memory device. The logic device may be an application-specific integrated circuit (ASIC) chip including, e.g., a central processing unit (CPU), a graphics processing unit (GPU), a micro-processor, a micro-controller, an application processor (AP), a digital signal processing core, etc. The memory device may include a semiconductor package, e.g., the HBM package of
In example embodiments, the package substrate 20 may have an upper surface and a lower surface opposite to each other in the vertical direction. For example, the package substrate 20 may be a printed circuit board (PCB). The printed circuit board may be a multi-layer circuit board having various circuits therein.
The interposer 30 may be mounted on the package substrate 20 through a fifth conductive connection member 32. In example embodiments, a planar area of the interposer 30 may be smaller than a planar area of the package substrate 20. The interposer 30 may be disposed within an area of the package substrate 20 in a plan view.
The interposer 30 may be a silicon interposer or a redistribution interposer having a plurality of wirings therein. The first semiconductor device 40 and the second semiconductor device 50 may be connected to each other through the wirings in the interposer 30 or electrically connected to the package substrate 20 through the fifth conductive connection member 32. The fifth conductive connection member 32 may include, e.g., a micro-bump. The silicon interposer may provide a high-density interconnection between the first and second semiconductor devices 40 and 50.
The first semiconductor device 40 may be disposed on the interposer 30. The first semiconductor device 40 may be mounted on and bonded with the interposer 30 by a flip chip bonding process. In this case, the first semiconductor device 40 may be mounted on the interposer 30 such that an active surface on which conductive pads are formed may face downwardly toward the interposer 30. The conductive pads of the first semiconductor device 40 may be electrically connected to conductive pads of the interposer 30 through a sixth conductive connection member 42. For example, the sixth conductive connection member 42 may include, e.g., a micro-bump.
Alternatively, the first semiconductor device 40 may be mounted on the interposer 30 by a wire bonding process, and in this case, the active surface of the first semiconductor device 40 may face upwardly.
The second semiconductor device 50 may be disposed on the interposer 30, and may be spaced apart from the first semiconductor device 40 in the horizontal direction. The second semiconductor device 50 may be mounted on and bonded with the interposer 30 by, e.g., a flip chip bonding process. In this case, conductive pads of the second semiconductor device 50 may be electrically connected to conductive pads of the interposer 30 by the first conductive connection member 150.
Although a single first semiconductor device 40 and a single second semiconductor device 50 are illustrated on the interposer 30, the inventive concept may not be limited thereto, and a plurality of first semiconductor devices 40 and/or a plurality of second semiconductor devices 50 may be disposed on the interposer 30.
In example embodiments, the first underfill member 34 may fill a space between the interposer 30 and the package substrate 20, and the second and third underfill members 44 and 54 may fill a space between the first semiconductor device 40 and the interposer 30 and a space between the second semiconductor device 50 and the interposer 30, respectively.
The first to third underfill members 34, 44 and 54 may include a material having a relatively high fluidity to effectively fill a small space between the first and second semiconductor devices 40 and 50 and the interposer 30 and a small space between the interposer 30 and the package substrate 20. For example, each of the first and second underfill members 34, 44 and 54 may include an adhesive containing an epoxy material.
The semiconductor device 50 may include a buffer die and a plurality of memory dies sequentially stacked on the buffer die. The buffer die and the memory dies may be electrically connected to each other by through electrodes, e.g., TSVs, and the through electrodes may be electrically connected to each other by conductive connection members. Data signals and control signals may be transferred to the buffer die and the memory dies by the through electrodes.
In example embodiments, the heat slug 60 be formed on the package substrate 20 to thermally contact the first and second semiconductor devices 40 and 50. The heat dissipation member 62 may be disposed on an upper surface of each of the first and second semiconductor devices 40 and 50, and may include, e.g., thermal interface material (TIM). The heat slug 60 may thermally contact the first and second semiconductor devices 40 and 50 via the heat dissipation member 62.
A conductive pad may be formed at a lower portion of the package substrate 20, and a fourth conductive connection member 22 may be disposed beneath the conductive pad. In example embodiments, a plurality of fourth conductive connection members 22 may be spaced apart from each other in the horizontal direction. The fourth conductive connection member 22 may be, e.g., a solder ball. The electronic device 10 may be mounted on a module board via the fourth conductive connection members 22 to form a memory module.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of example embodiments as defined in the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2024-0003612 | Jan 2024 | KR | national |
