SEMICONDUCTOR PATTERN AND METHOD OF ROUNDING THE SAME

Abstract

A semiconductor pattern is provided in the present invention, including a first line extending to one end in a first direction and a second line extending in a second direction perpendicular to the first direction and adjacent to the end of the first line in the first direction, wherein the end of the first line is provided with a rounding feature, the first line has a width in the second direction, and the width is gradually increased to a maximum width toward the end and gradually converged to form the rounding feature.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor pattern, and more specifically, to a semiconductor pattern with rounding feature and method of rounding the same.

2. Description of the Prior Art

Embedded high voltage (eHV) technology uses CMOS-based logic process to manufacture high-voltage driver ICs required by various monitors, which plays an important part in the manufacture of display panel like LCD, OLED, or emerging micro-LED and micro-OLED, etc. In comparison to ordinary logic device, eHV device requires higher driving voltage (between 5V and 27V), whose tolerance voltage applied in time-dependent dielectric breakdown (TDDB) test may reach up to ten times of the one of ordinary logic device. In addition, pointed features in semiconductor pattern usually have larger charge density since their smaller radius of curvature, so that the electric field induced at these pointed features is quite high, which may reach up to one hundred times of the one in ordinary logic device. This extremely high electric field tends to burn-out the dielectrics near the pointed features, which impacts the reliability of device.

SUMMARY OF THE INVENTION

In the light of aforementioned issues encountered in technology of current embedded high-voltage (eHV) device, the present invention hereby provides a novel semiconductor pattern and method of rounding the same, with feature of forming a rounding feature at the pointed end of semiconductor pattern with a width larger than the original width of line pattern, so as to lower the electric field at the end to avoid the issues of dielectrics burn-out and device reliability.

One aspect of present invention is to provide a semiconductor pattern, including a first line extending to one end in a first direction, and a second line extending in a second direction perpendicular to the first direction and adjacent to the end of the first line, wherein the end of the first line is provided with a rounding feature, the first line has a width in the second direction, and the width gradually increases to a maximum width toward the end and then gradually decreases and converges to form the rounding feature at the end.

Another aspect of the present invention is to provide a method of rounding semiconductor pattern, including steps of providing a semiconductor pattern having a first line and a second line, wherein the first line extends in a first direction to one end, and the second line extends in a second direction perpendicular to the first direction and adjacent to the end of the first line in the first direction, and using optical proximity correction (OPC) tool to perform a rounding action to the end of the first line so as to form a rounding feature at the end, wherein the first line has a width in the second direction, and the width gradually increases to a maximum width toward the end and then gradually decreases and converges to form the rounding feature at the end.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

FIG. 1 is a layout of a semiconductor pattern in accordance with the embodiment of present invention; and

FIG. 2 is an enlarged schematic view of a semiconductor pattern in accordance with the embodiment of present invention.

Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

In the following detailed description of the present invention, reference is made to the accompanying drawings which form a part hereof and is shown by way of illustration and specific embodiments in which the invention may be practiced. These embodiments are described in sufficient details to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. Additionally, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of other factors not necessarily expressly described, again depending at least in part on the context.

It will be further understood that the terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Please refer to FIG. 1, which is a layout of a semiconductor pattern in accordance with the embodiment of present invention. The semiconductor pattern of present invention generally includes a first line L1 extending in a first direction D1 to one end 10 and a second line L2 extending in a second direction D2 perpendicular to the first direction D1. The second line L2 is adjacent to the end 10 of first line L1 in the first direction D1, and the two lines are separated by a first spacing S1 in the first direction D1.

The semiconductor pattern of present invention may further include third lines L3 at two sides of the first line L1 in the second direction D2. The third line L3 extends in the first direction D1 to connect with the second line L2. In the embodiment of present invention, multiple third lines L3 and multiple first lines L1 may be parallel to each other and alternately arranged in the second direction D2, and the third line L3 and the first line L1 are separated by a second spacing S2 in the second direction D2.

In actual implementation, the first line L1, second line L2 and third line L3 may be conductive metal lines with dielectrics isolated therebetween. In conventional skill, since the operating voltage of embedded high voltage (eHV) device is higher (5V-27V in comparison to 1.2V-3.3V of ordinary logic device) and the pointed feature at the end 10 of first line L1, the electric field there will be higher (may reach up to one hundred time of ordinary logic device) and tends to burn-out the surrounding dielectrics, especially along the discharge path between the end 10 of first line L1, the second line L2 and the third line L3. The burn-out of dielectrics may cause issues in the aspect of electrical property, reliability and life time of the device.

Please refer to FIG. 2, which is an enlarged schematic view of a semiconductor pattern in accordance with the embodiment of present invention. In order to solve the aforementioned issues, the present invention uses optical proximity correction (OPC) tool to perform a rounding action to the end 10 of first line L1, so as to form a rounding feature 12 at the end. Specifically, as shown in figure, the first line L1 has an initial width W₀ gradually increasing to a maximum width W_max toward the end 10 and then gradually decreasing and converging to form the rounding feature 12 at the end 10.

Please note that the width of rounding feature 12 formed in the rounding action of present invention is larger than the initial width W₀ of first line L1 before the convergence, so that its radius of curvature (i.e. half of the maximum width W_max) is increased and the electric field there is therefore decreased. In comparison to the feature of present invention above, common line-end rounding action in prior art is directly decreasing and converging the line width toward the end to form a rounding feature (as denoted by the dashed line in the figure), with its width not excessing the predetermined line width W₀, so that the radius of curvature of the rounding feature is not relatively increased with respect to the original line width, which has limited effect to decrease the electrical field.

Furthermore, please refer back to FIG. 1. Since the first line L1, second line L2 and specific design of the first line L1 in the semiconductor pattern of present invention, in the embodiment of present invention in addition of forming the rounding feature above, the issue of discharge burn-out may be further prevented by specifying the dimension of these features. For example, the first spacing S1 may be designedly between 200 nm and 300 nm, the ratio of first spacing S1 to the maximum width W_max of rounding feature 10 may be designedly between 1.5 and 3.0, the initial width W₀ of first line L1 may be designedly between 80 nm and 100 nm, the ratio of the maximum width W_max of rounding feature 10 to the initial width W₀ of first line L1 may be designedly between 0.5 and 1.2, the radius of curvature of the rounding feature 10 (half of the maximum width W_max) may be designedly between 30 nm and 50 nm, or the ratio of the first spacing S1 to the second spacing S2 may be designedly between 1.0 and 2.0. Besides, as shown in FIG. 2, a ratio of a length L from a position of the width of first line L1 beginning to increase to the end to the maximum width W_max of the rounding feature 10 maybe designedly between 1.0 and 2.0.

According to the embodiment above, the semiconductor pattern and method of rounding the same provided by the present invention may decrease the electric field at line end through the formation of the rounding feature with width larger than the original line width, thereby preventing the device reliability issue caused by the burn-out of adjacent dielectrics and being particularly suitable for the manufacture of eHV devices, which is invention provided both with novelty and non-obviousness.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor pattern, comprising: a first line extending to one end in a first direction; anda second line extending in a second direction perpendicular to said first direction and adjacent to said end of said first line;wherein said end of said first line is provided with a rounding feature, said first line has a width in said second direction, and said width gradually increases to a maximum width toward said end and then gradually decreases and converges to form said rounding feature at said end.

2. The semiconductor pattern of claim 1, wherein a spacing is between said end and said second line in said first direction, and said spacing is between 200 nm and 300 nm.

3. The semiconductor pattern of claim 2, wherein a ratio of said spacing to said maximum width of said rounding feature in said second direction is between 1.5 and 3.0.

4. The semiconductor pattern of claim 1, wherein said width of said first line is between 80 nm and 100 nm.

5. The semiconductor pattern of claim 1, a ratio of said maximum width of said rounding feature in said second direction to said width of said first line in said second direction is between 0.5 and 1.2.

6. The semiconductor pattern of claim 1, a half of said maximum width is a radius of curvature of said rounding feature, and said radius of curvature is between 30 nm and 50 nm.

7. The semiconductor pattern of claim 1, further comprising two third lines respectively at two sides of said first line in said second direction and extending in said first direction to connect with said second line, wherein a first spacing is between said end and said second line, a second spacing is between said first line and said third line, and a ratio of said first spacing to said second spacing is between 1.0 and 2.0.

8. The semiconductor pattern of claim 1, wherein a ratio of a length from a position of said width of said first line beginning to increase to said end to said maximum width of said rounding feature is between 1.0 and 2.0.

9. A method of rounding semiconductor pattern, comprising: providing a semiconductor pattern having a first line and a second line, wherein said first line extends in a first direction to one end, and said second line extends in a second direction perpendicular to said first direction and adjacent to said end of said first line in said first direction; andusing optical proximity correction (OPC) tool to perform a rounding action to said end of said first line, so as to form a rounding feature at said end, wherein said first line has a width in said second direction, and said width gradually increases to a maximum width toward said end and then gradually decreases and converges to form said rounding feature.

10. The method of rounding semiconductor pattern of claim 9, wherein a spacing is between said end and said second line, and said end is between 200 nm and 300 nm.

11. The method of rounding semiconductor pattern of claim 10, wherein a ratio of said spacing to said maximum width of said rounding feature in said second direction is between 1.0 and 1.8.

12. The method of rounding semiconductor pattern of claim 9, wherein said width of said first line is between 80 nm and 100 nm.

13. The method of rounding semiconductor pattern of claim 9, wherein a ratio of said maximum width of said rounding feature in said second direction to said width of said first line in said second direction is between 1.0 and 1.7.

14. The method of rounding semiconductor pattern of claim 9, wherein a half of said maximum width is a radius of curvature of said rounding feature, and said radius of curvature is between 50 nm and 70 nm.

15. The method of rounding semiconductor pattern of claim 9, further comprising providing two third lines respectively at two sides of said first line in said second direction and extending to connect with said second line in said first direction, wherein a first spacing is between said end and said second line in said first direction, a second spacing is between said first line and said second line in said second direction, and a ratio of said first spacing to said second spacing is between 1.0 and 2.0.

16. The method of rounding semiconductor pattern of claim 9, wherein a ratio of a length from a position of said width of said first line beginning to increase to said end to said maximum width of said rounding feature is between 1.0 and 2.0.