Patent Application
20210074721
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-164761, filed on Sep. 10, 2019; the entire contents of which are incorporated herein by reference.
Embodiments of the present disclosure relate to a semiconductor storage device and a manufacturing method of the same.
In the past, there have been known semiconductor storage devices including three dimensionally arranged memory cells. These memory cells may be configured by piercing memory holes in a stacked body in which electrically conductive layers and insulating layers are alternately stacked one on the other, and by forming semiconductor pillars and gate insulating films that surround corresponding lateral surfaces of the semiconductor pillars within the memory holes.
A semiconductor storage device according to embodiments is provided with a stacked-layer structure in which insulating layers and electrically conductive layers are alternately stacked one on another above a base body; a semiconductor layer buried in a bottom portion of a hole that penetrates the stacked-layer structure; a memory layer formed on an inner side surface of the hole having the semiconductor layer buried at the bottom portion thereof; and a channel layer formed on the memory layer in the hole having the semiconductor layer buried at the bottom portion thereof. An upper surface of the semiconductor layer is located within a widened region formed in a part of the hole.
Non-limiting, exemplary embodiments of the present disclosure will now be described with reference to the accompanying drawings. In the drawings, the same or corresponding reference marks are given to the same or corresponding members or components, and redundant explanations will be omitted. It is to be noted that the drawings are illustrative of the disclosure, and there is no intention to indicate scale or relative proportions among the members or components, or between thicknesses of various layers. Therefore, the specific thickness or size should be determined by a person having ordinary skill in the art in view of the following non-limiting embodiments.
Referring to
In the stacked-layer structure SL, the insulating layer SO1 between the sacrificial layer SN1 and the sacrificial layer SN2 is formed of silicon oxide that has a higher wet or dry etching rate than silicon oxide that constitutes the insulating layers SO2, SO3, . . . , which are formed on the upper layer side of the insulating layer SO1. Here, the sacrificial layer SN1 is the lowest layer or the nearest neighbor sacrificial layer to the substrate SUB among the sacrificial layers SN1, SN2, . . . within the stacked-layer structure SL. The sacrificial layer SN2 is the second lowest layer or the sacrificial layer next to the sacrificial layer SN1 on the upper layer side of the sacrificial layer SN1. Additionally, the insulating layer SO1 formed of silicon oxide having a higher etching rate is thicker than the other insulating layers SO2, SO3, . . . , on the upper layer side of the insulating layer SO1.
Next, a photoresist pattern is formed on an upper surface of the stacked-layer structure SL. The photoresist pattern has an opening in a position where a semiconductor pillar is to be formed. Then, the stacked-layer structure SL is etched by an anisotropic etching method such as a reactive ion etching (RIE) method, using the photoresist pattern as a mask. With this, a memory hole 10 that penetrates the stacked-layer structure SL is formed as illustrated in
Subsequently, a wet etching is performed using a diluted hydrofluoric acid (DHF) solution, and thus a part of the memory hole 10 is enlarged in diameter or in lateral directions. With this, a widened region WR is formed as illustrated in
Specifically, because the insulating layer SO1 is formed of silicon oxide that has a higher wet etching rate than silicon oxide that constitutes the other insulating layers SO2, SO3, . . . , as described above, the insulating layer SO1 is etched to a greater extent than the insulating layers SO2, 503, . . . , as illustrated in
Incidentally, in order to form the insulating layer SO1 with silicon oxide that has a higher wet etching rate than silicon oxide that constitutes the insulating layers SO2, 503, . . . , the insulating layer SO1 may be deposited under different deposition conditions from those for the other insulating layers SO2, SO3, . . . . For example, the insulating layer SO1 may be deposited at a lower temperature by a plasma chemical vapor deposition (CVD). The silicon oxide layer deposited at a lower temperature may contain relatively larger amount of impurities. Alternatively, such silicon oxide layer may contain a larger number of Si—OH bonds or Si—H bonds and a smaller number of Si—O bonds. Namely, the silicon oxide that constitutes the insulating layer SO1 may be oxygen-depleted silicon oxide, or silicon oxide deviated from the stoichiometric composition. Therefore, the insulating layer SO1 becomes more susceptible to wet etching.
Next, a single crystalline semiconductor layer (for example, a single crystalline silicon layer) 11 is grown in a bottom portion of the memory hole 10, as illustrated in
Then, the upper surface of the semiconductor layer 11 is exposed to an oxidizing atmosphere produced by a water vapor generator (WVG), and thus oxidized. With this, a silicon oxide film is formed on the semiconductor layer 11. This silicon oxide film serves as a protection film for the semiconductor layer 11, and is referred to as a protection film 11A hereinafter (Step S15, see
Next, as illustrated in
Specifically, the memory layer 12 includes a block insulating layer formed of silicon oxide or the like on the inner side surface and bottom surface of the memory hole 10; a charge storage layer formed of silicon nitride or the like on the block insulating layer; and a tunnel insulating layer formed of silicon oxide or the like on the charge storage layer.
Subsequently, a part of the memory layer 12, the part being exposed as the bottom surface of the memory hole 10, is etched by the RIE method (Step S17). In this etching, the protection film 11A and at least an upper part of the semiconductor layer 11 are also etched. As a result, a larger area of the semiconductor layer 11 becomes exposed, as illustrated in
Next, a channel layer CH and a core layer CR, which serve as a semiconductor pillar (column), are formed (Step S18).
With the above configuration, as illustrated in
Next, the sacrificial layers SN1, SN2, SN3, . . . are replaced with an electrically conductive material such as Tungsten (W), using the pillar as a supporting member, and thus are turned into electrically conductive layers EL1, EL2, EL3, . . . , respectively.
In
As described above, according to the first embodiment, when the semiconductor layer 11, the protection film 11A, and the memory layer 12 are formed in the bottom portion of the memory hole 10 having the widened region WR, the upper surface of the semiconductor layer 11, the protection film 11A, and the memory layer 12 are located in the widened region WR. With this, when the bottom surface of the memory hole 10 is etched, a larger area of the semiconductor layer 11 can be exposed. Therefore, when the channel layer CH is formed on the semiconductor layer 11, the channel layer CH can be in contact at a larger area with the semiconductor layer 11, which allows the contact resistance therebetween to be reduced.
Even in the second embodiment, the insulating layer SO1 between the sacrificial layer SN1 and the sacrificial layer SN2 is formed of silicon oxide that has a higher wet etching rate or dry etching rate than silicon oxide that constitutes the other insulating layers SO2, SO3, . . . in the stacked-layer structure SL. Here the sacrificial layer SN1 is the lowest layer among the sacrificial layers SN1, SN2, SN3, . . . within the stacked-layer structure SL, and the sacrificial layer SN2 is the second lowest layer to the lowest layer. Additionally, the insulating layer SO1 formed of the silicon oxide having a higher etching rate is thicker than the other insulating layers SO2, SO3, . . . on the upper layer side.
Next, a photoresist pattern, which has an opening in a position where a semiconductor pillar is to be formed, is formed on an upper surface of the stacked-layer structure SL. The stacked-layer structure SL is etched by an anisotropic etching method such as a reactive ion etching (RIE) method, using the photoresist pattern as a mask. With this, a memory hole 10 is formed which penetrates the stacked-layer structure SL as illustrated in
Next, a single crystalline semiconductor layer (for example, a single crystalline silicon layer) 11 is grown in a bottom portion of the memory hole 10, as illustrated in
Next, as illustrated in
Next, a memory layer 12 is formed on an inner side surface and a bottom surface of the memory hole 10 (Step S26), as with the first embodiment. As illustrated in
In
Next, the sacrificial layers SN1, SN2, SN3, . . . are replaced with an electrically conductive material such as Tungsten (W), using the pillar as a supporting member, and thus are turned into electrically conductive layers EL1, EL2, EL3, . . . , respectively, as with the first embodiment. Before the electrically conductive layers EL1, EL2, EL3, . . . are formed, a gate-insulating film GI is formed on an outer side surface of the semiconductor layers 11. Even in this embodiment, an intersecting portion of the semiconductor pillar and the electrically conductive layer EL1 functions as a selective transistor, and intersecting portions of the semiconductor pillar and the electrically conductive layers EL2, EL3, . . . function as memory cells. In this way, a semiconductor storage device 100 in which plural memory cells are three-dimensionally arranged is obtained (see
As described above, even in the second embodiment, when the bottom surface of the memory hole 10 is etched, a larger area of the semiconductor layer 11 can be exposed. With this, when the channel layer CH is formed on the semiconductor layer 11, the channel layer CH can be in contact at a larger area with the semiconductor layer 11, which allows the contact resistance therebetween to be reduced.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
For example, while the widened region WR is formed by the wet etching method in the above embodiments, the widened region WR may be formed by a dry etching method.
Additionally, although the widened region WR is formed in the insulating layer located between the lowest electrically conductive layer and the second lowest electrically conductive layer of the stacked-layer structure SL in the above embodiments, the widened region WR may be formed, for example but not limited to, in an insulating layer corresponding to a position where the channel layer CH is electrically in contact with the semiconductor layer 11. Even with this, a contact resistance between the channel layer CH and the semiconductor layer 11 can be reduced.
Moreover, while specific examples of manufacturing methods of a semiconductor device have been described, the semiconductor storage device according to embodiments may be manufactured by any manufacturing methods, as long as the widened region of the memory hole can be formed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-164761 | Sep 2019 | JP | national |
