Patent Application
20220302160
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-044005, filed Mar. 17, 2021, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor storage device and a method for fabricating a semiconductor storage device.
In a semiconductor storage device, such as three-dimensional semiconductor memory, it is desired to increase the performance of films, such as a charge storage film used in a memory cell.
Embodiments provide a semiconductor storage device and a method for fabricating the semiconductor storage device, the device and the method which can increase the performance of certain memory cell films.
In general, according to one embodiment, a semiconductor storage device includes a plurality of electrode films on a substrate alternating with a plurality of gaps or insulating layers. A charge storage film is provided on a side surface of each of the plurality of electrode films with a first insulating film placed therebetween. A semiconductor film is provided on a side surface of the charge storage film with a second insulating film placed therebetween. Furthermore, a concentration of a first element in the charge storage film on adjacent to each gap or insulating film is higher than a concentration of the first element in the charge storage film adjacent to each electrode film. The first element is one of boron, niobium, or molybdenum.
Hereinafter, certain example embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference symbols and overlapping explanations for subsequent examples may be omitted.
The semiconductor storage device of
The electrode film 13 includes a barrier metal layer 13a and an electrode material layer 13b, and the block insulating film 14 includes an insulating layer 14a and an insulating layer 14b. Furthermore,
The substrate 1 is a semiconductor substrate such as a silicon substrate, for example. In the present specification, a +Z direction is referred to as an upward direction, and a −Z direction is referred to as a downward direction. The −Z direction may coincide with the direction of gravity, but the −Z direction does not have to coincide with the direction of gravity.
The stacked portion 2 includes: the plurality of films 12 formed above the substrate 1; and the plurality of air gaps 11. The air gaps 11 and the films 12 are alternately formed/stacked with one another. Each air gap 11 is a space or void filled with air. Each film 12 includes the block insulating film 14 and the electrode film 13.
The columnar portion 3 has a columnar shape (e.g., a cylindrical or pillar shape) extending in the Z direction through the stacked portion 2. The columnar portion 3 includes the charge storage film 15, the tunnel insulating film 16, the channel semiconductor film 17, and the core insulating film 18 which are formed in this order on a side surface of the stacked portion 2. The semiconductor storage device of the first embodiment includes a plurality of columnar portions 3 in the stacked portion 2, but
The block insulating film 14 in each film 12 includes the insulating layer 14a and the insulating layer 14b. The electrode film 13 in each film 12 includes the barrier metal layer 13a and the electrode material layer 13b. The insulating layer 14a, the insulating layer 14b, the barrier metal layer 13a, and the electrode material 13b are formed in this order on a side surface of the charge storage film 15. The insulating layer 14b and the barrier metal layer 13a are formed not only on the side surface of the electrode material layer 13b, but also on the upper surface and the lower surface of the electrode material layer 13b. The barrier metal layer 13a is a titanium nitride (TiN) film, for example. The electrode material layer 13b is a tungsten (W) layer, for example. The insulating layer 14a is a silicon oxide (SiO2) film, for example. The insulating layer 14b is an aluminum oxide (AlOx) film, for example.
The charge storage film 15 is formed on a side surface of each block insulating film 14. The side surface of the charge storage film 15 is also in contact with each air gap 11. The charge storage film 15 is used to store the charge in a memory cell transistor corresponding to the written/stored data. The charge storage film 15 is a silicon nitride (SiN) film, for example. The charge storage film 15 is formed on a side surface of each electrode film 13 with the block insulating film 14 placed therebetween.
The tunnel insulating film 16 is formed on a side surface of the charge storage film 15. The tunnel insulating film 16 is a silicon oxynitride (SiON) film, for example.
The channel semiconductor film 17 is formed on a side surface of the tunnel insulating film 16. The channel semiconductor film 17 functions as a channel of a memory cell transistor or a select transistor. The channel semiconductor film 17 is a polysilicon layer, for example. The channel semiconductor film 17 is formed on the side surface of the charge storage film 15 with the tunnel insulating film 16 placed therebetween.
The core insulating film 18 is formed on a side surface of the channel semiconductor film 17. The core insulating film 18 is a SiO2 film, for example.
The charge storage film 15, the tunnel insulating film 16, the channel semiconductor film 17, and the core insulating film 18 each include regions located adjacent to (at the same Z direction position as) the films 12 and regions adjacent to (at the same Z direction position as) the air gaps 11. A memory cell (also referred to as a memory cell transistor) of the semiconductor storage device of the first embodiment is formed in the regions adjacent to the films 12. This region can be referred to as a cell portion. The region between the adjacent cell portions is referred to as an inter-cell portion. The charge storage film 15, the tunnel insulating film 16, the channel semiconductor film 17, and the core insulating film 18 each include the cell portions on the adjacent to the films 12 and the inter-cell portion adjacent to the air gaps 11.
In the first embodiment, the charge storage film 15 contains dopant element 21 (boron atoms). It is to be noted that the B concentration in the charge storage film 15 on the side of the air gap 11 is higher than the B concentration in the charge storage film 15 on the side of the film 12. That is, the B concentration in the charge storage film 15 in the inter-cell portion is higher than the B concentration in the charge storage film 15 in the cell portion.
According to this comparative example, by adding the dopant element 21 (boron) in the charge storage film 15 in the inter-cell portion, it is possible to lower the dielectric constant of the charge storage film 15 in the inter-cell portion and reduce the capacitance of the inter-cell portion. This makes it possible to prevent interference between the memory cells and curb the spread of the distribution of the threshold voltages of the memory cells.
On the other hand, the charge storage film 15 in the cell portion of this comparative example contains the dopant element 21 (boron) whose concentration is equal to the concentration of the dopant element 21 (boron) in the charge storage film 15 in the inter-cell portion. When the charge storage film 15 in the cell portion contains a high concentration of the dopant element 21 (boron), a defect is likely to occur in the charge storage film 15 in the cell portion, which results in a dielectric strength failure and a decrease in reliability of the memory cell.
Moreover, an electric field from the electrode film 13 tends to be applied to the charge storage film 15 in the inter-cell portion of this comparative example. Thus, when a memory cell erasing operation is performed, a hole is also injected into the charge storage film 15 in the inter-cell portion and remains as a residual hole. When a memory cell write operation is then performed, the hole injected at the time of erasing operation and an electron written at the time of write operation become electrically neutral. This results in degradation in characteristics of the memory cell or a decrease in the reliability (data retention property) of the memory cell.
By adding the dopant element 21 (boron) to the charge storage film 15 in the inter-cell portion in high concentrations, as also in the case of the comparative example, it is possible to lower the dielectric constant of the charge storage film 15 in the inter-cell portion and reduce the capacitance of the inter-cell portion. This makes it possible to prevent interference between the memory cells and curb the spreading of the distribution of the threshold voltages of the memory cells. In the first embodiment, the B concentration in the charge storage film 15 in the inter-cell portion is 5.0×1020 atoms/cm3 or more, for example.
Additionally, the boron concentration in the charge storage film 15 in the cell portion of the first embodiment is lower than the boron concentration in the charge storage film 15 in the inter-cell portion. This makes it possible to prevent a defect from occurring in the charge storage film 15 in the cell portion and thus prevent a dielectric strength failure and a decrease in reliability of the memory cell.
Furthermore, by adding the dopant element 21 (boron) to the charge storage film 15 in the cell portion in low concentrations, it is possible to make the trap level deeper in the charge storage film 15 in the cell portion. This makes it possible to improve the write characteristic and charge retention property of the memory cell. In the first embodiment, the boron concentration in the charge storage film 15 in the cell portion is in a range of 1.0×1019 atoms/cm3 to 5.0×1020 atoms/cm3, for example.
Moreover, the semiconductor storage device of the first embodiment includes the air gaps 11 in place of the insulating films 19. This makes the electric field from the electrode film 13 even less likely to be applied to the charge storage film 15 in the inter-cell portion. This makes it possible to prevent a residual hole from remaining at the time of memory cell erasing operation and improve the charge retention property of the memory cell.
First, a plurality of sacrificial films 31 and a plurality of sacrificial films 32 are alternately formed above a substrate 1 (
An air gap 11 is formed in place of each sacrificial film 31. The sacrificial film 31 is a silicon (Si) layer having a film thickness of about 30 nm, for example, and is formed by plasma chemical vapor deposition (CVD) using silane (SiH4) gas.
A film 12 eventually replaces each sacrificial film 32. The sacrificial film 32 is a SiN film having a film thickness of about 30 nm, for example, and is formed by plasma CVD using dichlorosilane (SiH2Cl2) gas and ammonia (NH3) gas.
Next, a memory hole H1 is formed in the sacrificial films 31 and the sacrificial films 32 by lithography and reactive ion etching (RIE) (
Then, the front surface of each sacrificial film 32, which is exposed by the formation of the memory hole H1, is oxidized (
Next, a charge storage film 15, a tunnel insulating film 16, a channel semiconductor film 17, and a core insulating film 18 are formed in order in the memory hole H1 (
The charge storage film 15 is a silicon nitride (SiN) film having a film thickness of about 6 nm, for example, and is formed by atomic layer deposition (ALD) in a reduced-pressure environment (2000 Pa or less) at 300° C. to 800° C. using dichlorosilane (SiH2Cl2) gas and NH3 gas. In the present embodiment, the dopant element 21 (boron) is added to the charge storage film 15 by supplying BCl3 gas during this ALD sequence, or the addition of the dopant element 21 (boron) to the charge storage film 15 is performed by, for example, adding the dopant element 21 (boron) to the front surface of the charge storage film 15 and thermally diffusing the dopant element 21 (boron) in the charge storage film 15. At the stage of
The tunnel insulating film 16 is a silicon oxynitride (SiON) film having a film thickness of about 7 nm, for example, and is formed by ALD in a reduced-pressure environment (2000 Pa or less) at 400° C. to 800° C. using hexachlorodisilane (“HCD”) gas, NH3 gas, and O2 gas. The channel semiconductor film 17 is a silicon layer having a film thickness of about 10 nm, for example, and is formed by CVD in a reduced-pressure environment (2000 Pa or less) at 400° C. to 800° C. using silane (SiH4) gas as precursor. The resulting silicon film can then be crystallized by annealing. This causes this silicon layer to change to a polysilicon layer from an amorphous silicon layer. The core insulating film 18 is a SiO2 film, for example, and is formed by CVD using tetraethyl orthosilicate (“TEOS”).
Then, a slit is formed in the sacrificial films 31 and the sacrificial films 32 and the sacrificial films 32 are removed via the slit (
Next, an insulating layer 14b, a barrier metal layer 13a, and an electrode material layer 13b are formed in order in each cavity H2 from the slit (
Then, the sacrificial films 31 are removed from the slit (
Next, the dopant element 21 (boron) is added to the charge storage film 15 from the air gaps 11 (
In the process of
Then, various insulating films, wiring layers, plug layers, and the like are formed on the substrate 1. For example, the slit mentioned above is filled with an insulating film. In this way, the semiconductor storage device of the present embodiment is fabricated.
As described above, the charge storage film 15 of the first embodiment is formed such that the boron concentration in the portion of the charge storage film 15 adjacent the air gap 11 is higher than the boron concentration in the portion of the charge storage film 15 adjacent the film 12 . Thus, according to the first embodiment, as described with reference to
In addition to the same aspects as those of the semiconductor storage device of the first embodiment, the semiconductor storage device of the second embodiment includes a deuterium (D) dopant (dopant element 22 (D)) in columnar portions 3.
The dopant element 22 (deuterium) may be contained in each or any of a charge storage film 15, a tunnel insulating film 16, a channel semiconductor film 17, a core insulating film 18, an interface between the charge storage film 15 and the tunnel insulating film 16, an interface between the tunnel insulating film 16 and the channel semiconductor film 17, and an interface between the channel semiconductor film 17 and the core insulating film 18. Furthermore, the dopant element 22 (deuterium) may be contained in a block insulating film 14 or an interface between the block insulating film 14 and the charge storage film 15. According to the second embodiment, the dopant element 22 (deuterium) increases the reliability of the memory cell.
The columnar portion 3 may contain a hydrogen (H) element as an impurity in addition to the dopant element 22 (deuterium). It is preferable that, in an area containing the deuterium and the hydrogen, the deuterium concentration be higher than the hydrogen concentration. For example, when the charge storage film 15 contains the dopant element 22 (deuterium) and the hydrogen atoms, the deuterium concentration in the charge storage film 15 is preferably higher than the hydrogen concentration in the charge storage film 15. Likewise, when an interface between the charge storage film 15 and the tunnel insulating film 16 contains the dopant element 22 (deuterium) and the H element, it is preferable that the D concentration at the interface is higher than the H concentration at the interface.
In a first modified example shown in
In a second modified example shown in
First, the processes of
The above-mentioned annealing is performed using mixed gas containing deuterium (D2) gas or deuterium oxide (D2O) gas, for example. This mixed gas may further contain oxygen (O2) gas, helium (He) gas, neon (Ne) gas, argon (Ar) gas, krypton (Kr) gas, xenon (Xe) gas, or radon (Rn) gas. In the above-mentioned annealing, deuterium plasma is generated from D2 gas or D2O molecules and the deuterium plasma enter the columnar portion 3 from each cavity H2, whereby the dopant element 22 (deuterium) is added to the columnar portion 3. In so doing, the above-mentioned annealing may be performed with the assistance of not only radical components, but also ion components.
The above-mentioned annealing is performed at 800° C. for 30 seconds, for example. According to the second embodiment, by performing radical-assisted annealing, it is possible to add the dopant element 22 (deuterium) to the columnar portion 3 in a short time. For example, when the dopant element 22 (deuterium) is added by D2 (heavy hydrogen gas) annealing, by performing this annealing at 700° C. to 900° C. for 30 minutes, the dopant element 22 (deuterium) can be added to the columnar portion 3. In other examples, according to the present embodiment, by performing radical-assisted annealing at 700° C. or higher for 30 seconds, the dopant element 22 (deuterium) can be added to the columnar portion 3.
Then, a barrier metal layer 13a and an electrode material layer 13b are formed in order in each cavity H2 from the slit mentioned above (
Next, the processes of
As described above, the columnar portion 3 of the second embodiment contains the dopant element 22 (deuterium). According to the second embodiment, the dopant element 22 (deuterium) increases the reliability of the memory cell. Furthermore, according to the second embodiment, by adding the dopant element 22 (deuterium) by radical-assisted annealing, it is possible to add the dopant element 22 (deuterium) in a short time.
The semiconductor storage device of the third embodiment includes a plurality of insulating films 19 in place of the plurality of air gaps 11 of the semiconductor storage device of the first embodiment. The insulating film 19 is a SiO2 film, for example.
Moreover, the semiconductor storage device of the third embodiment includes an insulating layer 14a as part of a columnar portion 3 instead of an insulating layer 14a on each film 12. That is, the insulating layer 14a is continuous along the length of the columnar portion 3 instead being provided in discrete portions separated from one another. In the third embodiment, the insulating layer 14a, a charge storage film 15, a tunnel insulating film 16, a channel semiconductor film 17, and a core insulating film 18 are formed in order on a side surface of each of the plurality of insulating films 19 and a plurality of films 12.
Furthermore, the semiconductor storage device of the third embodiment includes niobium (Nb) (dopant element 23) in the charge storage film 15 in place of the dopant element 21 (boron).
In other examples, the charge storage film 15 of the third embodiment may contain a molybdenum (Mo) in place of, or along with niobium. In this case, the molybdenum atomic concentration in the charge storage film 15 and the presence of elements other than the molybdenum can be designed in the same manner as described for niobium (dopant element 23) above. Moreover, the semiconductor storage device of the third embodiment may include the dopant element 21 (boron) and/or dopant element 22 (deuterium) such as in the case of the semiconductor storage devices of the first embodiment and the second embodiment.
According to the third embodiment, by adding the niobium dopant element 23 to the charge storage film 15, it is possible to make the trap level in the charge storage film 15 deeper. Thus, it is preferable to add the niobium dopant element 23 to the charge storage film 15 in the cell portion and the inter-cell portion. Moreover, the higher the niobium concentration in the charge storage film 15 becomes, the closer to the properties of a metal layer the charge storage film 15 will obtain, therefore, it is preferable to set the Nb concentration in the charge storage film 15 at 1.0×1021 atoms/cm3 or less. The same goes for a case where the molybdenum is used in place of niobium.
In the example shown in
In the example shown in
In the example shown in
First, a plurality of insulating films 19 and a plurality of sacrificial films 33 are alternately formed above a substrate 1 and a memory hole H1 is formed in the insulating films 19 and the sacrificial films 33 by lithography and RIE (
Next, an insulating layer 14a, a charge storage film 15, a tunnel insulating film 16, a channel semiconductor film 17, and a core insulating film 18 are formed in this order in the memory hole H1 (
The charge storage film 15 is a silicon nitride (SiN) film having a film thickness of about 6 nm, for example, and is formed by ALD in a reduced-pressure environment at 300° C. or to 800° C. using dichlorosilane (SiH2Cl2) gas and ammonia (NH3) gas. In the third embodiment, by supplying niobium pentachloride (NbCl5), water (H2O), and ammonia (NH3) during the ALD sequence, the niobium dopant element 23 is added to the charge storage film 15. In this case, the niobium dopant element 23 is added to the charge storage film 15 in the form of niobium oxynitride (NbOxNy), for example. In the third embodiment, the molybdenum dopant element 24 may be added to the charge storage film 15 by supplying MoCl5, NH3, and zinc (Zn) during this ALD sequence. In this case, the molybdenum dopant element 24 is added to the charge storage film 15 in the form of molybdenum nitride (MoNy), for example. The charge storage film 15 of the third embodiment is formed after the formation of the insulating layer 14a.
The tunnel insulating film 16 is a SiON film having a film thickness of about 7 nm, for example, and is formed by ALD in a reduced-pressure environment at 400° C. to 800° C. using HCD gas, NH3 gas, and O2 gas. The channel semiconductor film 17 is a silicon layer having a film thickness of about 10 nm, for example, and is formed by CVD in a reduced-pressure environment at 400° to 800° C. using silane (SiH4) gas. The resulting film is then crystallized by annealing. This causes this silicon layer to change to a polysilicon layer from an amorphous silicon layer. The core insulating film 18 is a SiO2 film, for example, and is formed by CVD using TEOS.
Then, an unillustrated slit is formed in the insulating films 19 and the sacrificial films 33 and the sacrificial films 33 are removed from the slit (
Next, an insulating layer 14b, a barrier metal layer 13a, and an electrode material layer 13b are formed in order in each cavity H2 from the slit (
Then, various insulating films, wiring layers, plug layers, and the like are formed on the substrate 1. For example, the previously formed slit is filled with an insulating film. In this way, the semiconductor storage device of the third embodiment is fabricated.
As described above, the charge storage film 15 of the present embodiment is formed so as to contain at least one of the niobium dopant element 23 and the molybdenum dopant element 24. Thus, according to the third embodiment, as described with reference to
The semiconductor storage device of the present embodiment includes a substrate 41 and a plurality of stacked portions formed above the substrate 41, and, as shown in
The substrate 41 is a semiconductor substrate such as a silicon substrate, for example.
The insulating films 42 extend in the Y direction. The insulating film 42 is a SiO2 film, for example. The electrode films 43 also extend in the Y direction. The electrode films 43 include a TiN film as a barrier metal layer and include a W layer as an electrode material layer, for example.
As shown in
The block insulating film 44, the charge storage film 45, and the tunnel insulating film 46 extend in the Y direction and the Z direction. The block insulating film 44 is a SiO2 film, for example. The charge storage film 45 is a SiN film, for example. The tunnel insulating film 46 is a SiON film, for example.
The channel semiconductor film 47, the core insulating film 48, and the insulating film 49 extend in the Z direction. The two stacked portions share the core insulating film 48. The insulating film 49 is provided between the channel semiconductor films 47 which are adjacent to each other in the Y direction and between the core insulating films 48 which are adjacent to each other in the Y direction. The channel semiconductor film 47 is a polysilicon layer, for example. The core insulating film 48 is a SiO2 film, for example. The insulating film 49 is a SiO2 film, for example.
As described above, in the semiconductor storage device of the present embodiment, the electrode film 43 extends in the Y direction and the channel semiconductor film 47 extends in the Z direction. Thus, the electrode film 43 and the channel semiconductor film 47 intersect at predetermined Y coordinate and Z coordinate. A point at which the electrode film 43 and the channel semiconductor film 47 intersect will be referred to as a “point of intersection”. In the present embodiment, a region located at a point of intersection is a cell portion and a region displaced, in the Y direction, from the cell portion is an inter-cell portion.
In the present embodiment, the charge storage film 45 contains the dopant element 21 (boron). It is to be noted that, as shown in
The boron concentration in the charge storage film 45 in the inter-cell portion is 5.0×1020 atoms/cm3 or more, for example. The boron concentration in the charge storage film 45 in the cell portion is 1.0×1019 atoms/cm3 or more but less than 5.0×1020 atoms/cm3, for example. The charge storage film 45 in the cell portion may contain the dopant element 21 (boron), the charge storage film 45 does not otherwise have to contain the dopant element 21.
It is to be noted that, as in the case of the semiconductor storage device of the first, second, or third embodiment, the semiconductor storage device of the fourth embodiment may contain at least one of the dopant element 22 (deuterium), the niobium dopant element 23, and the molybdenum dopant element 24. In this case, the block insulating film 14, the charge storage film 15, the tunnel insulating film 16, the channel semiconductor film 17, and the core insulating film 18 of the first, second, or third embodiment respectively correspond to the block insulating film 44, the charge storage film 45, the tunnel insulating film 46, the channel semiconductor film 47, and the core insulating film 48 of the present embodiment. Moreover, the semiconductor storage device of the fourth embodiment may contain the dopant element 21 (boron) not only in the charge storage film 45, but also in the channel semiconductor film 47.
According to this comparative example, by adding the Dopant element 21 to the charge storage film 45 in the inter-cell portion, it is possible to lower the dielectric constant of the charge storage film 45 in the inter-cell portion and reduce the capacitance of the inter-cell portion. This makes it possible to prevent interference between the memory cells and curb the spread of the distribution of the threshold voltages of the memory cells.
On the other hand, the charge storage film 45 in the cell portion of this comparative example contains the Dopant element 21 whose concentration is equal to the concentration of the Dopant element 21 in the charge storage film 45 in the inter-cell portion. When the charge storage film 45 in the cell portion contains a high concentration of the Dopant element 21, a defect occurs in the charge storage film 45 in the cell portion, which results in a dielectric strength failure and a decrease in reliability of the memory cell.
According to the present embodiment, by adding the Dopant element 21 to the charge storage film 45 in the inter-cell portion in high concentrations, as in the case of the above-mentioned comparative example, it is possible to lower the dielectric constant of the charge storage film 45 in the inter-cell portion and reduce the capacitance of the inter-cell portion. This makes it possible to prevent interference between the memory cells and curb the spread of the distribution of the threshold voltages of the memory cells. In the present embodiment, the B concentration in the charge storage film 45 in the inter-cell portion is 5.0×1020 atoms/cm3 or more, for example.
Moreover, the B concentration in the charge storage film 45 in the cell portion of the present embodiment is lower than the B concentration in the charge storage film 45 in the inter-cell portion. This makes it possible to prevent a defect from occurring in the charge storage film 45 in the cell portion and prevent a dielectric strength failure and a decrease in reliability of the memory cell.
Furthermore, according to the present embodiment, by adding the Dopant element 21 to the charge storage film 45 in the cell portion in low concentrations, it is possible to make deeper the trap level in the charge storage film 45 in the cell portion. This makes it possible improve the write characteristic and charge retention property of the memory cell. In the present embodiment, the B concentration in the charge storage film 45 in the cell portion is in a range of 1.0×1019 atoms/cm3 to 5.0×1020 atoms/cm3, for example.
First, a plurality of insulating films 42 and a plurality of sacrificial films 50 are alternately formed on a substrate 41, and a memory hole H3 is formed in the insulating films 42 and the sacrificial films 50 by lithography and RIE (
Next, a block insulating film 44 and a charge storage film 45 are formed in this order in the memory hole H3 (
The charge storage film 45 is a SiN film having a film thickness of about 7 nm, for example, and is formed by ALD in a reduced-pressure environment (2000 Pa or less) at 300° C. to 800° C. using SiH2Cl2 gas and NH3 gas. In the present embodiment, by supplying BCl3 gas during this ALD sequence, the dopant element 21 (boron) is added to the charge storage film 45. The addition of the boron to the charge storage film 45 is performed by, for example, adding the dopant element 21 (boron) to the front surface of the charge storage film 45 and thermally diffusing the dopant element 21 (boron) into the charge storage film 45. At the stage of
Then, a tunnel insulating film 46, a channel semiconductor film 47, and a core insulating film 48 are formed in order in the memory hole H3 (
The tunnel insulating film 46 is a SiON film having a film thickness of about 6 nm, for example, and is formed by ALD in a reduced-pressure environment (2000 Pa or less) at 400° C. to 800° C. or lower using hexachlorodisilane (“HCD”) gas, NH3 gas, and O2 gas. The channel semiconductor film 47 is a silicon layer having a film thickness of about 10 nm, for example, and is formed by CVD in a reduced-pressure environment (2000 Pa or less) at 400° C. to 800° C. using SiH4 gas. The resulting film is then crystallized by annealing. This causes this silicon layer to change to a polysilicon layer from an amorphous silicon layer. The core insulating film 48 is a SiO2 film, for example, and is formed by CVD using TEOS.
Next, a hole H4 is formed in the channel semiconductor film 47 and the core insulating film 48 by lithography and RIE (
Then, BCl3 gas is supplied to the inside of the hole H4 (FIGS. 22A and 22B). As a result, BCl3 molecules adsorb onto a side surface of the tunnel insulating film 46 that is exposed in the hole H4.
Next, the dopant element 21 (boron) in the BCl3 molecules is thermally diffused in the charge storage film 45 (
Then, various insulating films, wiring layers, plug layers, and the like are formed on the substrate 41. For example, the hole H4 is filled with an insulating film 49 and the sacrificial films 50 are replaced with the electrode films 43 (
First, in this modification the processes shown in
Then, a core insulating film 48 is formed in the memory hole H3, and a hole H4 is formed in the channel semiconductor film 47 and the core insulating film 48 by lithography and RIE. A side surface of the channel semiconductor film 47 is then nitrided using N2 radicals (
Next, the processes shown in
As described above, the charge storage film 45 of the fourth embodiment is formed such that the B concentration in the charge storage film 45 portion between the electrode film 43 and the insulating film 49 is higher than the B concentration in the charge storage film 45 portion between the electrode film 43 and the channel semiconductor film 47. That is, the B concentration in the charge storage film 45 has a non-constant distribution along the Y direction. The B concentration of the charge storage film 45 between the electrode film 43 and the insulating film 49 is higher than the B concentration of the charge storage film 45 between the electrode film 43 and the channel semiconductor film 47. As a result, the B concentration in the charge storage film 45 in the inter-cell portion is higher than the B concentration in the charge storage film 45 in the cell portion. Thus, according to the fourth embodiment, as described with reference to
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-044005 | Mar 2021 | JP | national |
