This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-033948, filed Mar. 3, 2021, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor storage device.
A semiconductor storage device may include a substrate and conductor layers arranged on the substrate in a first direction orthogonal to a surface of the substrate. A semiconductor pillar may extend along the first direction through the conductor layers, and a gate insulating film can be provided between the conductor layers and the semiconductor pillar. The gate insulating layer comprises a memory unit capable of storing data. The memory unit utilizes an insulating charge storage layer including silicon nitride (Si3N4) or a conductive charge storage layer such as a floating gate to store data.
Embodiments provide a semiconductor storage device that can be easily integrated.
In general, according to one embodiment, a semiconductor storage device includes a substrate, a plurality of first conductive layers stacked on each other in a first direction intersecting a surface of the substrate and extending along a second direction parallel to the surface. A semiconductor layer extends in the first direction through the first conductive layers and faces each of first conductive layers in the second direction. A gate insulating film is between the semiconductor layer and the plurality of first conductive layers. A first resistance element on the substrate and extending in the first direction. One end of the first resistance element in the first direction is closer to the substrate than at least a part of the plurality of first conductive layers. The other end of the first resistance element in the first direction is farther from the substrate than the plurality of first conductive layers.
Next, semiconductor storage devices according to a plurality of embodiments will be described with reference to the drawings. The following embodiments are merely examples and are not intended to limit the present disclosure. The following drawings are schematic and some parts or structures and the like may be omitted for convenience of explanation. The same reference numerals may be given to parts common to a plurality of embodiments and the descriptions thereof may be omitted.
When the term “semiconductor storage device” is used in the present specification, the term may mean a memory die or a memory system including a controller die such as a memory chip, a memory card, or a solid-state drive (SSD). The term may also mean a host computer such as a smartphone, a tablet terminal, and a personal computer.
When the term “control circuit” is used in the present specification, the term may mean a peripheral circuit such as a sequencer provided on the memory die or may mean a controller die or a controller chip connected to the memory die, or a device that includes both.
In the present specification, when a first component is said to be “electrically connected” to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via a wiring, a semiconductive member, a transistor, or the like. For example, when three transistors are connected in series, the first transistor can be said to be “electrically connected” to the third transistor even when the second transistor is in the OFF state.
In the present specification, when a first element is said to be “connected between” a second element and a third element, the phrase may mean that the first element, the second element, and the third element are connected in series and that the second element is connected to the third element via the first element.
In the present specification, when a circuit or the like is said to “conduct” two wirings or elements, the term may mean that the circuit (or the like) includes a transistor or switching element, and the transistor (or the like) is provided on a current path between the two wirings and that the transistor or the like has been turned on (made conductive) within the context of the description.
In the present specification, a direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction orthogonal to the upper surface of the substrate is referred to as the Z direction.
In the present specification, in some cases, a direction along a certain surface is referred to as a first direction, a direction intersecting the first direction along the surface is referred to as a second direction, and a direction intersecting the surface is referred to as a third direction. The first direction, the second direction, and the third direction may or may not correspond to any of the X direction, the Y direction, and the Z direction.
In the present specification, relative positional expressions such as “upper” and “lower” are generally used with reference to the direction orthogonal to the substrate. For example, the direction away from the substrate along the Z direction is referred to as upward, and the direction approaching the substrate along the Z direction is referred to as downward. When referring to a lower surface or a lower end of a certain element, use of “lower” means a surface or an end portion of the element on the side thereof closer to (and generally facing) the substrate, and when referring to an upper surface or an upper end of an element, use of “upper” means a surface or an end of the element on the side thereof farther from (and generally facing away from) the substrate. A surface of an element that intersects the X direction and/or the Y direction is referred to as a side surface or the like.
In the present specification, when referring to “width”, “length”, “thickness”, or the like in a direction in an element, a member, or the like, they may mean width, length, thickness, or the like in a cross section or the like observed by scanning electron microscopy (SEM), transmission electron microscopy (TEM), or the like.
In the present specification, when the term “radial direction” is used for a cylindrical or annular member or a through-via hole, the term means the direction of approaching the central axis in a plane perpendicular to the central axis of the cylinder or annulus or the direction away from the central axis in the plane. When the term “thickness in the radial direction” or the like is used, the term means the difference between the distance from the central axis to the inner peripheral surface and the distance from the central axis to the outer peripheral surface in such a plane.
[Circuit Configuration of Memory Die MD]
As shown in
Each memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory transistors), a source-side select transistor STS, and a source-side select transistor STSb. The drain-side select transistor STD, the plurality of memory cells MC, the source-side select transistor STS, and the source-side select transistor STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side select transistor STD, the source-side select transistor STS, and the source-side select transistor STSb may be simply referred to as a select transistor (STD, STS, STSb).
Each memory cell MC is a field effect transistor. The memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. The memory cell MC stores one-bit or multiple-bit data. A word line WL is connected to each of the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. Each of the word lines WL is commonly connected to all memory strings MS in one memory block BLK.
The select transistor (STD, STS, STSb) is a field effect transistor. The select transistor (STD, STS, STSb) includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines (SGD, SGS, SGSb) are connected to the gate electrodes of the select transistors (STD, STS, STSb), respectively. One drain-side select gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side select gate line SGS is commonly connected to all memory strings MS in one memory block BLK. One source-side select gate line SGSb is commonly connected to all memory strings MS in one memory block BLK.
The peripheral circuit PC includes, for example, a voltage generation circuit that generates a plurality of operating voltages, a decoding circuit for applying the generated operating voltage to the bit line BL, the source line SL, the word line, and the select gate line (SGD, SGS, SGSb), a sense amplifier circuit for detecting the voltage or current of the bit line BL, and a sequencer for controlling the above-recited operations. The peripheral circuit PC includes a plurality of transistors, a plurality of capacitors, and a plurality of resistance elements that make up the above circuits.
[Structure of Memory Die MD]
As shown in
As shown in
[Structure of Semiconductor Substrate 100]
The semiconductor substrate 100 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). For example, as shown in
[Structure of Device Layers DLL and DLU in Memory Cell Array Region RMCA]
The memory cell array region RMCA includes a plurality of memory blocks BLK arranged along the Y direction, for example, as shown in
As shown in
The conductive layer 110 is a substantially plate-shaped conductive layer extending along the X direction. The conductive layer 110 may include a barrier conductive film such as titanium nitride (TiN) and a stacked film of a metal film such as tungsten (W). The conductive layer 110 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) and boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged along the Z direction.
A conductive layer 111 is provided below the conductive layer 110. The conductive layer 111 may include, for example, a barrier conductive film such as titanium nitride (TiN) and a stacked film of a metal film such as tungsten (W). An insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 111 and the conductive layer 110.
The conductive layer 111 functions as a gate electrode of the source-side select gate line SGSb (see
Among the plurality of conductive layers 110, one or more conductive layers 110 located at the lowest layer functions as a gate electrode of the source-side select gate line SGS (see
A plurality of conductive layers 110 located above the lowest layer function as gate electrodes of the word lines WL (see
One or more conductive layers 110 located further above function as a gate electrode of the drain-side select gate line SGD and the plurality of drain-side select transistors STD (see
The semiconductor layers 120 are arranged in a predetermined pattern along the X direction and the Y direction. Each semiconductor layer 120 functions as a channel region of a plurality of memory cells MC and select transistors (STD, STS, STSb) in one memory string MS (see
Each semiconductor layer 120 includes a semiconductor region 120L in the device layer DLL and a semiconductor region 120U in the device layer DLU. The semiconductor layer 120 includes a semiconductor region 120J connected to the upper end of the semiconductor region 120L and the lower end of the semiconductor region 120U, and an impurity region 121 connected to the upper end of the semiconductor region 120U. A semiconductor layer 122 is connected to the lower end of each semiconductor layer 120.
The semiconductor region 120L is a substantially cylindrical region extending along the Z direction. The outer peripheral surface of the semiconductor region 120L is surrounded by a plurality of conductive layers 110 in the device layer DLL and faces the plurality of conductive layers 110. The radial width W120LL of the lower end portion of the semiconductor region 120L (for example, the portion located below the plurality of conductive layers 110 in the device layer DLL) is smaller than the radial width W120LU of the upper end portion of the semiconductor region 120L (for example, the portion located above the plurality of conductive layers 110 in the device layer DLL).
The semiconductor region 120U is a substantially cylindrical region extending along the Z direction. The outer peripheral surface of the semiconductor region 120U is surrounded by a plurality of conductive layers 110 in the device layer DLU and faces the plurality of conductive layers 110. The radial width W120UL of the lower end portion of the semiconductor region 120U (for example, the portion located below the plurality of conductive layers 110 in the device layer DLU) is smaller than the radial width W120UU of the upper end portion of the semiconductor region 120U (for example, the portion located above the plurality of conductive layers 110 in the device layer DLU) and the above-described width W120LU.
Each semiconductor region 120J is provided above the plurality of conductive layers 110 in the device layer DLL and is provided below the plurality of conductive layers 110 in the device layer DLU. The radial width W120J of the semiconductor region 120J is larger than the widths W120LU and W120UU.
Each impurity region 121 contains N-type impurities such as phosphorus (P). The impurity region 121 is connected to the bit line BL via a via contact electrode Ch and a via contact electrode Cb (see
Each semiconductor layer 122 is connected to the active region 100A of the semiconductor substrate 100. The semiconductor layer 122 is made of, for example, single crystal silicon (Si) or the like. The semiconductor layer 122 functions as a channel region of the source-side select transistor STSb. The outer peripheral surface of the semiconductor layer 122 is surrounded by the conductive layer 111 and faces the conductive layer 111. An insulating layer 123 such as silicon oxide is provided between the semiconductor layer 122 and the conductive layer 111.
Each gate insulating film 130 has a substantially cylindrical shape that covers the outer peripheral surface of the corresponding semiconductor layer 120.
As shown in
As shown in
[Structure of Device Layers DLL and DLU in Hookup Region RHU]
As shown in
[Structure of Device Layers DLL and DLU in Row Decoder Region RRD]
As shown in
The active region 100A of the semiconductor substrate 100 functions as a channel region of a plurality of transistors Tr that make up the peripheral circuit PC, one electrode of a plurality of capacitors, and the like.
The plurality of electrodes gc in the wiring layer GC function as gate electrodes of the plurality of transistors Tr that make up the peripheral circuit PC, the other electrodes of the plurality of capacitors, and the like. As shown in
Each via contact electrode CS extends along the Z direction. The lower end of the via contact electrode CS is connected to the active region 100A of the semiconductor substrate 100 or the upper surface of the electrode gc. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CS and the active region 100A of the semiconductor substrate 100. The upper end of the via contact electrode CS is connected to the wiring m0. The via contact electrode CS may include, for example, a barrier conductive film made of, for example, titanium nitride (TiN) and a stacked metal film made of, for example, tungsten (W).
The via contact electrode CS includes a conductor region CSL in the device layer DLL and a conductor region CSU in the device layer DLU. The via contact electrode CS includes a conductor region CSJ connected to the upper end of the conductor region CSL and the lower end of the conductor region CSU.
The conductor region CSL is a substantially columnar region extending along the Z direction. The outer peripheral surface of the conductor region CSL is surrounded by an insulating layer 102 made of, for example, silicon oxide (SiO2) contained in the device layer DLL. The radial width WCSLL of the lower end portion of the conductor region CSL is smaller than the radial width WCSLU of the upper end portion of the conductor region CSL (for example, the portion located above the plurality of conductive layers 110 in the device layer DLL). The lower end portion of the conductor region CSL connected to the semiconductor substrate 100 may be, for example, a portion located below the plurality of conductive layers 110 in the device layer DLL. The lower end portion of the conductor region CSL connected to the electrode gc may be, for example, a connection portion with the electrode gc.
The conductor region CSU is a substantially columnar region extending along the Z direction. The outer peripheral surface of the conductor region CSU is surrounded by the insulating layer 102 in the device layer DLU. The radial width WCSUL of the lower end portion of the conductor region CSU (for example, the portion located below the plurality of conductive layers 110 in the device layer DLU) is smaller than the radial width WCSUU of the upper end portion of the conductor region CSU (for example, the portion located above the plurality of conductive layers 110 in the device layer DLU) and the above-described width WCSUU.
Each conductor region CSJ is provided above the plurality of conductive layers 110 in the device layer DLL and is provided below the plurality of conductive layers 110 in the device layer DLU. The radial width WCSJ of the conductor region CSJ is larger than the above-described widths WCSLU and WCSUU.
[Structure of Device Layers DLL and DLU in Peripheral Circuit Region RP]
The peripheral circuit region RP of
Each via resistor VR extends along the Z direction, for example, as shown in
The via resistor VR includes a resistor region VRL in the device layer DLL and a resistor region VRU in the device layer DLU. The via resistor VR includes a resistor region VRJ connected to the upper end of the resistor region VRL and the lower end of the resistor region VRU.
The resistor region VRL is a substantially columnar region extending along the Z direction. The outer peripheral surface of the resistor region VRL is surrounded by the insulating layer 102 in the device layer DLL. The radial width WVRLL of the lower end portion of the resistor region VRL is smaller than the radial width WVRLU of the upper end portion of the resistor region VRL (for example, the portion located above the plurality of conductive layers 110 in the device layer DLL). The lower end portion of the resistor region VRL connected to the semiconductor substrate 100 may be, for example, a portion located below the plurality of conductive layers 110 in the device layer DLL. The lower end portion of the resistor region VRL connected to the electrode gc may be, for example, a connection portion with the electrode gc.
The resistor region VRU is a substantially columnar region extending along the Z direction. The outer peripheral surface of the resistor region VRU is surrounded by the insulating layer 102 in the device layer DLU. The radial width WVRUL of the lower end portion of the resistor region VRU (for example, the portion located below the plurality of conductive layers 110 in the device layer DLU) is smaller than the radial width WVRUU of the upper end portion of the resistor region VRU (for example, the portion located above the plurality of conductive layers 110 in the device layer DLU) and the above-described width WVRLU.
Each resistor region VRJ is provided above the plurality of conductive layers 110 in the device layer DLL and is provided below the plurality of conductive layers 110 in the device layer DLU. The radial width WVRJ of the resistor region VRJ is larger than the above-described widths WVRLU and WVRUU.
[Structure of Wiring Layers M0 and M1]
For example, as shown in
The wiring layer M0 includes a plurality of wirings m0. Each of the plurality of wirings m0 may include, for example, a barrier conductive film made of, for example, titanium nitride (TiN) and a stacked metal film made of, for example, such as tungsten (W).
The wiring layer M1 includes a plurality of wirings m1. Each of the plurality of wirings m1 may include, for example, a barrier conductive film made of, for example, titanium nitride (TiN) and a stacked metal film made of, for example, copper (Cu). Some of the plurality of wirings m1 function as bit lines BL (see
[Manufacturing Method]
Next, a manufacturing method of the memory die MD will be described with reference to
In manufacturing the memory die MD according to the present embodiment, first, the wiring layer GC is formed in the row decoder region RRD and the peripheral circuit region RP of the semiconductor substrate 100.
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, as shown in
Next, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, as shown in
Next, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, as shown in
After that, the memory die MD is formed by forming wiring and the like and dividing the wafer by dicing.
[Effect]
As described with reference to
Here, the thickness of the device layers DLL and DLU in the Z direction increases as the integration becomes higher. Each via resistor VR extends along the Z direction through the device layers DLL and DLU so as to have an enough length (resistor length) in the Z direction to provide the necessary resistance value. Therefore, the circuit area can be significantly reduced as compared with the case where, for example, a part of the wiring layer GC or the semiconductor substrate 100 is used as a resistance element.
For example, when a part of the wiring layer GC is used as a resistance element, the material of the wiring layer GC needs to be selected considering the characteristics of the transistor Tr and the like. The material of the via resistors VR may be selected relatively freely according to manufacturing conditions or the like. For example, when a semiconductor layer such as silicon (Si) containing N-type impurities or P-type impurities is used as the material for the via resistors VR, the characteristics of the via resistors VR can be adjusted in a relatively easy manner by adjusting the impurity concentration. Therefore, according to the via resistors VR according to the present embodiment, it is possible to implement resistance elements having suitable characteristics in a relatively easy manner.
Next, a semiconductor storage device according to a second embodiment will be described with reference to
The semiconductor storage device according to the second embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, the semiconductor storage device according to the second embodiment includes via resistors VR2 instead of the via resistors VR.
Each via resistor VR2 extends along the Z direction. The lower end of the via resistor VR2 is connected to the active region 100A of the semiconductor substrate 100 or the upper surface of the electrode gc. The upper end of the via resistor VR2 is connected to the wiring m0.
The via resistor VR2 includes a resistor region VR2L in the device layer DLL and a conductor region VC in the device layer DLU. The via resistor VR2 includes a resistor region VR2J connected to the upper end of the resistor region VR2L and the lower end of the conductor region VC. The resistor region VR2L and the resistor region VR2J may include, for example, a semiconductor layer made of, for example, silicon (Si) containing N-type impurities or P-type impurities. The conductor region VC may include, for example, a barrier conductive film made of, for example, titanium nitride (TiN) and a stacked metal film made of, for example, tungsten (W).
The resistor region VR2L is a substantially columnar region extending along the Z direction. The outer peripheral surface of the resistor region VR2L is surrounded by the insulating layer 102 in the device layer DLL. The radial width WVR2LL of the lower end portion of the resistor region VR2L is smaller than the radial width WVR2LU of the upper end portion of the resistor region VR2L (for example, the portion located above the plurality of conductive layers 110 in the device layer DLL). The lower end portion of the resistor region VR2L connected to the semiconductor substrate 100 may be, for example, a portion located below the plurality of conductive layers 110 in the device layer DLL. The lower end portion of the resistor region VR2L connected to the electrode gc may be, for example, a connection portion with the electrode gc.
The conductor region VC is a substantially columnar region extending in the Z direction. The outer peripheral surface of the conductor region VC is surrounded by the insulating layer 102 in the device layer DLU. The radial width WVCUL of the lower end portion of the conductor region VC (for example, the portion located below the plurality of conductive layers 110 in the device layer DLU) is smaller than the radial width WVCUU of the upper end portion of the conductor region VC (for example, the portion located above the plurality of conductive layers 110 in the device layer DLU) and the above-described width WVR2LU.
Each resistor region VR2J is provided above the plurality of conductive layers 110 in the device layer DLL in the z direction and is provided below the plurality of conductive layers 110 in the device layer DLU in the z direction. The radial width WVR2J of the resistor region VR2J is larger than the widths WVRLU and WVCUU.
Next, a method of manufacturing the semiconductor storage device according to the second embodiment will be described with reference to
In manufacturing the semiconductor storage device according to the present embodiment, first, among the processes in the method of manufacturing the semiconductor storage device according to the first embodiment, the processes up to the process described with reference to
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, as shown in
After that, the semiconductor storage device according to the second embodiment is formed by forming wiring and the like and dividing the wafer by dicing.
According to the semiconductor storage device according to the second embodiment, it is possible to reduce the circuit area and implement resistance elements having suitable characteristics, similarly to the semiconductor storage device according to the first embodiment.
In the method for manufacturing a semiconductor storage device according to the second embodiment, the amorphous silicon film CSA used as a sacrificial film is used as the resistor region VR2L and the resistor region VR2J of each via resistor VR2, and the conductor region VC of the via resistor VR2 is formed at the same time as the via contact electrode CS. Therefore, the number of manufacturing processes can be reduced as compared with the manufacturing method of the semiconductor storage device according to the first embodiment.
Next, a semiconductor storage device according to a third embodiment will be described.
The semiconductor storage device according to the third embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, the semiconductor storage device according to the third embodiment includes the via resistors VR2 (see
Next, a method of manufacturing the semiconductor storage device according to the third embodiment will be described.
In manufacturing the semiconductor storage device according to the present embodiment, first, among the processes in the method for manufacturing the semiconductor storage device according to the second embodiment, the processes up to the process described with reference to FIG. 34 are performed.
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, as shown in
After that, the semiconductor storage device according to the third embodiment is formed by forming wiring and the like and dividing the wafer by dicing.
According to the semiconductor storage device according to the third embodiment, it is possible to reduce the circuit area and implement resistance elements having suitable characteristics, similarly to the semiconductor storage device according to the first embodiment.
According to the semiconductor storage device according to the third embodiment, it is possible to simultaneously form the via resistors VR and VR2 having two resistance values. Thereby, the circuit area can be further reduced.
[Structure of Memory Die MD4]
Next, a semiconductor storage device according to a fourth embodiment will be described with reference to
The memory die MD4 includes a semiconductor substrate 400, for example, as shown in
As shown in
[Structure of Semiconductor Substrate 400]
The semiconductor substrate 400 is configured in almost the same manner as the semiconductor substrate 100 (see
[Structure of Transistor Layer LTR]
The transistor layer LTR is configured in almost the same manner as the row decoder region RRD and the peripheral circuit region RP of the device layer DLL of the memory die MD (see
Each via contact electrode CS′ extends along the Z direction and is connected to the upper surface of the semiconductor substrate 400 or the electrode gc at the lower end thereof. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CS′ and the semiconductor substrate 400. The via contact electrode CS′ may include, for example, a barrier conductive film made of, for example, titanium nitride (TiN) and a stacked metal film made of, for example, tungsten (W).
[Structure of Wiring Layers D0, D1, and D2]
For example, as shown in
The wiring layers D0, D1, and D2 include a plurality of wirings d0, d1, and d2, respectively. Each of the plurality of wirings d0, d1, and d2 may include, for example, a barrier conductive film made of, for example, titanium nitride (TiN) and a stacked metal film made of, for example, tungsten (W).
[Structure of Memory Cell Array Layers LMCA1 and LMCA2 in Memory Hole Region RMH]
The structure of the memory cell array layers LMCA1 and LMCA2 in the memory hole region RMH is almost the same as the structure of the device layers DLL and DLU of the memory die MD (see
However, as shown in
For example, as shown in
[Structure of Memory Cell Array Layers LMCA1 and LMCA2 in Contact Connection Region RC4T]
The contact connection regions RC4T of the memory cell array layers LMCA1 and LMCA2 include, for example, a plurality of insulating layers 110A arranged along the Z direction and a plurality of via contact electrodes C4 extending along the Z direction, as shown in
A plurality of via contact electrodes C4 are arranged along the X direction. Each via contact electrode C4 may include a barrier conductive film made of, for example, titanium nitride (TiN) and a stacked metal film made of, for example, tungsten (W). The outer peripheral surface of the via contact electrode C4 is surrounded by the insulating layers 110A and the insulating layers 101 and is connected to the insulating layers 110A and the insulating layers 101. As shown in
[Structure in Hookup Region RHU′ of Memory Cell Array Layers LMCA1 and LMCA2]
The structure in the hookup Region RHU′ of the memory cell array layers LMCA1 and LMCA2 is almost the same as the structure of the hookup area RHU′ of the device layers DLL and DLU of the memory die MD (
[Via Resistors VR4]A plurality of via resistors VR4 are provided in any region of the memory die MD4. Each via resistor VR4 extends along the Z direction, for example, as shown in
The via resistor VR4 includes a resistor region VR4L in the memory cell array layer LMCA1 and a resistor region VR4U in the memory cell array layer LMCA2. The via resistor VR4 includes a resistor region VR4J connected to the upper end of the resistor region VR4L and the lower end of the resistor region VR4U.
The resistor region VR4L is a substantially columnar region extending along the Z direction. The outer peripheral surface of the resistor region VR4L is surrounded by the insulating layer 102 in the memory cell array layer LMCA1. The radial width WVR4LL of the lower end portion of the resistor region VR4L (for example, the portion located below the plurality of conductive layers 110 in the memory cell array layer LMCA1) is smaller than the radial width WVR4LU of the upper end portion of the resistor region VR4L (for example, the portion located above the plurality of conductive layers 110 in the memory cell array layer LMCA1).
The resistor region VR4U is a substantially columnar region extending along the Z direction. The outer peripheral surface of the resistor region VR4U is surrounded by the insulating layer 102 in the memory cell array layer LMCA2. The radial width WVR4UL of the lower end portion of the resistor region VR4U (for example, the portion located below the plurality of conductive layers 110 in the memory cell array layer LMCA2) is smaller than the radial width WVR4UU of the upper end portion of the resistor region VR4U (for example, the portion located above the plurality of conductive layers 110 in the memory cell array layer LMCA2) and the above-described width WVR4LU.
Each resistor region VR4J is provided above the plurality of conductive layers 110 in the memory cell array layer LMCA1 in the Z direction and below the plurality of conductive layers 110 in the memory cell array layer LMCA2 in the Z direction. The radial width WVR4J of the resistor region VR4J is larger than the widths WVR4LU and WVR4UU.
[Manufacturing Method]
Next, a method of manufacturing the semiconductor storage device according to the fourth embodiment will be described with reference to
In manufacturing the semiconductor storage device according to the present embodiment, first, the transistor layer LTR and the wiring layers D0 to D2 described with reference to
Next, for example, as shown in
Next, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the process described with reference to
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, as shown in
After that, for example, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the processes described with reference to
[Effect]
According to the semiconductor storage device according to the fourth embodiment, it is possible to reduce the circuit area and implement resistance elements having suitable characteristics, similarly to the semiconductor storage device according to the first embodiment.
Next, a semiconductor storage device according to a fifth embodiment will be described with reference to
The semiconductor storage device according to the fifth embodiment is basically configured in the same manner as the semiconductor storage device according to the fourth embodiment. However, the semiconductor storage device according to the fifth embodiment includes via resistors VR5 instead of the via resistors VR4.
Each via resistor VR5 extends along the Z direction. The lower end of the via resistor VR5 is connected to the semiconductor layer 423. The upper end of the via resistor VR5 is connected to the wiring m0.
The via resistor VR5 includes a resistor region VR5L in the memory cell array layer LMCA1 and the conductor region VC in the memory cell array layer LMCA2. The via resistor VR5 includes a resistor region VR5J connected to the upper end of the resistor region VR5L and the lower end of the conductor region VC. The resistor region VR5L and the resistor region VR5J may include, for example, a semiconductor layer made of, for example, silicon (Si) containing N-type impurities or P-type impurities.
The resistor region VR5L is a substantially columnar region extending along the Z direction. The outer peripheral surface of the resistor region VR5L is surrounded by the insulating layer 102 in the memory cell array layer LMCA1. The radial width WVR5LL of the lower end portion of the resistor region VR5L (for example, the portion located below the plurality of conductive layers 110 in the memory cell array layer LMCA1) is smaller than the radial width WVR5LU of the upper end portion of the resistor region VR5L (for example, the portion located above the plurality of conductive layers 110 in the memory cell array layer LMCA1) .
Each of the resistor regions VR5J is provided above the plurality of conductive layers 110 in the memory cell array layer LMCA1 in the Z direction and below the plurality of conductive layers 110 in the memory cell array layer LMCA2 in the Z direction. The radial width WVR5J of the resistor region VR5J is larger than the above-described widths WVRLU and WVCUU.
Next, a method of manufacturing the semiconductor storage device according to the fifth embodiment will be described with reference to
In manufacturing the semiconductor storage device according to the present embodiment, first, among the processes in the method for manufacturing the semiconductor storage device according to the fourth embodiment, the processes described with reference to
Next, for example, as shown in
Next, for example, as shown in
Next, for example, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the processes described with reference to
Next, for example, as shown in
Next, the via contact electrodes C4, CC, and the like described with reference to
After that, other wirings or the like is formed and the wafer is divided by dicing to form the semiconductor storage device according to the fifth embodiment.
According to the semiconductor storage device according to the fifth embodiment, it is possible to reduce the circuit area and implement resistance elements having suitable characteristics, similarly to the semiconductor storage device according to the fourth embodiment.
In the method for manufacturing a semiconductor storage device according to the fifth embodiment, the amorphous silicon film 120A used as a sacrificial film is used as the resistor region VR5L and the resistor region VR5J of the via resistor VR5, and the conductor region VC of the via resistor VR5 is formed at the same time as the other via contact electrodes. Therefore, the number of manufacturing processes can be reduced as compared with the manufacturing method of the semiconductor storage device according to the fourth embodiment.
Next, a semiconductor storage device according to a sixth embodiment will be described.
The semiconductor storage device according to the sixth embodiment is basically configured in the same manner as the semiconductor storage device according to the fourth embodiment. However, the semiconductor storage device according to the sixth embodiment includes the via resistors VR5 (see
Next, a method of manufacturing the semiconductor storage device according to the sixth embodiment will be described.
In manufacturing the semiconductor storage device according to the present embodiment, first, among the processes in the method for manufacturing the semiconductor storage device according to the fourth embodiment, the processes described with reference to
Next, for example, as shown in
Next, for example, as shown in
Next, for example, as shown in
Next, among the processes in the method for manufacturing the semiconductor storage device according to the fourth embodiment, the processes described with reference to
Next, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the processes described with reference to
After that, among the processes in the method for manufacturing the semiconductor storage device according to the fifth embodiment, the processes after the process described with reference to
According to the semiconductor storage device according to the sixth embodiment, it is possible to reduce the circuit area and implement resistance elements having suitable characteristics, similarly to the semiconductor storage device according to the fourth embodiment.
According to the semiconductor storage device according to the sixth embodiment, it is possible to simultaneously adopt via resistors VR4 and VR5 having two resistance values. Thereby, the circuit area can be further reduced.
Next, a semiconductor storage device according to a seventh embodiment will be described with reference to
The semiconductor storage device according to the seventh embodiment is basically configured in the same manner as the semiconductor storage device according to the first to third embodiments. However, the semiconductor storage device according to the seventh embodiment includes two device layers DLL and DLU arranged along the Z direction, and one device layer DLM provided therebetween. The semiconductor storage device includes three types of via resistors VR″, VR2″, and VR3″ instead of the via resistors VR and VR2. The semiconductor storage device includes a via contact electrode CS″ instead of the via contact electrode CS.
The via resistor VR″ includes a resistor region VRL in the device layer DLL, a resistor region VRM in the device layer DLM, and a resistor region VRU in the device layer DLU. The via resistor VR″ includes a resistor region VRJ connected to the upper end of the resistor region VRL and the lower end of the resistor region VRM, and a resistor region VRJ connected to the upper end of the resistor region VRM and the lower end of the resistor region VRU. The resistor region VRM is configured in the same manner as the resistor regions VRL and VRU.
The via resistor VR2″ includes a resistor region VRL in the device layer DLL, a resistor region VRM in the device layer DLM, and a conductor region CSU in the device layer DLU. The via resistor VR2″ includes a resistor region VRJ connected to the upper end of the resistor region VRL and the lower end of the resistor region VRM, and a resistor region VRJ connected to the upper end of the resistor region VRM and the lower end of the conductor region CSU.
The via resistor VR3″ includes a resistor region VRL in the device layer DLL, a conductor region CSM in the device layer DLM, and a conductor region CSU in the device layer DLU. The via resistor VR3″ includes a resistor region VRJ connected to the upper end of the resistor region VRL and the lower end of the conductor region CSM, and a conductor region CSJ connected to the upper end of the conductor region CSM and the lower end of the conductor region CSU. The conductor region CSM is configured in the same manner as the conductor regions CSL and CSU. The via resistor VR3″ includes an insulating layer VRE made of, for example, silicon nitride (Si3N4) provided on the upper surface of the resistor region VRJ. The insulating layer VRE covers the outer peripheral surface of the lower end of the conductor region CSM.
The via contact electrode CS″ includes a conductor region CSL in the device layer DLL, a conductor region CSM in the device layer DLM, and a conductor region CSU in the device layer DLU. The via contact electrode CS″ includes a conductor region CSJ connected to the upper end of the conductor region CSL and the lower end of the conductor region CSM, and a conductor region CSJ connected to the upper end of the conductor region CSM and the lower end of the conductor region CSU.
Next, a method of manufacturing the semiconductor storage device according to the seventh embodiment will be described with reference to
In manufacturing the semiconductor storage device according to the present embodiment, first, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the processes up to the process described with reference to
Next, as shown in
Next, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the processes described with reference to
Next, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the processes described with reference to
Next, among the processes in the method for manufacturing the semiconductor storage device according to the first embodiment, the processes described with reference to
Next, as shown in
Next, for example, as shown in
Next, as shown in
Next, for example, as shown in
Next, as shown in
Next, for example, as shown in
Next, as shown in
Next, as shown in
After that, the semiconductor storage device according to the seventh embodiment is formed by forming wirings and the like and dividing the wafer by dicing.
The semiconductor storage devices according to the first to seventh embodiments have been described above.
However, the semiconductor storage devices according to the embodiments are merely examples, and specific configurations, operations, and the like can be appropriately adjusted.
For example, the via resistors VR, VR2, VR4, VR5, VR″, VR2″, and VR3″ according to the first to seventh embodiments include resistor regions VRJ, VR2J, VR4J, and VR5J. However, it is also possible to omit the resistor regions VRJ, VR2J, VR4J, and VR5J from the via resistors VR, VR2, VR4, VR5, VR″, VR2″, and VR3″. In such a case, for example, the processes described with reference to
For example, the outer peripheral surfaces of the via resistors VR4 and VR5 according to the fourth to sixth embodiments are surrounded by the insulating layer 102. However, the outer peripheral surfaces of the via resistors VR4 and VR5 may be surrounded by the plurality of insulating layers 110A and the plurality of insulating layers 101, for example, as shown in
For example, the semiconductor storage device according to the seventh embodiment basically has the same configuration as the semiconductor storage device according to the first to third embodiments. The semiconductor storage device includes three device layers DLL, DLM, and DLU arranged along the Z direction. As described above, the semiconductor storage device according to the first to third embodiments may include three or more device layers. Via resistors having three or more different resistance values may be provided. Similarly, the semiconductor storage device according to the fourth to sixth embodiments may include three or more memory cell array layers. Via resistors having three or more different resistance values may be provided.
The via resistors according to the first to seventh embodiments can be applied to various circuits.
For example,
For example,
[Others]
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
Number | Date | Country | Kind |
---|---|---|---|
2021-033948 | Mar 2021 | JP | national |