Patent Application
20250022749
This application claims the benefit of priority of Chinese patent application with the application No. 202210814687.7, entitled “Semiconductor Structure And Method For Fabricating The Same”, filed on Jul. 12, 2022 with the China Patent Office, the contents of which are incorporated herein by reference in its entirety.
The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for preparing the semiconductor structure.
Dynamic Random Access Memory (DRAM for short) is a commonly used semiconductor storage device, which includes multiple repeated storage units. Each memory cell generally includes a transistor and a capacitor. The gate of the transistor is connected to a word line (WL), the drain is connected to a bit line (BL), and the source is connected to the capacitor.
A conductive connection structure is provided in the DRAM memory, and the conductive connection structure may be a metal interconnection structure or a contact plug structure. Wherein, the metal interconnection structure is used for connecting signal lines of different storage units, or used for connecting different conductive layers in the storage units. In order to adapt to the continuous shrinking of the size of the DRAM memory, the size of the conductive connection structures in the related art and the distance between adjacent conductive connection structures are correspondingly reduced continuously.
However, the parasitic capacitance of the conductive connection structure in the above solution is relatively large, resulting in serious capacitance resistance (RC) delay, which affects the storage performance of the DRAM memory.
In a first embodiment, the present application provides a semiconductor structure, having a conductive layer. There is a hole in the conductive layer. The inner wall of the hole is covered with a first dielectric layer. The thickness of the first dielectric layer on the side of the hole near the hole is greater than that away from the hole. The thickness of the first dielectric layer on the side of the mouth; the first dielectric layer on the side close to the orifice is covered with a second dielectric layer, and the second dielectric layer blocks the orifice:
Air gaps are formed in the first dielectric layer and the second dielectric layer, and the size of the air gap on the side away from the orifice is larger than the size of the air gap on the side close to the orifice.
In a second embodiment, the present application provides a method for preparing a semiconductor structure, including:
Air gaps are formed in the first dielectric layer and the second dielectric layer, wherein the size of the air gaps on the side away from the orifice is larger than the size of the air gaps on the side close to the orifice.
The inventors of the present application learned in their experiments that the DRAM memory includes multiple repetitive storage units to realize the storage function. The DRAM memory includes conductive connection structure, and the conductive connection structure may be a metal interconnection structure or a contact plug structure. Wherein, the metal interconnection structure is used to connect signal lines of different storage units, and the contact plug connects different conductive layers in the storage unit. With the improvement of the integration level of DRAM memory, the size of DRAM memory keeps shrinking, and the size of conductive connection structures and the distance between adjacent conductive connection structures are correspondingly reduced continuously.
However, the parasitic capacitance of the conductive connection structure after shrinking in size is relatively large, resulting in serious capacitance resistance (RC) delay, which affects the storage performance of the DRAM memory. In the related art, the problem of adjusting the parasitic capacitance of the conductive connection structure is solved by reducing the resistance of the conductive connection structure or changing the filling medium in the conductive connection structure. In process of reducing the resistance of the conductive connection structure, it is difficult to adjust parameters related to resistance such as the material and cross-sectional area of the conductive connection structure in the DRAM memory.
Therefore, changing the filling medium in the conductive connection structure can be a means to adjust its parasitic capacitance, this technique is based on the low dielectric constant of air (dry air dielectric constant is 2.1). Based on this fact, adjusting the air gap structure in the conductive connection structure by increasing the size of the air gap and increasing the amount of air fill can be some effective method to reduce the parasitic capacitance of the conductive connection structure.
In view of this, in the semiconductor structure and the method for preparing the semiconductor structure according to the embodiments of the present application, in the semiconductor structure, by providing a conductive layer with holes, the conductive layer can transmit signals, so as to realize the conductive connection function of the semiconductor structure. The air pores in the layer can form subsequent air gaps. By arranging the first dielectric layer and the second dielectric layer on the inner wall of the channel, the second dielectric layer seals the orifice to form an air gap in the first dielectric layer and the second dielectric layer. By making the thickness of the first dielectric layer near the orifice side of the channel larger than the thickness of the first dielectric layer on the side away from the orifice, the size of the air gap on the side away from the orifice is larger than that on the side near the orifice. In addition, in the semiconductor manufacturing method, the blocking layer is used for mask etching to remove part of the thickness of the first dielectric layer, so that the thickness of at least part of the second dielectric layer on the side away from the hole is smaller. In this way, the size of the air gap in the semiconductor structure can be effectively increased, and the filled amount of air in the air gap can be increased, thereby alleviating the problems of parasitic capacitance and RC delay of the semiconductor structure. When the semiconductor structure is applied to a memory, it can also be optimized accordingly memory storage performance.
To further clarify the goal, technical solutions and advantages of the present application, the embodiments of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the application. The embodiments described below by referring to the figures are exemplary, and are intended to explain the present application, and should not be construed as limiting the present application. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application. Embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.
An air gap 102 is formed in the first dielectric layer 200 and the second dielectric layer 300, and the size of the air gap 102 on the side away from the orifice 101a is larger than the size of the air gap 102 on the side close to the orifice 101a.
It should be noted that the semiconductor structure according to the present application may be an interconnection structure (such as a metal interconnection line) or a plug structure (such as a metal plug). When the semiconductor structure is applied to a memory, signal lines between different storage units in the memory can usually be connected through the interconnection structure, so as to realize signal transmission of multiple storage units. Alternatively, the capacitor in the storage unit is arranged above the transistor, and a plug structure is arranged between the transistor and the capacitor for connecting the capacitor to the drain of the transistor. In other embodiments, the semiconductor structure can also be used for other connection requirements, which is not limited in this embodiment.
Wherein, the conductive layer 100 may be a metal aluminum layer, or a metal copper layer. The holes 101 of the conductive layer 100 can be formed by mask etching. The first dielectric layer 200 formed in the channel 101 may be located on the side wall and the bottom wall of the channel 101. The first dielectric layer 200 can be formed by deposition, for example, chemical vapor deposition (CVD for short). In the process based on chemical vapor deposition, when the deposited layer is thick, the problem of step coverage becomes more obvious. In the embodiment of the present application, by virtue of the characteristics of the chemical vapor deposition process, in the process of forming the first dielectric layer 200, compared with the deposition rate of the first dielectric layer 200 on the side away from the orifice 101a of the channel 101, the deposition rate of the first dielectric layer 200 on the side of the orifice 101a is relatively large, so are the pores near the channel 101. Therefore, the thickness of the formed first dielectric layer 200 is not equal to that at the position away from the orifice 101a and near the orifice 101a, specifically, the thickness of the first dielectric layer 200 near the orifice 101a side of the channel 101 is greater than the thickness of the first dielectric layer 200 on the side away from the orifice 101a.
In this way, the first dielectric layer 200 near the orifice 101a can form an “overhang structure (overhang)”.
It should be explained that the concept of “dimension” in the embodiment of the present application may refer to the extension length of the channel 101 along the direction perpendicular to the direction approaching and away from the orifice 101a in the cross-sectional view of
The first dielectric layer 200 near the orifice 101a is covered with a second dielectric layer 300, and the second dielectric layer 300 blocks the orifice 101a. Wherein, based on the thickness of the first dielectric layer 200 on the side close to the orifice 101a is relatively large, the second dielectric layer 300 covering the first dielectric layer 200 close to the orifice 101a can block the orifice 101a to ensure that A structurally stable air gap 102 is formed in the channel 101. The air gap 102 may be filled with dry air, and the semiconductor structure of the present application may be completed in an environment of dry air during the manufacturing process, and the prepared air gap 102 is naturally filled with dry air. The dielectric constant of the semiconductor structure can be adjusted by using dry air to reduce its parasitic capacitance, thereby effectively alleviating the problem of RC delay and ensuring that when the semiconductor structure is applied to a memory, the storage performance of the memory is improved.
In the semiconductor structure of the present application, the first dielectric layer 200 may be a tetraethyl silicate layer (TEOS).
In some embodiments, the thickness of the second dielectric layer 300 on the side close to the orifice 101a is greater than the thickness of the second dielectric layer 300 on the side away from the orifice 101a. The second dielectric layer 300 can be formed by a deposition process, and a thicker second dielectric layer 300 is formed on the side close to the orifice 101a, so that the second dielectric layer 300 on the side close to the orifice 101a can effectively block the orifice 101a, thereby forming a stable air gap 102 structure; and forming a thinner second dielectric layer 300 on the side away from the orifice 101a, so as to increase the size of the air gap 102 in the channel 101 and improve the filling of air in the air gap 102 The amount helps to alleviate the problem of large parasitic capacitance of the semiconductor structure.
Moreover, based on the fact that the first dielectric layer 200 and the second dielectric layer 300 have larger thicknesses on the side near the orifice 101a, the formed air gap 102 has a larger size on the side near the orifice 101a.
Wherein, the thickness of the second dielectric layer 300 gradually decreases along the direction away from the orifice 101a, and the size of the air gap 102 in the second dielectric layer 300 gradually increases along the direction away from the orifice 101a. Since the second dielectric layer 300 is formed through a deposition process, the step coverage of the deposition of the second dielectric layer 300 gradually changes along the direction away from the orifice 101a, so that the thickness of the second dielectric layer 300 will also gradually decrease, correspondingly, the size of the air gap 102 in the second dielectric layer 300 gradually increases, so that the flatness of the surface of the second dielectric layer 300 close to the air gap 102 can be effectively ensured to improve the structure of the second dielectric layer 300 Regularity.
Continuing to refer to
Specifically, the thickness range of the second part 202 in the embodiment of the present application is 5-10 nm.
In the present application, setting the thickness of the second part 202 on the side away from the orifice 101a to be smaller can effectively increase the size of the air gap 102, thereby increasing the air filling amount in the air gap 102. Therefore, the thickness of the second part 202 is reduced, which helps to adjust the parasitic capacitance of the semiconductor structure. However, when the thickness of the second part 202 is too small, the anti-interference ability of the electrical signal of the semiconductor structure is reduced. When a semiconductor structure is applied to a memory, as the size of the memory decreases, the distance between two adjacent semiconductor structures decreases, and electrical signal interference between them will affect their own signal transmission. Therefore, it is necessary to ensure that the second dielectric layer 300 has a certain thickness in the semiconductor structure, so as to ensure the anti-interference ability of the electrical signal of the semiconductor structure. In some feasible embodiments, the thickness of the second part 202 may be 6 nm, 7 nm or 8 nm, and the specific value of the thickness of the second part 202 is not limited in this embodiment.
Based on the above-mentioned first dielectric layer 200 including the first part 201 and the second part 202, the second dielectric layer 300 can be covered on the first part 201, so that the second dielectric layer 300 is arranged closer to the orifice 101a, so as to plug the hole Mouth 101a. Based on the fact that the thickness of the first part 201 is greater than that of the second part 202, and the first part 201 is also covered with the second dielectric layer 300, therefore, the size of the air gap 102 in the second part 202 is larger than that of the air gap in the first part 201. The size of the gap 102. In this way, the position where the air gap 102 is larger is far from the position of the orifice 101a, which can ensure the structural stability of the air gap 102 and the position of the orifice 101a. Wherein, the size of the air gap 102 formed in the second part 202 can be the part shown in c in FIG. a and b.
Specifically, the thickness of the first part 201 near the orifice 101a is greater than the thickness of the first part 201 away from the orifice 101a; and, the thickness of the first part 201 gradually decreases along the direction away from the orifice 101a. Since the first dielectric layer 200 is formed by a chemical vapor deposition process, the first part 201 of the first dielectric layer 200 is also affected by the step coverage, so that the thickness of the side near the orifice 101a is greater than the thickness of the side away from the orifice 101a. The thickness of the first part 201 gradually decreases along the direction away from the orifice 101a, which can also ensure the surface smoothness of the first dielectric layer 200 near the orifice 101a.
Referring to
Based on the above descriptions of the first part 201 and the second part 202, this application sets the first dielectric layer 200 near the middle of the channel 101 in the semiconductor structure to be thinner (that is, the thickness of the second part 202 is smaller), which can effectively enlarge the size of the air gap 102 to avoid affecting the structural stability of the semiconductor structure. The first dielectric layer 200 near the orifice 101a and the bottom of the hole is set thicker (that is, the thickness of the first part 201 and the third part 203 is relatively large), which can effectively improve the structural stability and electrical performance stability of the semiconductor structure.
As a realizable implementation, the materials of the first dielectric layer 200 and the second dielectric layer 300 in this application can be the same, which can reduce the difficulty of manufacturing the semiconductor structure and ensure the interfacial stability of the contact surface between the first dielectric layer 200 and the second dielectric layer 300. Materials for both include silicon oxide and/or germanium oxide.
In the semiconductor structure of the present application, a third dielectric layer 400 may be further included. The third dielectric layer 400 is located outside the channel 101, and the third dielectric layer 400 covers the conductive layer 100 near the orifice 101a. The third dielectric layer 400 may be a titanium nitride layer.
As some realizable implementations, at least part of the first dielectric layer 200 is located outside the channel 101, and the first dielectric layer 200 located outside the channel 101 covers the third dielectric layer 400.
At least part of the second dielectric layer 300 is located outside the channel 101, and the second dielectric layer 300 located outside the channel 101 covers the first dielectric layer 200. The top surface of the first dielectric layer 200 outside the channel 101 may be flat, which facilitates the installation of the second dielectric layer 300 outside the channel 101 and ensures the stability of the second dielectric layer 300.
FIG. illustrates a schematic flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present application. Referring to
S100: provide a conductive layer with a channel. As shown in
S200: form a first dielectric layer, the first dielectric layer covers at least the inner wall of the channel, and the thickness of the first dielectric layer at the side close to the orifice of the channel is greater than the thickness of the first dielectric layer at the side away from the orifice. As shown in
It should be noted that the chemical vapor deposition process has the characteristics of step coverage when the deposition thickness is relatively large, so this application can apploes this characteristic to arrange the thickness of the first dielectric layer 200 formed on the side close to the orifice 101a relatively large, and the thickness of the first dielectric layer 200 on the side away from the orifice 101a relatively small.
Wherein, the first dielectric layer 200 includes a first part 201 near the hole 101a and a third part 203 at the bottom of the hole 101. During the deposition process of the first dielectric layer 200, the position of the orifice 101a is closer to the deposition evaporation source relative to the bottom of the hole, so the formed first part 201 near the orifice 101a will appear close. The thickness of the first part 201 on the side of the orifice 101a is greater than the thickness of the first part 201 on the side away from the orifice 101a. In
Also, the thickness of the first part 201 gradually decreases in a direction away from the orifice 101a. In this way, the flatness of the surface of the first part 201 close to the air gap 102 can be ensured.
In the direction along the plane where the bottom of the hole is located, the third parts 203 may be evenly distributed, that is, the thicknesses of the third parts 203 at each position of the bottom of the hole may be substantially equal.
S300: form a barrier layer, and the barrier layer covers at least the first dielectric layer on the side close to the opening of the channel.
The barrier layer 500 is formed through a physical vapor deposition process. The physical vapor deposition process (Physical Vapor Deposition, referred to as PVD) has obvious characteristics of step coverage. In this application, the step coverage difference of the physical vapor deposition process is used to make the thickness of the barrier layer 500 near the hole 101a larger than the thickness of the barrier layer 500 away from the hole 101a.
The barrier layer 500 may cover the first dielectric layer 200 close to the opening 101a, that is, the first part 201. Based on the thickness of the first part 201 on the side near the orifice 101a, it is greater than the thickness of the first part 201 on the side away from the orifice 101a, and the thickness of the barrier layer 500 is larger on the side near the orifice 101a, and is far from the side of the orifice 101a. The thickness is smaller. Therefore, after the barrier layer 500 is formed, the size of the channels 101 on the side close to the orifice 101a is smaller than the size of the channels 101 on the side away from the orifice 101a. The barrier layer 500 can effectively protect the first dielectric layer 200 near the orifice 101a, and avoid affecting the thickness of the first dielectric layer 200 on the side near the orifice 101a in the subsequent process of removing part of the thickness of the first dielectric layer 200, so as to effectively prevent subsequent steps from enlarging the size of the orifice 101a of the channel 101 and ensure the stability of the formed air gap 102 structure.
As a possible implementation, the thickness of the barrier layer 500 gradually decreases along the direction away from the orifice 101a. Since the barrier layer 500 is formed by deposition, the thickness gradually decreases along the direction away from the orifice 101a, which can ensure the smoothness of the wall surface of the barrier layer 500 near the channel 101.
In the embodiment of the present application, the material of the barrier layer 500 may include but not limited to titanium nitride. The material of the barrier layer 500 can be selected from a material different from that of the first dielectric layer 200, and the selective etching ratio of the two for the same chemical etching solution is different, so as to facilitate the subsequent removal of part of the thickness of the first dielectric layer 200 and the removal of the barrier layer 500 and so on.
Referring to
After the barrier layer 500 is formed, the method further includes: S400: remove a part of the thickness of the first dielectric layer not covered by the barrier layer. Referring to
As a realizable implementation manner, removing the part of the thickness of the first dielectric layer 200 not covered by the barrier layer 500 includes: using the first etchant to remove the part of the thickness not covered by the barrier layer 500 through a chemical etching process. For the first dielectric layer 200, the selective etching ratio of the first etchant to the barrier layer 500 and the first dielectric layer 200 is 1:10.
Wherein, the first etching solution is hydrofluoric acid solution (DHF). In the hydrofluoric acid solution, the ratio of hydrofluoric acid to water ranges from 200:1 to 300:1, and the etching process time of the first etching solution is 100-140 s. In this embodiment, the first etching solution The etching process time can be 110 s, 120 s or 130 s.
Specifically, removing the partial thickness of the first dielectric layer 200 not covered by the barrier layer 500 includes: removing the partial thickness of the first dielectric layer 200 in the first dielectric layer 200 except for the first part 201 and the third part 203, And form the second part 202 of the first dielectric layer 200. Wherein, the thicknesses of the first part 201 and the third part 203 are both greater than the thickness of the second part 202.
It should be noted that, after removing part of the thickness of the first dielectric layer 200, the remaining thickness of the first dielectric layer 200 may be the part shown in d in
And, after being positioned at the first dielectric layer 200 of partial thickness of channel 101 sidewalls to be removed, expose the first dielectric layer 200 of hole channel 101 hole bottoms, therefore be positioned at hole bottom place and be close to the partial thickness of channel 101 sidewalls second dielectric layer 300 is also removed, thereby forming the structure shown in part B of
The inventor found in the course of research that, compared with the semiconductor structure in which no barrier layer 500 is provided and part of the thickness of the first dielectric layer 200 is not removed, the present application sets the barrier layer 500 and removes part of the thickness of the first dielectric layer 200 After that, the size of the air gap 102 in the semiconductor structure can be increased by about 200%, and the parasitic capacitance of the semiconductor structure can be reduced by about 27%.
After removing part of the thickness of the first dielectric layer 200, the method may further include: S500: remove the barrier layer.
As an achievable implementation manner, removing the barrier layer 500 includes: removing the barrier layer 500 through a chemical etching process using a second etchant, and selectively etching the barrier layer 500 and the first dielectric layer 200 by the second etchant. The eclipse ratio is 12:1. Wherein, the second etching solution is a mixture of ammonia, hydrogen peroxide and water (SCI), wherein the ratio of ammonia, hydrogen peroxide and water is 1:4:130, and the etching process time of the second etching solution is 40-80 s. In this embodiment, the etching process time of the second etching solution may be 50 s, 55 s or 60 s.
After the barrier layer 500 is removed, the method further includes: S600: form a second dielectric layer, the second dielectric layer covers at least the first dielectric layer at the side close to the orifice, and blocks the orifice of the channel.
Wherein, air gaps 102 are formed in the first dielectric layer 200 and the second dielectric layer 300, and the size of the air gaps 102 on the side away from the orifice 101a is larger than the size of the air gaps 102 on the side close to the orifice 101a.
As shown in
Wherein, the size of the air gap 102 on the side away from the orifice 101a is larger than the size of the air gap 102 close to the orifice 101a, which can effectively ensure the stability of the structure of the orifice 101a, and avoid the position of the orifice 101a. The second dielectric layer 300 or the first dielectric layer 200 is damaged and can help to improve the stability of the electrical properties of the semiconductor structure.
In some embodiments, before forming the first dielectric layer 200, further includes:
forming a third dielectric layer 400, the third dielectric layer 400 is located outside the channel 101 and covers the conductive layer 100 near the orifice 101a:
Wherein, at least part of the first dielectric layer 200 is located outside the channel 101, and the first dielectric layer 200 located outside the channel 101 covers the third dielectric layer 400.
It should be noted that the third dielectric layer 400 may be formed on the top surface of the conductive layer 100 without the holes 101, and part of the third dielectric layer 400 and part of the thickness of the conductive layer 100 are removed by etching, so that the conductive layer A channel 101 is formed in 100. Alternatively, it can be completed after forming the conductive layer 100 with the holes 101, and the third dielectric layer 400 only covers the top surface of the conductive layer 100 and does not fill the holes 101.
The top surface of the first dielectric layer 200 located outside the channel 101 may be a plane, which may facilitate subsequent setting of the second dielectric layer 300 located outside the channel 101.
Specifically, the barrier layer 500 is formed, including:
At least part of the barrier layer 500 is located outside the channel 101, and the barrier layer 500 located outside the channel 101 covers the first dielectric layer 200. In this way, it can be effectively ensured that the first etching solution is prevented from contacting the third dielectric layer 400 outside the channel 101 during the process of removing part of the thickness of the first dielectric layer 200, so as to ensure the stability of the semiconductor structure. The barrier layer 500 outside the channel 101 can be formed by simultaneous deposition with the barrier layer 500 inside the channel 101.
Wherein, at least part of the second dielectric layer 300 is located outside the channel 101, and the second dielectric layer 300 located outside the channel 101 covers the first dielectric layer 200. In this way, it can be ensured that the second dielectric layer 300 completely blocks the opening 101a to ensure the structural stability of the air gap 102, and the second dielectric layer 300 can also protect the third dielectric layer 400. Similarly, the second dielectric layer 300 outside the channel 101 and the second dielectric layer 300 inside the channel 101 can be formed by simultaneous deposition.
In a third embodiment, the embodiment of the present application further provides a memory, including the above-mentioned semiconductor structure. The memories provided herein may be memory devices or non-memory devices. The storage device may include, for example, a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a flash memory, an Electrically Erasable Programmable Read Only Memory (EEPROM), phase change random access memory (PRAM) or magnetoresistive random access memory (MRAM). A non-memory device may be a logic device such as a microprocessor, digital signal processor, or microcontroller, or the like. The embodiment of the present application is described by taking a DRAM storage device as an example.
The foregoing semiconductor structure may be an interconnection structure or a plug structure in a three-dimensional DRAM storage device, which is not limited in this embodiment. Other technical features of the memory of the present application are the same as those of the embodiments of the above-mentioned semiconductor structure, and can achieve the same technical effect, and will not be repeated here.
It should be noted that the term “layer” used herein may refer to a material portion including a region with a certain thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of transverse planes at the top and bottom surfaces. Layers may extend laterally, vertically and/or along the tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above, and/or below. Layers may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
In the above description, it should be understood that, unless otherwise clearly stipulated and limited, the terms “installation”. “connection” and “connection” should be interpreted in a broad sense, for example, it can be fixed connection or indirect connection through an intermediary. Connected can be the internal communication of two elements or the interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations. The orientation or positional relationship indicated by the terms “upper”, “lower”, “front”, “rear”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” etc. is based on The orientation or positional relationship shown in the drawings is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as Limitations on this Application. In the description of the present application, “plurality” means two or more, unless otherwise specified precisely.
The terms “first”, “second”, “third”, “fourth”, etc. (if any) in the description and claims of this application and the above drawings are used to distinguish similar objects, and not necessarily Used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein, for example, can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms “comprising” and “having”, as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit it: although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the various embodiments of the application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210814687.7 | Jul 2022 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/107192 | 7/21/2022 | WO |
