Patent Application
20200211964
The disclosure relates to semiconductor technologies, and more particularly to a semiconductor device having a conductive feature and a method for manufacturing the same.
Since laterally diffused metal oxide semiconductors (LDMOSs) have high operating efficiency and good gain characteristics and are easy to integrate with other circuitry, the LDMOS has become a semiconductor component that is often used in various electronic products.
However, since the LDMOS has a conductive feature connected to a source electrode and a conductive terminal of a substrate, the dopants of the conductive feature often diffuse to peripheral elements during subsequent processes (e.g. a high-temperature thermal process) to negatively affect the electrical properties of the LDMOS. In addition, when the size of an LDMOS is reduced, the impact of dopant diffusion from the conductive feature is more significant. Thus, the scaling down of the LDMOS is limited and the source-drain resistance (RDSON) cannot be reduced to enhance the performance of the LDMOS any further.
While existing LDMOSs have been generally adequate for their intended purposes, there are still many problems. Thus, how to improve the existing LDMOS has become one of the topics that the industry has paid much attention to.
In some embodiments of the present disclosure, a semiconductor structure is provided. The semiconductor structure comprises a substrate, an epitaxial layer disposed on the substrate, a conductive feature disposed in the epitaxial layer and having a protruding portion that is higher than the epitaxial layer, and a diffusion barrier layer disposed on sidewalls of the conductive feature. In one embodiment, the width of the protruding portion is greater than the width of the conductive feature in the epitaxial layer. In one embodiment, the protruding portion covers the top surface of the diffusion barrier layer. In one embodiment, the diffusion barrier layer includes one or more dielectric barrier layers. In one embodiment, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer on the barrier oxide layer.
In one embodiment, the semiconductor structure further includes a drain region disposed in the epitaxial layer, wherein the diffusion barrier layer contacts the drain region and separates the drain region from the conductive feature. In one embodiment, the conductive feature is disposed between two laterally diffused metal oxide semiconductors (LDMOSs) and the conductive feature penetrates a common source region of the LDMOSs.
In some embodiments of the present disclosure, a method for fabricating a semiconductor structure is provided, wherein the method includes providing a substrate; forming an epitaxial layer on the substrate; forming a mask structure on the epitaxial layer, and the mask structure has an opening exposing a portion of the epitaxial layer; using the mask structure as an etching mask to remove the exposed portion of the epitaxial layer to form a trench; forming a diffusion barrier layer on sidewalls of the trench; forming a conductive feature in the trench, and the conductive feature has a protruding portion that is higher than the epitaxial layer; and removing the mask structure.
In one embodiment, the width of the protruding portion is greater than the width of the conductive feature in the trench. In one embodiment, the protruding portion covers the top surface of the diffusion barrier layer. In one embodiment, the mask structure includes one or more dielectric layers. In one embodiment, the mask structure includes a first oxide layer and a nitride layer formed on the first oxide layer. In one embodiment, the mask structure further includes a second oxide layer formed on the nitride layer. In one embodiment, the mask structure includes multiple dielectric layers, and removing the mask structure includes: removing a portion of the mask structure without removing the layer of the multiple dielectric layers which is closest to the epitaxial layer; and removing the remaining portions of the mask structure after removing the portion of the mask structure.
In one embodiment, the diffusion barrier layer includes one or more dielectric barrier layers. In one embodiment, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer formed on the barrier oxide layer. In one embodiment, the method further includes forming a drain region in the epitaxial layer, wherein the diffusion barrier layer contacts the drain region and separates the drain region from the conductive feature. In one embodiment, the conductive feature is disposed between two laterally diffused metal oxide semiconductors (LDMOSs) and the conductive feature penetrates a common source region of the LDMOSs.
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with common practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as “over”, “below,” “lower,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Subsequently, an epitaxial layer 12 is formed on the substrate 10. In some embodiments, the formation of the epitaxial layer 12 includes performing an epitaxial growth process to form the epitaxial layer 12 on the substrate 10. In the present embodiment, the epitaxial layer 12 may be P-type. In some embodiments, the epitaxial growth process may be such as a metal organic chemical vapor deposition (MOCVD), a plasma-enhanced chemical vapor deposition (PECVD), a molecular beam epitaxy (MBE), a hydride vapor phase epitaxy (HVPE), a liquid phase epitaxy (LPE), a chloride vapor phase epitaxy (Cl-VPE).
Subsequently, a mask structure 14 is formed on the epitaxial layer 12. The mask structure 14 has an opening 15 exposing a portion of the epitaxial layer 12. In some embodiments, the mask structure 14 includes one or more dielectric layers. In this embodiment, the mask structure 14 is a first oxide layer. The thickness of the first oxide layer is in a range from about 2000 angstroms (Å) to about 5000 Å. The material of the first oxide layer may be made of, or include, silicon dioxide or another suitable oxides. For example, thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other similar processes may be used to form the first oxide layer. In some embodiments, the formation of the mask structure 14 includes forming a mask material on the epitaxial layer 12 and then patterning the mask material to form the mask structure 14.
Referring to
Furthermore, when removing the exposed epitaxial layer 12 to form the trench 18, the first oxide layer used as the etching mask is also partially consumed and thus becomes thinner. In some embodiments, before removing the exposed epitaxial layer 12 to form the trench 18, the thickness of the first oxide layer (e.g. the first oxide layer shown in
Referring to
In some embodiments shown in
Referring to
Referring to
It should be noted that the conductive feature 28 formed in the trench 18 is prone to forming a seam. When the height of the top surface of the conductive feature 28 is lower than or the same as the height of the top surface of the epitaxial layer 12, the seam will penetrate the top surface of the conductive feature 28 which causes erosion in subsequent cleaning steps, and leads to short-circuits and other problems in the subsequently formed circuitry. Thus, the conductive feature 28 with a protruding portion 30 that is higher than the epitaxial layer 12 in the present disclosure can prevent the seam in the conductive feature 28 from penetrating the top surface of the conductive feature 28 and further prevent problems from arising in the subsequent manufacturing processes. In an embodiment, the height of the protruding portion 30 is in a range from 200 Å to 800 Å.
Furthermore, the conductive feature 28 may be a P-type conductive feature. In some embodiments, the conductive feature 28 includes dopants. The dopants may be made of, or include, boron, gallium, indium, aluminum, or a combination thereof. It should be noted that since the diffusion barrier layer 20 provided in the present disclosure is disposed between the conductive feature 28 and the epitaxial layer 12, the diffusion barrier layer 20 can block the dopant diffusion from the conductive feature 28 to the periphery during subsequent processes (e.g. a high-temperature thermal process) and further prevent the electrical properties of peripheral elements from being impacted.
Furthermore, in general, when the size of the formed semiconductor structure 100 in
In some embodiments, a bottom surface of the trench 18 may be a planar bottom surface or a U-shaped bottom surface. When the bottom surface of the trench 18 is a U-shaped bottom surface, an area of a direct contact between the conductive feature 28 and the epitaxial layer 12 can be increased to enlarge a flux of operating current to enhance the performance of the semiconductor structure 100 formed in subsequent processes.
Referring to
It should be noted that the reference numerals and partial description of the following embodiments are the same as the above embodiments, wherein the same or similar reference numerals are used to represent the same or similar elements, and the description of the same technical features are omitted. For the description of the omitted part, reference may be made to the above embodiments without being described again.
Referring to
It should be noted that, in the embodiments shown in
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In some embodiments, since the etching selection ratio of the nitride layer 32a is greater than that of the first oxide layer 16a, the first oxide layer 16a can remain completely after removing the nitride layer 32a. Then, after removing the nitride layer 32a, the first oxide layer 16a is subsequently removed.
It should be noted that when the thickness of the first oxide layer 16a is in a range from about 300 Å to about 700 Å, an etching process with a short cycle time (e.g. about 10 seconds to about 30 seconds) may be performed to completely remove the first oxide layer 16a, in the embodiment. This etching process can remove the first oxide layer 16a completely and precisely, so the elements around the first oxide layer 16a may be undamaged by this etching process. In particular, the short cycle time of the etching process, which is between about 10 and 30 seconds, means that the etching process can be performed to completely remove the first oxide layer 16a and prevent over etching from damaging the diffusion barrier layer 20. Furthermore, the diffusion barrier layer 20 can remain intact and the dopant diffusion from the conductive feature 28 can be blocked effectively, and thereby the electrical properties of the peripheral elements may not be impacted.
In a specific embodiment, an etching process with hot phosphoric acid as an etchant may be performed on the nitride layer 32a for about 50 seconds to about 100 seconds to completely remove the nitride layer 32a. Subsequently, an etching process with hydrofluoric acid as an etchant is performed on the first oxide layer 16a for about 50 seconds to about 100 seconds to completely remove the first oxide layer 16a.
Referring to
It should be noted that, in the embodiments shown in
Referring to
In some embodiments, the height of the top surface of the protruding portion 30 is between the top surface and the bottom surface of the nitride layer 32b. Thus, when performing a wet etching to remove the nitride layer 32b, the second oxide layer 34 on the nitride layer 32b may be removed simultaneously. In addition, in some embodiments, since the etching selection ratio of the nitride layer 32b is greater than that of the first oxide layer 16b, the first oxide layer 16b can remain completely after removing the nitride layer 32b.
Then, after removing the second oxide layer 34 and the nitride layer 32b, the first oxide layer 16b is subsequently removed. It should be noted that in the embodiment that the thickness of the first oxide layer 16b is in a range from about 300 Å to about 700 Å, an etching process with a short cycle time (e.g. about 10 seconds to about 30 seconds) may be performed to completely remove the first oxide layer 16b. This etching process can remove the first oxide layer 16b completely and precisely, so the elements around the first oxide layer 16b may remain undamaged by this etching process. In particular, the short cycle time of the etching process, which is between about 10 and 30 seconds, means that the etching process can be performed to completely remove the first oxide layer 16b and prevent over etching from damaging the diffusion barrier layer 20. Furthermore, the diffusion barrier layer 20 can remain intact and the dopant diffusion from the conductive feature 28 to the periphery can be blocked effectively, and thereby the electrical properties of the peripheral elements may not be impacted.
In a specific embodiment, an etching process with hot phosphoric acid as an etchant may be performed on the nitride layer 32b and the second oxide layer 34 for about 50 seconds to about 100 seconds to completely remove the nitride layer 32a and the second oxide layer 34. Subsequently, an etching process with hydrofluoric acid as an etchant is performed on the first oxide layer 16b for about 50 seconds to about 100 seconds to completely remove the first oxide layer 16b.
In some other embodiments, the second oxide layer 34, the nitride layer 32b, and the first oxide layer 16b may be removed in sequence. For example, the hydrofluoric acid is used to remove the second oxide layer 34, the hot phosphoric acid is used to remove the nitride layer 32b, and then the hydrofluoric acid is used to remove the first oxide layer 16b.
Referring to
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In addition, a source region 40 may be formed in the first well region 38, wherein the source region 40 surrounds a portion of the conductive feature 28 which is near the upper surface of the epitaxial layer 12. In the present embodiment, the diffusion barrier layer 20 contacts the source region 40 and separates the source region 40 from the conductive feature 28. Thus, the diffusion barrier layer 20 can block the dopants of the conductive feature 28 diffusing to the source region 40 which further prevents the electrical properties of the source region 40 from being impacted. The source region 40 may be N-type. In some embodiments, a drain region 44 may be formed in the second well region 42. The drain region 42 may be heavily-doped N-type.
In some embodiments, a gate spacer 54 may be formed on sidewalls of the gate structure 46, and an insulating layer 55 may be formed on the upper surface of the gate structure 46, a surface of the gate spacer 54, and the upper surface of the epitaxial layer 12, wherein the insulating layer 55 exposes the conductive feature 28, the source region 40, and the drain region 44.
In some embodiments, a conductive layer 56 may be formed on the epitaxial layer 12. The conductive layer 56 covers the conductive feature 28, the source region 40, the gate structure 46, and a portion of the second well region 42, and exposes the drain region 44. In some embodiments, an interlayer dielectric layer 58 may be formed on the epitaxial layer 12, and a contact plug 60 may be formed to penetrate the interlayer dielectric layer 58 and connect the drain region 44. The contact plug 60 may include polysilicon, aluminum, gold, cobalt, copper, similar materials, or a combination thereof. Then, a conductive feature 62 may be formed on the interlayer dielectric layer 58 and electrically connect the contact plug 60. The conductive feature 62 may include copper, gold, tin, similar materials, or a combination thereof.
A semiconductor structure 100 shown in
In summary, the semiconductor structure in the embodiments of the present disclosure has a diffusion barrier layer disposed between a conductive feature and an epitaxial layer. Thus, the diffusion barrier layer can block the dopant diffusion from the conductive feature to the periphery during subsequent processes (e.g. a high-temperature thermal process) which further prevents the electrical properties of peripheral elements from being impacted. Furthermore, the scaling down of the LDMOS is not limited and the source-drain resistance (RDSON) can be reduced further to enhance the performance of the LDMOS.
In addition, when the height of the top surface of the conductive feature is lower than or the same as the height of the top surface of the epitaxial layer, a seam in the conductive feature penetrates the top surface of the conductive feature to cause erosion in subsequent cleaning steps, so short-circuits and other problems may subsequently arise. Thus, the conductive feature of the semiconductor structure in the embodiments of the present disclosure that has a protruding portion that is higher than the epitaxial layer can prevent the seam in the conductive feature from penetrating the top surface of the conductive feature and further prevent problems from arising in subsequent manufacturing processes.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
