BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view showing a conventional semiconductor structure located on the scribe line.
FIGS. 2A through 2C are cross-sectional views showing a method for manufacturing a semiconductor structure according to one embodiment of the present invention.
FIG. 3A is a top view of the semiconductor structure on a scribe line shown in FIG. 2C.
FIG. 3B is a top view of a semiconductor structure according to another embodiment of the present invention.
FIG. 3C is a top view of a semiconductor structure according to the other embodiment of the present invention.
FIG. 3D is a top view of a semiconductor structure according to the other embodiment of the present invention.
FIG. 3E is a top view of a semiconductor structure according to the other embodiment of the present invention.
FIG. 3F is a top view of a semiconductor structure according to the other embodiment of the present invention.
FIG. 3G is a top view of a semiconductor structure according to the other embodiment of the present invention.
FIG. 3H is a top view of a semiconductor structure according to the other embodiment of the present invention.
FIGS. 4A through 4C are cross-sectional views showing a method for manufacturing a semiconductor structure according to one embodiment of the present invention.
FIG. 5 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
FIGS. 2A through 2C are cross-sectional views showing a method for manufacturing a semiconductor structure according to one embodiment of the present invention. As shown in FIG. 2A, a substrate 200 is provided. The substrate 200 has a scribe line region 201 and a device region (not shown). Then, a dielectric layer 202 is formed on the substrate 200. The dielectric layer 202 can be, for example, made of low-k material. Furthermore, within the dielectric layer 202 located in the scribe line region 201, there are interconnects structures or other device structures (not shown) which are as same as those formed in the dielectric layer 202 in the device region. These interconnects structures or other device structures are used as test keys. Thereafter, a test pad 204 is formed on the dielectric layer 202 in the scribe line region 201 and the test pad 204 is electrically connected to the aforementioned interconnects structures and other device structures so that the operator can use probe or other method to perform an inspection on the test key within the dielectric layer 202 in the scribe line region 201. Hence, the condition of the device in the device region can be monitored anytime. The material of the test pad 204 can be, for example, aluminum and the method for forming the test pad 204 can be, for example, comprise forming a pad material layer (not shown) on the dielectric layer 202 and then patterning the pad material layer.
As shown in FIG. 2B, a passivation layer 206 is formed on the dielectric layer 202 to cover the test pad 204. The passivation layer 206 can be, for example, made of silicon oxide, silicon nitride, silicon oxy-nitride or the well-known insulating material and the method for forming the passivation layer 206 can be, for example, a chemical vapor deposition. Then, a patterned photoresist layer 208 is formed on the passivation layer 206. The patterned photoresist layer 208 exposes a portion of the passivation layer 206 above the test pad 204 and a position for forming grooves in the later performed process.
As shown in FIG. 2C, by using the patterned photoresist layer 208 as a mask, an etching process is performed to remove the exposed portion of the passivation layer 206 over the test pad 204 and the position predetermined to form grooves so that the test pad 204 is exposed and a groove 210 between sidewalls of the passivation layer 206 and the test pad 204 at each side of the test pad 204 is formed. Moreover, the groove 210 is located between the test pad 204 and the boundary 203 of the scribe line region 201. The groove 210 exposes a portion of the surface of the dielectric layer 202. Then, the patterned photoresist layer 208 is removed.
It should be noticed that the steps for forming the aforementioned test pad 204, the test keys, the dielectric layer 202 and the passivation layer 206 is commonly integrated with the manufacturing process performed on the device region and it is unnecessary to further perform additional manufacturing steps. In addition, in the aforementioned etching process, not only the portion of the passivation layer 206 over the test pad 204 and the position predetermined to form grooves is removed but also a portion of the passivation layer 206 over the bonding pad in the device region is removed.
FIG. 3A is a top view of the semiconductor structure on a scribe line shown in FIG. 2C. FIG. 2C is taken as an example hereafter to describe the semiconductor structure of the present invention.
As shown in FIG. 3A together with FIG. 2C, the semiconductor structure of the present invention is located at the scribe line region 201 on the substrate 200. The semiconductor structure comprises the dielectric layer 202, the test pad 204 and the passivation layer 206. The dielectric layer 202 is disposed on the substrate 200 and the test pad 204 is located on the dielectric layer 202. The passivation layer 206 is located on the dielectric layer 202 and surrounding the test pad 204. Between the sidewalls of the passivation layer 206 and the test pad 204 at each side of the test pad 204, there is a groove 210 and the groove 210 is located between the test pad 204 and the boundary 203 of the scribe line region 201. In this embodiment, because the groove 210 is located between the passivation layer 206 and the test pad 204, that is, the extension direction of the groove 210 is along the cutting direction, the stress, which is generated from the test pad 204 as the test pad 204 is cut during the wafer cutting process, dose not impact the passivation layer 206 to be laminated. Furthermore, the problem that the external moisture enters into the device region through the interface between the passivation layer 206 and the dielectric layer 202 due to the delamination of the passivation layer can be avoided.
Additionally, in another embodiment, the bottom of the groove 210 can be located within the dielectric layer 202. That is, in the aforementioned etching process, not only a portion of the passivation layer 206 is removed but also a portion of the dielectric layer 202 is removed to form a groove 210 with a bottom inside the dielectric layer 202. Accordingly, the delamination of the passivation layer 206 due to the stress generated from the test pad 204 during the wafer cutting process can be avoided.
Furthermore, in the other embodiment, the shape of the groove 210 can be the shape shown in FIG. 3A and the opposite sides of the groove 210 which intersect with the cutting direction along the scribe line region 201 are at the same level with the opposite sides of the test pad 204, which intersect with the cutting direction along the scribe line region 201, respectively. Alternatively, the length of the groove 210, which is along the cutting direction following the scribe line region, can be larger than that of the test pad 204 and the lengths of the grooves 210 at both sides of the test pad 204 can be different from each other (as shown in FIG. 3B). In the other embodiment, the groove 210 not only can be disposed between the test pad 204 and the boundary 203 of the scribe line region 201 but also can be located adjacent to the test pad 204 and partially surrounding the test pad 204 (as shown in FIG. 3C) or fully surrounding the test pad 204 (as shown in FIG. 3D).
Notably, in the step for forming the groove 210 by using the etching process, besides using the patterned photoresist layer 208 as a mask to form the aforementioned groove 210, the patterned photoresist layer with different pattern can be also applied as a mask in the etching process so as to form several grooves 211 instead of the groove 210 at each side of the test pad 204. Moreover, the shape constituted by the grooves 211 at each of the opposite sides, which is parallel to the cutting direction along the scribe line region 201, can possess outmost sides, which intersect with the cutting direction along the scribe line region 201, at the same level with the opposite sides of the test pad 204, which intersect with the cutting direction along the scribe line region 201 (as shown in FIG. 3E). Alternatively, the length of the shape, which is along the cutting direction following the scribe line region, constituted by the grooves 211 can be larger than that of the test pad 204 (as shown in FIG. 3F). In the other embodiment, the shape constituted by the grooves 211 partially surrounds the test pad 204 (as shown in FIG. 3G) or fully surrounds the test pad 204 (as shown in FIG. 3H).
Additionally, in the FIG. 2A, before the dielectric layer 202 is formed, at least one dielectric layer 212 is formed on the substrate 200. The formation of two dielectric layers 212 over the substrate 200 is taken as an example in the following to describe the method for manufacturing a semiconductor structure of the present invention.
FIGS. 4A through 4C are cross-sectional views showing a method for manufacturing a semiconductor structure according to one embodiment of the present invention. As shown in FIG. 4A, a substrate 200 is provided. Then, a first dielectric layer 212 is formed on the substrate 200. The material of the first dielectric layer 212 can be, for example, a low-k material and, within the first dielectric layer 212 located in the scribe line region 201, there are test keys (not shown). Thereafter, a first test pad 214 is formed on the first dielectric layer 212 over the scribe line region 201 and the test pad 214 is electrically connected to the aforementioned test keys so that the operator can use probe or other method to perform the inspection. Moreover, a second dielectric layer 212 is formed on the first dielectric layer 212 and a second test pad 214 is formed on the second dielectric layer 212 over the scribe line region 201. Noticeably, in order to save the space to meet the requirement of the high integration, the second test pad 214 is normally formed right above the first test pad 214. Then, a dielectric layer 202 is formed on the second dielectric layer 212 and a test pad 204 is formed on the dielectric layer 202 over the scribe line region 201. Furthermore, the test pad 204 is located right above the second test pad 214. Further, a passivation layer 206 is formed on the dielectric layer 202 to cover the test pad 204. In addition, a patterned photoresist layer 208 is formed on the passivation layer 206 to expose a portion of the passivation layer 206 above the test pad 206 and the position for forming grooves in the later performed process.
As shown in FIG. 4B, by using the patterned photoresist layer 208 as a mask, an etching process is performed to remove the exposed passivation layer 206 over the test pad 204 and the position predetermined to form grooves to expose the test pad 204 and to form grooves 210 between the sidewalls of the passivation layer 206 and the test pad 204 at both sides of the test pad 204. Moreover, the groove 210 is located between the test pad 204 and the boundary 203 of the scribe line region 201 at each side of the test pad 204. The groove 210 exposes a portion of the surface of the dielectric layer 202.
As shown in FIG. 4C, by using the patterned photoresist layer 208 as a mask, another etching process is performed to remove a portion of the dielectric layer 202, a portion of the second dielectric layer 212 and a portion of the first dielectric layer 212 so as to form groove 213. In this embodiment, in order to prevent the dielectric layer 212 from being delaminated due to the stress generated from the test pad 214 under the test pad 204 during the wafer cutting process, the depth of the groove 213 should be large enough at least the bottom of the groove 213 at the same level with the surface of the dielectric layer 212 under the test pad 214, the first test pad 214, which is the nearest test pad to the substrate 200. Therefore, the dielectric layer 212, which is located under the nearest test pad to the substrate, can be prevented from being delaminated. That is, the bottom the groove 213 exposes the surface of the dielectric layer 212 under the nearest test pad 214 to the substrate 200. Alternatively, in another embodiment, to more efficiently prevent the dielectric layer 212 from being delaminated, the groove with relatively larger depth can be formed so that the bottom of the groove 213 is located within the dielectric layer 212 under the nearest test pad 214 to the substrate 200.
It should be noticed that the aforementioned two etching processes can be replaced by one etching process under the circumstance that the process factors of two etching processes are mutual compatible. That is, in the step illustrated by FIG. 4B, by using the patterned photoresist layer 208 as a mask, the groove 213 is directly formed by performing the etching process once.
Moreover, since the depth of the groove 213 is relatively large, the time for performing the etching process is relatively long. Therefore, the width of the upper opening of the groove 213 is relatively large because etching time is relatively long.
FIG. 3C is taken as an example hereafter to describe the semiconductor structure of the present invention.
As shown in FIG. 4C, the semiconductor structure of the present invention is located at the scribe line region 201 on the substrate 200. The semiconductor structure comprises the dielectric layers 202 and 212, the test pads 204 and 214 and the passivation layer 206. The dielectric layer 202 is disposed on the substrate 200 and the test pad 204 is located on the dielectric layer 202. The first dielectric layer 212 and the second dielectric layer 212 are disposed in order between the substrate 200 and the dielectric layer 202 and each layer of the dielectric layers 212 has a test pad 214 thereon. In addition, the test pads 214 are located under the test pad 204. The passivation layer 206 is located on the dielectric layer 202 and surrounding the test pad 204. Between the sidewalls of the passivation layer 206 and the test pad 204 at each side of the test pad 204, there is a groove 213 and the groove 213 is located between the test pad 204 and the boundary 203 of the scribe line region 201. The bottom of the groove 213 exposes the surface of the dielectric layer 212 under the test pad 214 which is the nearest test pad to the substrate 200. In another embodiment, to more efficiently prevent the dielectric layer 212 from being delaminated, the bottom of the groove 213 can be located within the dielectric layer 212 under the nearest test pad 214 to the substrate 200.
In the step illustrated by FIG. 4A, the test pad 214 can be selectively formed on the first dielectric layer 212 or on the second dielectric layer 212 in the scribe line region 201 according to the practical requirement.
For example, in one embodiment, the first dielectric layer 212 is formed on the substrate 200 beforehand. Then, the test pad 214 is formed on the first dielectric layer 212. Thereafter, the second dielectric layer 212 and the dielectric layer 202 are formed on the first dielectric layer 212 sequentially. Then, the test pad 204 and the passivation layer 206 are formed on the dielectric layer 202. A photolithography process and an etching process are performed to form the groove 213 and the bottom of the groove 213 is located at the surface of the first dielectric layer 212 or within the first dielectric layer 212. Hereafter, FIG. 5 is used to describe the semiconductor structure formed according to the method of this embodiment.
FIG. 5 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. As shown in FIG. 5, the difference between the semiconductor structure of this embodiment differentiates and the semiconductor structure shown in FIG. 4C is that, in the semiconductor structure in FIG. 4C, the test pads 214 are disposed on the first dielectric layer 212 and the second dielectric layer 212 respectively and on the other hand, in the semiconductor structure of the present embodiment, the test pad 214 only disposed on the first dielectric layer 212. It should be noticed that, in this embodiment, although there is no test pad on the second dielectric layer 212, the bottom of the groove 213 still need to be located at the surface of the first dielectric layer 212 or within the first dielectric layer 212 as there is a test pad disposed on the first dielectric layer 212 so that the delamination of the first dielectric layer 212 during the wafer cutting process can be avoided.
Altogether, in the present invention, the groove is formed between the test pad and the boundary of the scribe line region so that the delamination of the film layer (such as the passivation layer or the dielectric layer) squeezed by the stress generated by the test pad during the wafer cutting process can be avoided. Furthermore, the devices in the device region can be prevented from being damaged by the external moisture entering into the device region through the interface between the film layers at the delamination portion. Hence, the device reliability is increased.
The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.
Patent Application
20070290204
