Claims
- 1. A semiconductor structure for a MOS transistor having a source, a drain and a channel, comprising:a substrate, a gate oxide on said substrate, and a polysilicon layer on said gate oxide; said polysilicon layer having interruptions formed therein, and defining field plates and a polysilicon layer in an active area of the semiconductor structure; insulating oxide disposed above said field plates and in said interruptions in said polysilicon layer; and a further polysilicon deposition on said polysilicon layer in the active area, said deposition raising up said polysilicon layer in the active area to a level being substantially coplanar with said insulating oxide above said field plates.
Priority Claims (1)
Number |
Date |
Country |
Kind |
196 22 276 |
Jun 1996 |
DE |
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CROSS-REFERENCE TO RELATED APPLICATION
This application is a division of application No. 08/870,121, filed Jun. 3, 1997, now U.S. Pat. No. 5,817,570.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
Country |
41 12 045 A1 |
Oct 1991 |
DE |
Non-Patent Literature Citations (1)
Entry |
“Improved Narrow Trench Profile Using a Composite Spacer Process” (Garling et al.), Motorolla, Aug. 1996, p. 143. |