Patent Application
20190067477
The present invention relates generally to the field of semiconductor structure with fin-shaped structures, and more particularly to a semiconductor structure with periodically arranged fin-shaped structures and the method of fabricating the same.
Semiconductor devices are used in a large number of electronic devices, such as computer, communication, consumer electronics, cars and others. Semiconductor devices comprise integrated circuits (ICs) that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. The most common active element in the ICs is transistor including planar field-effect transistors (FETs) such as metal oxide semiconductor (MOS) transistors and 3D fin field-effect transistors (FinFETs).
In generally, a fin field-effect transistor may include periodically arranged fin-shaped structures which are often physically and electrically separated by a trench isolation structure, such as shallow trench isolation (STI). The fin-shaped structures protruding from the STI may act as active regions of the transistors. Since the height to width ratio of each fin-shaped structure is gradually increased with the advance of the semiconductor techniques, several drawbacks, such as fin bending or cracking, often occurs when the process of fabricating STI is completed and thus degrade the performance of the corresponding fin field-effect transistor.
In order to overcome the drawbacks disclosed above, there is a need for providing an improved fin field-effect transistor and the method of fabricating the same.
According to one embodiment of the present invention, a semiconductor structure is provided and includes a substrate, fin-shaped structures disposed on the substrate, an isolation layer disposed between the fin-shaped structures, and a doped region disposed in an upper portion of the isolation layer, where the doped region is doped with helium or neon.
According to another embodiment of the present invention, a method for fabricating a semiconductor structure is provided and includes the following steps: providing a substrate; forming fin-shaped structures on the substrate; forming an isolation layer to fill up a space between the fin-shaped structures; performing a first ion implantation process to implant an element to the isolation layer, where the first ion implantation process has a first ion implantation energy; performing a second ion implantation process to implant another element to the isolation layer, where the second ion implantation process has a second ion implantation energy different from the first ion implantation energy; and annealing the isolation layer after performing the first and the second ion implantation processes.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The invention will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, the disclosed embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity unless express so defined herein. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well. Like numbers refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments.
Spatially relative terms, such as “inner,” “outer,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element and/or feature's relationship to another element(s) and/or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” and/or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular terms “a”, “an,” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “includes” and/or “including” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.
Example embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the disclosed example embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein unless expressly so defined herein, but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention, unless expressly so defined herein.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the following paragraphs, processes for fabricating a semiconductor structure with fin-shaped structures are described in detail.
Referring to
Then, in step 1004, several fin-shaped structures 110 and trenches 102 are fabricated by etching the substrate 100. In particularly, in order to form the trench 102 and the fin-shaped structure 110, a hard mask 130 is formed first and followed by an etching process to remove a portion of the substrate 100 not covered and protected by the hard mask 130, thus the fin-shaped structure 110 is formed between the two adjacent trenches 102. The hard mask 130 may be fabricated by depositing a hard mask layer (not shown) through a suitable process such as, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even silicon oxide formation followed by nitridation, may alternatively be utilized. In addition, the hard mask layer (not shown) may be any suitable material such as titanium oxide (TiO2), tantalum oxide (TaO), silicon nitride (SiN), silicon oxide (SiO2), silicon carbide (SiC), silicon carbide nitride (SiCN), and a combination thereof. Once the hard mask layer (not shown) is formed, the hard mask layer is patterned through a suitable photolithographic and etching process to form a pattern. A portion of the hard mask layer over the substrate may act as the hard mask 130 used to define the position of the fin-shaped structure 110, while other portions of the hard mask layer over the substrate 100 may be removed so as to define the position of the trench 102. After the formation of the hard mask 130, an etching process is performed to etch the substrate 100 not covered and protected by the hard mask 130. Therefore, the fin-shaped structure 110 is formed between the hard mask 130 and the substrate 100.
Referring to
Referring to
Furthermore, a position and a thickness of the doped dielectric layer 220 can be controlled by ion implantation parameters such as, but not limited to, kind of ions, implantation time, implantation angle, and implantation energy. By properly setting the parameters, the doped dielectric layer 220 can be formed in a desired position with a desired thickness. In addition, multiple ion implantations of different kinds of foreign elements may be conducted to obtain a desired doped structure of unique characteristics, position, and thickness.
According to this embodiment, a first ion implantation process with implantation energy of 10 keV, 16 keV or 20 keV is conducted to implant foreign element, such as helium or neon, to the dielectric layer 200. Then, a second ion implantation process with implantation energy of 10 keV, 16 keV or 20 keV is conducted to implant foreign element, such as helium or neon, to the dielectric layer 200. Preferably, the first implantation process and the second implantation process are performed at the same temperature and dose, and the implantation energy of the first implantation process is different from the implantation energy of the second implantation process. More preferably, the implantation energy of the first implantation process is less than the implantation energy of the second implantation process. In this way, the foreign elements may be uniformly distributed in the doped dielectric layer 220.
Refer to
Refer to
Then, the process proceeds to step 1012 by performing an annealing process. In some embodiments, the annealing process is performed at 900° C.˜1100° C. It is understood that the annealing process is aimed to release structural stress of the dielectric layer 200 and expel impurities from the dielectric layer 200. That is to say, the former is relocating position of atoms to compensate or eliminate defects in material, while the latter is removing undesired elements by diffusing them out of material. In particular, several structural defects are generated during depositing the dielectric layer 200, which need to be eliminated before following manufacturing process. Generally, during the annealing of the dielectric layer 200, the shrinkage of the dielectric layer 200 will cause a structural stress on the adjacent structure (i.e. the fin-shaped structure 110) so that the fin-shaped structure 110 may be bending or even cracking. However, according to the disclosure, since the doped dielectric layer 220 have a coefficient of thermal expansion (CTE) closer to the fin-shaped structure 110, the defects of fin-shaped structure 110 such as fin bending or cracking may be avoided during the annealing process.
It should be noted that, in some embodiment, the annealing process and the ion implantation process are performed at the same time. In other embodiments, the annealing process may comprise multiple annealing processes with/without steam or various gases. In other embodiments, the annealing process and the aforementioned ion implantation process may be performed at the same time. In some embodiments, additional annealing process may be performed after the planarization process afterward.
Then, referring to
As shown in
Referring to
Then, referring to
Referring to
As shown in Table 1, when the stress is more negative, the compressive stress between fin-shaped structures and the neighboring dielectric layer is more significant. Therefore, by increasing the compressive stress between fin-shaped structures and the neighboring dielectric layer, the drawbacks, such as fin bending and cracking, can be overcome successfully. Furthermore, the compressive stress applied to the fin-shaped structures also increases along with the increase in the temperature of the ion implantations. For example, as shown in Table 1, the compressive stress for the cases where the ion implantation is conducted at 500° C. is generally more intense than the compressive stress for the cases where the ion implantation is conducted at the temperature lower than 500° C., i.e. 25° C. (R.T.) and 200° C.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
