BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view illustrating a transistor according to some embodiments of the present invention.
FIGS. 2 to 5 are cross-sectional views illustrating methods of manufacturing the transistor of FIG. 1 according to some embodiments of the present invention.
FIG. 6 is a cross-sectional view illustrating a transistor according to some other embodiments of the present invention.
FIGS. 7 to 8 are cross-sectional views illustrating methods of manufacturing the transistor of FIG. 6 according to some embodiments of the present invention.
FIG. 9 is a graph illustrating inversion capacitances.