Patent Application
20100207175
Embodiments of the subject matter described herein relate generally to semiconductor devices. More particularly, embodiments of the subject matter relate to a semiconductor transistor having an embedded stress element for the source region and having no embedded stress element for the drain region.
The prior art is replete with different techniques and processes for fabricating semiconductor devices such as metal oxide semiconductor (MOS) transistors. In accordance with typical fabrication techniques, a MOS transistor is formed by creating a device structure on a semiconductor substrate, where the device structure includes a gate stack formed on a layer of semiconductor material, and source and drain regions formed in the semiconductor material to define a channel region under the gate stack. In addition, embedded strain elements (i.e., doped or undoped semiconductor material that imparts longitudinal stress on the channel region) can be used to improve the performance of MOS transistors. The conventional approach is to form embedded strain elements on both sides of the channel region: some of the stress-inducing material is located in the source region and some of the stress-inducing material is located in the drain region. The conventional approach (symmetric strain elements on both sides of the gate region) is particularly beneficial in digital circuit applications.
An exemplary embodiment of a semiconductor transistor device includes a layer of semiconductor material having a channel region defined therein, a gate structure overlying the channel region, a source region in the layer of semiconductor material, a drain region in the layer of semiconductor material, the channel region located between the source region and the drain region, a source recess formed in the layer of semiconductor material and located in the source region, and a stress-inducing semiconductor material located in the source recess. The stress-inducing semiconductor material is only located in the source region, and the drain region is void of the stress-inducing semiconductor material.
A method of fabricating a semiconductor device is also provided. The method involves the formation of a gate structure overlying a layer of semiconductor material, the formation of spacers adjacent sidewalls of the gate structure, and the formation of a source region and a drain region in the layer of semiconductor material. The method continues by creating a source recess in the layer of semiconductor material corresponding to the source region without creating a drain recess in the layer of semiconductor material corresponding to the drain region. The method proceeds by at least partially filling the source recess with a stress-inducing semiconductor material.
An exemplary embodiment of a semiconductor transistor device is also provided. The device includes a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, a source region in the layer of semiconductor material, the source region comprising a stress-inducing semiconductor material, and a drain region in the layer of semiconductor material, the drain region being free of the stress-inducing semiconductor material.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
For the sake of brevity, conventional techniques related to semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor based transistors are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.
The techniques and technologies described herein may be utilized to fabricate MOS transistor devices, including NMOS transistor devices, PMOS transistor devices, and CMOS transistor devices. Although the term “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate.
MOS transistor devices can be utilized for various analog applications and circuits, such as bandgap reference, sense amplifiers, voltage regulators, current mirrors, hypertransport, phase locked loop (PLL) circuits, input/output (I/O) circuits, etc. Embedded stress-inducing material usually increases p-n junction leakage. Such leakage, while tolerable in most digital applications, can adversely affect performance of analog and input/output devices. Floating Body (FB) devices are extensively used in PLL, I/O and hypertransport circuits in silicon-on-insulator (SOI) technology. FB devices exhibit hysteresis—time and state dependent delay behavior. In general, lower hysteresis is desired, because higher positive or negative hysteresis can shrink or stretch the clock-pulse in a propagation chain. Hysteresis depends on the ability to store change in the neutral body region. The balance of source-body, drain-body, and gate-to-body current and source-body, drain-body, and gate-to-body capacitance, in turn, determines this charge. Increasing source-drain leakage is one way to reduce hysteresis.
The semiconductor transistor devices described herein take advantage of the p-n junction leakage phenomena to improve performance of analog circuits and applications. More specifically, the semiconductor transistor devices described herein includes a stress-inducing element (or elements) that imparts more stress from the source region than the drain region. In preferred embodiments, stress-inducing material is only utilized in the source region, and the drain region remains free of stress-inducing material. In alternate embodiments, the stress-inducing material on the source side may be shaped or sized, or it may have a certain composition, such that it imparts more stress to the channel region, relative to that imparted by the stress-inducing material on the drain side.
During operation, a semiconductor transistor device having stress-inducing material only in the source region will experience relatively high source-body junction leakage and relatively low drain-body junction leakage. This characteristic can be important for purposes of hysteresis estimation of a circuit. In this regard, the source-body diode is forward biased in a partially depleted MOSFET circuit. The asymmetric effect in the source and drain side diodes reduces the hysteresis in the circuit. A leaky forward biased source-body diode lowers the body voltage for a given drain-body and gate-body current and, hence, reduces hysteresis. Moreover, the absence of a stress-inducing element in the drain region of the MOS transistor results in reduced carrier mobility on the drain side (relative to the source side). Lower mobility in the drain region results in a higher saturation electric field for a given saturation velocity. The higher saturation electric field also results in increased output resistance, which is desirable for analog circuit applications. A higher electric field lowers the channel pinch-off region for given drain and gate biases and, hence, increases output resistance.
The semiconductor transistor devices described herein employ a structure having an asymmetric configuration of embedded strain elements flanking the gate region. In preferred embodiments, only a source-side strain element is used, and no stress-inducing material is located in the drain region. In this regard,
Device 100 generally includes a source region 108 formed or otherwise defined in semiconductor material 106, a drain region 110 formed or otherwise defined in semiconductor material 106, and a channel region 112 formed or otherwise defined in semiconductor material 106. Device 100 also includes a suitably configured gate structure 114 overlying semiconductor material 106. In accordance with conventional fabrication techniques and processes, channel region 112 is located between source region 108 and drain region 110, and gate structure 114 overlies channel region 112. Notably, device 100 includes a source recess 116 formed in semiconductor material 106, but it does not include a corresponding drain recess. Source recess 116 is located in source region 108, and
Source recess 116 is formed to accommodate an appropriate stress-inducing semiconductor material 118. As shown in
In accordance with typical semiconductor transistor implementations, device 100 includes silicide contact areas 120, 122, 124 for source region 108, drain region 110, and gate structure 114, respectively. These silicide contact areas 120, 122, 124 are electrically conductive elements that can be used to provide bias and/or operating voltages to device 100. Although not shown in
Referring to
Isolation regions 210 are formed that extend through semiconductor material 208 to insulating layer 206. Isolation regions 210 are preferably formed by well-known shallow trench isolation (STI) techniques. Isolation regions 210 provide electrical isolation, as needed, between various devices of the circuit that are to be formed in semiconductor material 208. Either before or preferably after fabrication of isolation regions 210, selected portions of semiconductor material 208 can be impurity doped, for example by ion implantation, to form appropriate wells for the active transistor regions. For example, an N-type well can be formed between isolation regions 210 for the fabrication of PMOS transistors.
After gate structure 212 has been created, spacers 220 are formed adjacent the sidewalls 222 of gate structure 212 (see
Although other fabrication steps or sub-processes may be performed after the formation of spacers 220, this example continues by forming a source region 226 and a drain region 228 in the layer of semiconductor material 208 (see
Although other fabrication steps or sub-processes may be performed after the formation of source region 226 and drain region 228, this example continues by forming a patterned photoresist layer 234 that overlies drain region, but does not overlie source region 226 (see
Although other fabrication steps or sub-processes may be performed after the creation of patterned photoresist layer 234, this example continues by etching semiconductor material 208 (see
Notably, patterned photoresist layer 234 protects drain region 228 and prevents the portion of semiconductor material 208 corresponding to drain region 228 from being etched. Consequently, source recess 240 is formed during the etching step without creating a drain recess in drain region 228. The formation of asymmetric recesses is depicted in FIG. 7—no recess is created in semiconductor material 208 located on the drain side of device structure 200.
Although other fabrication steps or sub-processes may be performed after the formation of source recess 240, this example continues by removing patterned photoresist layer 234 and at least partially filling source recess 240 with a stress-inducing semiconductor material 246 (see
Depending upon the chosen process technology, stress-inducing semiconductor material 246 may be grown in an undoped state, or it may be in-situ doped (meaning that a suitable dopant is introduced into a host material as that host material is grown). Epitaxially grown in-situ doped silicon material can be utilized so that the material need not be subjected to ion implantation for purposes of doping. For an NMOS transistor device, the in-situ doped material may be phosphorus doped silicon carbon, and for a PMOS transistor device, the in-situ doped material may be boron doped silicon germanium. If stress-inducing semiconductor material 246 is formed in an undoped state, then a subsequent ion implantation step may be performed to implant impurity ions into stress-inducing semiconductor material 246. In practice, both the source and drain sides could be subjected to conventional halo, extension, and other implants.
Although other fabrication steps or sub-processes may be performed at this time (e.g., thermal annealing, formation of additional spacers, etc.), this example continues by forming metal silicide contact areas for the source, drain, and gate of device structure 200. More particularly, a source silicide contact area 250 is formed on stress-inducing semiconductor material 246, a drain silicide contact area 252 is formed on drain region 228, and a gate silicide contact area 254 is formed on the polysilicon gate electrode 216 (see
Thereafter, any number of known process steps can be performed to complete the fabrication of the MOS transistor device. For the sake of brevity, these process steps and the resulting MOS transistor device are not shown or described here. A MOS transistor device can be manufactured in this manner such that it has an asymmetric profile or arrangement of strain elements. During operation, this asymmetry results in relatively high source-body junction leakage and relatively low drain-body junction leakage, which can provide certain benefits and advantages for analog circuit applications.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes could be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
