SEMICONDUCTOR WAFER

Abstract

The present invention is a semiconductor wafer 1 including an orientation identification mark 3, which is used for identifying crystal orientation, on a peripheral surface 2 thereof, in which the orientation identification mark 3 has a curved surface that is concave toward an inner diameter direction D1 of the semiconductor wafer 1 and toward a center in a thickness direction D3, and has a gloss different from that of a portion 21 outside of the orientation identification mark 3 on the peripheral surface 2.

Description

This application is based on and claims the benefit of priority from Japanese Patent Application No. 2008-133131, filed on 21 May 2008, the content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor wafer including an orientation identification mark for identifying crystal orientation.

2. Related Art

In a semiconductor wafer (hereinafter simply referred to as “wafer”) that is sliced from a semiconductor ingot such as a silicon ingot, an orientation identification mark for identifying crystal orientation thereof is provided on a peripheral portion thereof. The orientation identification mark is used, for example, for alignment of the wafer with respect to various processing devices. Conventionally, an orientation flat (hereinafter also referred to as “OF”), a notch, a laser mark or the like have been used as the orientation identification mark (for example, see Japanese Unexamined Patent Application Publication Nos. 2005-19579, No. 2001-160527, and No. Hei 10-256105).

However, in the wafer including the abovementioned orientation identification mark such as the OF, notch, laser mark or the like, breakage and slip may easily occur due to stress concentrated in a peripheral portion of the orientation identification mark, for example during transportation (in which the wafer bends particularly easily) and processing (particularly in a thermal process) thereof. Such a problem is considered to be more significant as the size of the wafers increases.

SUMMARY OF THE INVENTION

Given this, an objective of the present invention is to provide a semiconductor wafer that includes an orientation identification mark for identifying crystal orientation and that can inhibit stress concentration in a peripheral portion of the orientation identification mark therein.

In a first aspect of the present invention, a semiconductor wafer includes an orientation identification mark, which is used for identifying crystal orientation, on a peripheral surface thereof, wherein the orientation identification mark has a curved surface that is concave toward an inner diameter direction of the semiconductor wafer and toward the center in a thickness direction, and has a gloss different from that of the portion outside of the orientation identification mark on the peripheral surface.

According to a second aspect of the present invention, in the semiconductor wafer as described in the first aspect, it is preferable that: the orientation identification mark has a rectangular shape when the semiconductor wafer is seen from the inner diameter direction; and the orientation identification mark that has a rectangular shape is positioned closer to a first surface of the semiconductor wafer than the center in the thickness direction of the semiconductor wafer.

According to a third aspect of the present invention, the orientation identification mark preferably has a width in a range of 0.1 to 5.0 mm and a height in a range of 0.3 to 1.8 mm, when the semiconductor wafer is seen from the inner diameter direction.

According to the present invention, in a semiconductor wafer that includes an orientation identification mark for identifying crystal orientation, stress concentration in a peripheral portion of the orientation identification mark therein can be inhibited.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are diagrams illustrating an embodiment of a semiconductor wafer according to the present invention respectively:

FIG. 1A is a diagram illustrating the entire semiconductor wafer according to the present embodiment, seen from a thickness direction;

FIG. 1B is an enlarged view of a portion indicated by an arrow B in FIG. 1A; and

FIG. 1C is a diagram illustrating the semiconductor wafer seen from a second direction D2 shown in FIG. 1B; and

FIGS. 2A to 2D are diagrams (corresponding to FIG. 1C) sequentially showing steps for forming the orientation identification mark 3 on the semiconductor wafer 1.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the semiconductor wafer (hereinafter also referred to simply as “wafer”) according to the present invention is described hereinafter with reference to the drawings. FIGS. 1A to 1C are diagrams illustrating an embodiment of a semiconductor wafer according to the present invention. FIG. 1A is a diagram illustrating the entire semiconductor wafer according to the present embodiment, seen from a thickness direction. FIG. 1B is an enlarged view of a portion indicated by an arrow B in FIG. 1A. FIG. 1C is a diagram illustrating the semiconductor wafer seen from a second direction D2 shown in FIG. 1B. The second direction D2 is a direction that is orthogonal to a direction from the center 11 in a diameter direction of wafer 1 to the orientation identification mark 3.

A wafer 1 according to the present embodiment is, for example, a silicon wafer or a gallium arsenide wafer.

As shown in FIGS. 1A to 1D, a shape of the wafer 1, in which an orientation identification mark 3 (described later) is not formed, seen from a thickness direction (a third direction D3) is typically a perfect circle. Diameter of the wafer 1 is, for example, 200 mm, 300 mm, or 450 mm. Here, the diameter of the wafer 1 is a desired value in manufacturing, and includes a predetermined tolerance (allowable margin of error). The shape of the wafer 1 seen from the thickness direction D3 can also be elliptical.

Thickness t of the wafer 1 is, for example, in a range of 725 to 2000 μm, and preferably in a range of 925 to 1800 μm.

The wafer 1 according to the present embodiment is not provided with a conventional orientation identification mark, such as an orientation flat (OF), a notch, a laser mark or the like, as an orientation identification mark that is used for identification of crystal orientation. Instead, the wafer 1 according to the present embodiment is provided with the orientation identification mark 3 on a peripheral surface 2 thereof.

The orientation identification mark 3 is a mark used for identifying crystal orientation and provided at a position indicating crystal orientation <110>±1 degree on a peripheral surface 2 of the wafer 1, for example.

The orientation identification mark 3 has a curved surface that is concave toward an inner diameter direction D1 of the wafer 1 and toward a center 14 (shown by a dashed-dotted line in FIG. 1C) in a thickness direction D3. The inner diameter direction D1 of the wafer 1 is a direction from the peripheral surface 2 of the wafer 1 to a center 11 of the wafer 1.

The orientation identification mark 3 has a gloss different from that of a portion outside of the orientation identification mark 3 (hereinafter referred to as “unmarked portion 21”) on the peripheral surface 2. As used herein, “having a gloss that is different” indicates that the gloss is different to such a degree that the orientation identification mark 3 and the unmarked portion 21 can be distinguished by an optical sensor or can be visually distinguished.

The orientation identification mark 3 has a width W1 smaller than a perimeter of the peripheral surface 2 of the wafer 1 and a height W2 smaller than a thickness t of the wafer 1. In addition, the orientation identification mark 3, which has a rectangular shape, is positioned more on an inner side in the thickness direction D3 than a first surface 12 (one principal surface) and a second surface 13 (another principal surface) of the wafer 1. More specifically, the orientation identification mark 3, which has a rectangular shape, is disposed closer to the center 14 in the thickness direction D3 of the wafer 1 than the first surface 12 of the wafer 1, and closer to the first surface 12 than the center 14 in the thickness direction D3 of the wafer 1, when the wafer 1 is seen from the inner diameter direction D1.

The width (maximum width) W1 of the orientation identification mark 3 is, for example, in a range of 0.1 to 10.0 mm and preferably in a range of 0.1 to 5.0 mm. In addition, a height (maximum height) W2 thereof is, for example, in a range of 0.1 to 2.0 mm and preferably in a range of 0.3 to 1.8 mm.

As shown in FIG. 1B, a depth (maximum depth) W3 of the orientation identification mark 3 from the peripheral surface 2 is, for example, in a range of 575 to 2225 μm, and more preferably in a range of 1075 to 1175 μm.

When the wafer 1 is seen from the second direction D2, in the unmarked portion 21 on the peripheral surface 2 of the wafer 1, a portion closer to the first surface 12 than the orientation identification mark 3 and a portion closer to the second surface 13 than the orientation identification mark 3 are rounded.

A manufacturing method for the wafer 1 according to the present embodiment is hereinafter described with reference to the drawings. FIGS. 2A to 2D are diagrams (corresponding to FIG. 1C) sequentially showing steps for forming the orientation identification mark 3 on the semiconductor wafer 1.

In a slicing step, a semiconductor wafer 1A as shown in FIG. 2A is obtained by slicing a semiconductor ingot (not shown) by way of a wire saw or the like. Here, the wafer 1A is not chamfered.

As shown in FIG. 2B, in a chamfering step, the wafer 1A obtained in the slicing step is subjected to chamfering processing (beveling), thus obtaining a semiconductor wafer 1B. More specifically, a grinding wheel is brought into contact with an edge on the peripheral surface 2 of the wafer 1, thereby rounding the edge. This is aimed at preventing cracking of the wafer 1 and generation of dust from the wafer 1.

As shown in FIG. 2C, in a mark-forming step, an orientation identification mark 3 is formed on the semiconductor wafer 1B obtained in the chamfering step.

The orientation identification mark 3 is formed by means of, for example, an etching solution supplying device.

The etching solution supplying device includes a solution tank (not shown), a solution pump (not shown), a solution supplying nozzle 51 and the like.

The solution tank contains a predetermined etching solution E. For example, mixed acid composed of hydrofluoric acid, nitric acid, acetic acid, or the like is used as the etching solution E. The solution pump feeds the etching solution contained in the solution tank to the solution supplying nozzle 51. The solution supplying nozzle 51 supplies the etching solution E, fed by the solution pump, in a spot-like shape (point-like shape) on the peripheral surface 2 of the wafer 1. A mode of supplying the etching solution E to the wafer 1 is not particularly limited, and a drip, a spray, or allowing the solution to flow down the wafer can be adopted.

With the etching solution supplying device thus configured, the orientation identification mark 3 can be formed on the wafer 1B by, for example: supplying the etching solution E at a predetermined position (a position at which the orientation identification mark 3 is formed) on the peripheral surface 2 of the wafer 1B in a spot-like shape. As a result, as shown in FIG. 2D, a portion on the peripheral surface 2 of the wafer 1B is locally removed in a curved shape, thereby forming a curved portion, which is concave toward the inner diameter direction D1 of the wafer 1 and toward the center 14 in the thickness direction D3, on the peripheral surface 2. The curved portion is the orientation identification mark 3. It should be noted that a two-dot chain line in FIG. 2D is a virtual extended line 22 of the peripheral surface 2.

Here, the orientation identification mark 3 has a gloss different from that of the unmarked portion 21 on the peripheral surface 2. In addition, in etching processing, processing distortions do not easily occur, thus alleviating stress concentration in a peripheral portion of the orientation identification mark 3 on the wafer 1.

It should be noted that, in addition to the abovementioned steps, various steps can be carried out before and after the mark forming step, as necessary.

As described above, in the wafer 1 according to the present embodiment, the orientation identification mark 3 has a curved surface that is concave toward an inner diameter direction D1 of the wafer 1 and toward a center 14 in a thickness direction D3, and has a gloss different from that of the unmarked portion 21. As a result, crystal orientation can be identified by an optical sensor or can be visually identified, and stress concentration in a peripheral portion of the orientation identification mark 3 on the wafer 1 can be inhibited.

An embodiment of the present invention has been described above; however, the present invention is not limited thereto.

For example, in the abovementioned mark forming step, although the orientation identification mark 3 is formed by means of the etching solution supplying device in order to inhibit processing distortions, the present invention is not limited thereto. With regard to processing that does not easily generate processing distortions, the orientation identification mark 3 can be formed by processing such as polishing or the like.

Claims

1. A semiconductor wafer comprising an orientation identification mark used for identifying crystal orientation, on a peripheral surface thereof, wherein the orientation identification mark has a curved surface that is concave toward an inner diameter direction of the semiconductor wafer and toward a center in a thickness direction, and has a gloss different from that of the portion outside of the orientation identification mark on the peripheral surface.

2. The semiconductor wafer according to claim 1, wherein: the orientation identification mark has a rectangular shape when the semiconductor wafer is seen from the inner diameter direction; and the orientation identification mark that has a rectangular shape is positioned closer to a first surface of the semiconductor wafer than the center in the thickness direction of the semiconductor wafer.

3. The semiconductor wafer according to claim 2, wherein a width thereof is in a range of 0.1 to 5.0 mm and a height thereof is in a range of 0.3 to 1.8 mm, when the semiconductor wafer is seen from the inner diameter direction.