1. Field of the Invention
This invention generally relates to a semiconductor device and fabrications thereof and more particularly to a fin field effect transistor and fabrication thereof.
2. Description of the Related Art
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin field effect transistor (FinFET). A typical FinFET is fabricated with a thin ‘fin’ extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reduction of short channel effect and higher current flows.
There are issues associated with fabrication of FinFETs.
The invention provides a semiconductor device, comprising a substrate, a fin type semiconductor layer disposed on the substrate, a gate dielectric layer disposed on a top and sidewalls of the fin type semiconductor layer, a metal nitride layer disposed on the gate dielectric layer, and an aluminum doped metal nitride layer disposed on the metal nitride layer. In an embodiment of the invention, the metal nitride layer is a titanium nitride layer and the aluminum doped metal nitride layer is an aluminum doped titanium nitride layer.
The invention provides a fin field effect transistor device, comprising a fin type semiconductor layer, a gate structure wrapping around the fin type semiconductor layer, wherein the gate structure comprises a gate dielectric layer and a titanium nitride layer, and an oxidation barrier layer protecting the titanium nitride layer from oxidation, wherein the oxidation barrier layer comprises aluminum doped titanium nitride layer.
The invention provides a method for forming a semiconductor device, comprising providing a substrate, forming a fin type semiconductor layer on the substrate, forming a gate dielectric layer on a top and sidewalls of the fin type semiconductor layer, forming a metal nitride layer on the gate dielectric layer; and forming an aluminum doped metal nitride layer on the metal nitride layer.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein,
It is understood that specific embodiments are provided as examples to teach the broader inventive concept, and one of ordinary skill in the art can easily apply the teaching of the present disclosure to other methods or apparatus. In addition, it is understood that the methods and device discussed in the present disclosure include some conventional structures and/or processes. Since these structures and processes are well known in the art, they will only be discussed in a general level of detail. Furthermore, reference numbers are repeated throughout the drawings for sake of convenience and example, and such repetition does not indicate any required combination of features or steps throughout the drawings. Moreover, the formation of a first feature over and on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. A FinFET device as the term is employed in the current disclosure provides any fin-based, multi-gate transistor.
In other embodiments, the substrate 202 includes a silicon-on-insulator (SOT) substrate. The SOI substrate may be fabricated by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The layer of silicon may be a silicon layer of an SOI substrate (e.g., overlying an insulator layer). The fins 204 may be formed, for example, by etching a layer of silicon on the substrate or a polysilicon layer on the substrate.
In an embodiment, the fins 204 may be formed by a double-patterning lithography (DPL) process. The DPL process is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. The DPL process allows for fabrication of enhanced feature (e.g., fin) density. Various DPL processes have been disclosed including, double exposure (e.g., using two mask sets), adjacent feature spacer formation and feature removal processes to provide a pattern of spacers, and resist freezing, and/or other suitable processes.
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The invention replaces the silicon nitride and TEOS barrier layer with an aluminum doped metal nitride layer 208 and has the following advantages. First, the aluminum doped metal nitride layer 208 has good barrier performance and is thinner than the silicon nitride and TEOS barrier layer, such that the space between fins can be increased for SOD filling to eliminate SOD void issues. Second, the aluminum doped metal nitride layer 208 can be in-situ formed at the same chamber for forming the metal nitride layer 208. Therefore, the invention can save process time and/or cost. Third, the invention can fine tune the aluminum concentrations of the aluminum doped metal nitride layer 208 for better process flexibility.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. It is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.