The present disclosure relates to sensing circuits, and more particularly, to sensing circuits and a method for sensing charge trap transistors.
A one time programmable memory (OTPM) is a charge trap transistor based non-volatile memory which contains a twin cell circuit. In the twin cell circuit, data is stored when electrons are trapped in a gate dielectric. The trapped electrons (i.e., trapped charge) lead to a threshold voltage (Vt) shift on either the true transistor or complement transistor, which weakens the device.
In conventional circuits, a differential current sense amplifier is used to sense a current threshold voltage (Vt) between a true transistor and a complement transistor. However, the conventional circuits are slow to sense the data. Therefore, improved sensing circuits are needed to perform a faster sensing operation.
In an aspect of the disclosure, a structure includes a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.
In another aspect of the disclosure, a circuit includes a twin cell transistor pair which is activated by a wordline, a first cross-coupled transistor which is connected to the twin cell transistor pair through a true bitline signal, and a second cross-coupled transistor which is connected to the twin cell transistor pair through a complement bitline signal.
In another aspect of the disclosure, a method includes programming one of a true transistor and a complement transistor of a twin cell transistor pair, comparing a first delay through a first delay path circuit connected to the complement transistor with a second delay through a second delay path circuit connected to the true transistor after programming one of the true transistor and the complement transistor, sensing a threshold voltage difference between the true transistor and the complement transistor based on a comparison of the first delay with the second delay, and outputting a data signal based on the sensed threshold voltage difference between the true transistor and the complement transistor.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to sensing circuits, and more particularly, to sensing circuits and a method for sensing charge trap transistors. In specific embodiments, the sensing can be performed using a delay based approach which races two signals to a data port and a clock port of a Flip-Flop circuit. Further, a charge trap transistor (CTT) non-volatile memory includes a write function that enables an initial random state to be overcome with a write operation to a known, repeatable margin. A differential wordline is used for margining a threshold voltage during write operations. In a read operation, a wordline voltage is set to a high gain point, which is a statistical average of a twin cell threshold voltage plus some additional overdrive voltage.
In embodiments, a sensing technique is disclosed with two identical paths which are raced against each other to determine data stored in a twin cell transistor pair. In the sensing technique, a path to ground (i.e., a power supply VSS) is connected using a bitline complement or a bitline true and enabled by a wordline activation in a memory array. The twin cell can be activated by a wordline voltage. The wordline voltage is set at a statistical average of the mean threshold voltage of the twin cell transistor pair plus some overdrive voltage. After programming (i.e., a write operation), one transistor is severely weakened. In this write operation, a threshold voltage (Vt) of a transistor of a twin cell is shifted upwards. The activation of the twin cell by the wordline voltage which resulted in a weakened transistor will significantly increase a delay in one path. In comparison to typical sense amplifiers, which take approximately 10 nanoseconds to sense data, the sensing circuits of the disclosure can sense data in approximately 1 nanosecond.
In the embodiment shown, the first delay block 20 receives an INPUT signal to the inverter 21, which delays the INPUT signal and outputs the delay signal to the inverter 22. The remaining inverters (i.e., inverters 22, 23, and 24) will provide subsequent delay signals in a serial manner, which then will be outputted as an OUTA signal to a logic cloud 60.
In
The first delay block 20 and the second delay block 30 have identical delay circuit paths with connections through a complement bitline signal BLC and a true bitline signal BLT, respectively. Therefore, the first delay block 20 and the second delay block 30 may have different delays relative to each other depending on the true bitline signal BLT and the complement bitline signal BLC (which are affected by the strength or weakness of the true transistor 40 and the complement transistor 50 threshold voltages (Vt)).
In
In operation, the twin cell transistor pair 65 is programmed such that one transistor of the twin cell transistor pair 65 (i.e., one of the true transistor 40 and the complement transistor 50) is weakened from the programming (i.e., the threshold voltage (Vt) is shifted up due to the programming). Based on the weakened transistor, one of the delay paths (i.e., the first delay block 20 or the second delay block 30) will have an increased delay.
During a read, the INPUT signal transitions from “0” to “1” (i.e., the read operation) and is passed through the first delay block 20 and the second delay block 30, where a race of the two input signals will result in one of the two input signals being delayed relative to the other input signal. As an example, if the INPUT signal to the first delay block 20 is delayed due to the weakened complement transistor 50 relative to the INPUT signal to the second delay block 30, then a “0” is loaded and latched in a latch circuit as the output Q signal. Alternatively, if the INPUT signal to the second delay block 30 is delayed due to the weakened true transistor 40 relative to the INPUT signal to the first delay block 20, then a “1” is loaded and latched in the latch circuit as the output Q signal. In
Similarly, in the delay based sensing circuit 70 of
In operation, the twin cell transistor pair 65 is programmed such that one transistor of the twin cell transistor pair 65 (i.e., one of the true transistor 40 and the complement transistor 50) is weakened from the programming (i.e., the threshold voltage Vt is shifted due to the programming). Based on the weakened transistor, one of the delay paths (i.e., the first delay block 20 or the second delay block 30) will have an increased delay. Therefore, during programming, the INPUT signal is passed through the first delay block 20 and the second delay block 30, where a race of the two input signals will result in one of the two input signals being delayed relative to the other input signal.
As an example, if the INPUT signal to the first delay block 20 is delayed due to the weakened complement transistor 50 relative to the INPUT signal to the second delay block 30, then the OUTA_PG is input to the data input of the D Flip-Flop Logic 110 after the OUTB_PG is input to the clock input of the D Flip-Flop Logic 110, thereby causing a “0” to be loaded and latched in the latch circuit as the output Q signal. Alternatively, if the INPUT signal to the second delay block 30 is delayed due to the weakened true transistor 40 relative to the INPUT signal to the first delay block 20, then the OUTB_PG is input to the clock input of the D Flip-Flop Logic 110 after the OUTA_PG is input to the data input of the D Flip-Flop Logic 110, thereby causing a “1” to be loaded and latched in the latch circuit as the output Q signal. In
In
Still referring to
In operation of the circuit as shown in
During programming (i.e., the write operation), the WRITE signal protects the cross-coupled PMOS transistors 172, 173. In this scenario, the cross-coupled PMOS transistors 172, 173 are turned ON with bitlines (i.e., the true bitline signal BLT and the complement bitline signal BLC) grounded during programming (i.e., the write operation). Further, during programming, the WRITE signal is a value of the power supply VCS. Also programming, the power supply VSL is a value of approximately 1.6 volts. During the read operation, the WRITE signal is a value of ground (i.e., VSS). The power supply VSL is also a value of ground (i.e., VSS) during the read operation, providing a path to ground through the charge trap transistor (CTT) pair.
The circuits described in the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the circuit and the method for sensing circuits for charge trap transistors of the present disclosure has been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the circuit and the method for sensing circuits for charge trap transistors uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Number | Name | Date | Kind |
---|---|---|---|
8742830 | Luo et al. | Jun 2014 | B2 |
9779783 | Anand | Oct 2017 | B2 |
9953727 | Fifield et al. | Apr 2018 | B1 |
20160217832 | Jayaraman | Jul 2016 | A1 |
20180075921 | Fifield et al. | Mar 2018 | A1 |
Entry |
---|
Hunt-Schroeder, Eric; Anand, Darren; Fitfield, John: Jacunski, Mark; Roberge, Michael; Pontius, Dale; Batson, Kevin; Kirihata, Toshiaki; 14nm FinFET 1.5Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming; Globalfoundries, VT USA, NY USA Symposium on VLSI Circuits Digest of Technical Papers; 2018. |
Number | Date | Country | |
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20210082532 A1 | Mar 2021 | US |