Read-write (R-W) circuits

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G11C11/409

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GPHYSICS G11Information storage G11CSTATIC STORES G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

Current Industry

G11C11/409Read-write (R-W) circuits

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Separated read BL scheme in 3T dram for read speed improvement
- Patent number 12,260,897
- Issue date Mar 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
In-memory computing circuit and method, and semiconductor memory
- Patent number 12,260,900
- Issue date Mar 25, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Heng-Chia Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal input buffer for effectively calibrating offset
- Patent number 12,260,901
- Issue date Mar 25, 2025
- FIDELIX CO., LTD.
- Jae Jin Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus with power-based data protection mechanism and methods fo...
- Patent number 12,260,895
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Bryce D. Cook
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus with memory process feedback
- Patent number 12,260,896
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Sujeet Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices and methods of processing security data thereof
- Patent number 12,260,918
- Issue date Mar 25, 2025
- Samsung Electronics Co., Ltd.
- Yoo-Jung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Complementary storage unit and method of preparing the same, and co...
- Patent number 12,260,902
- Issue date Mar 25, 2025
- Institute of Microelectronics, Chinese Academy of Sciences
- Qing Luo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device interface and method
- Patent number 12,253,943
- Issue date Mar 18, 2025
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub-word line driver placement for memory device
- Patent number 12,254,919
- Issue date Mar 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh and access modes for memory
- Patent number 12,254,957
- Issue date Mar 18, 2025
- Alberto Troia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random access memory circuit and read/write operation method...
- Patent number 12,254,920
- Issue date Mar 18, 2025
- UPBEAT TECHNOLOGY CO., LTD
- Bing-Chen Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier circuit architecture
- Patent number 12,254,921
- Issue date Mar 18, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Guifen Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Write driver boost circuit for memory cells
- Patent number 12,254,918
- Issue date Mar 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die termination of address and command signals
- Patent number 12,249,399
- Issue date Mar 11, 2025
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor-element-including memory device
- Patent number 12,249,366
- Issue date Mar 11, 2025
- Unisantis Electronics Singapore Pte. Ltd.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device capable of performing in-memory computing
- Patent number 12,249,365
- Issue date Mar 11, 2025
- Windbond Electronics Corp.
- Shu-Sen Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated assemblies comprising vertically-stacked decks with inte...
- Patent number 12,249,598
- Issue date Mar 11, 2025
- Micron Technology, Inc.
- Werner Juengling
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and nonvolatile memory for improving reliability of s...
- Patent number 12,249,388
- Issue date Mar 11, 2025
- Kioxia Corporation
- Katsuhiko Iwai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor-element-including memory device
- Patent number 12,245,417
- Issue date Mar 4, 2025
- Unisantis Electronics Singapore Pte. Ltd.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Layouts for sense amplifiers and related apparatuses and systems
- Patent number 12,243,579
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Yuko Watanabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reading memory
- Patent number 12,243,586
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yuhsiang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor apparatus with program operation control
- Patent number 12,242,732
- Issue date Mar 4, 2025
- SK hynix Inc.
- Hyung Jin Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated voltage demarcation (VDM) adjustment for memory device
- Patent number 12,243,577
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Yi-Min Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Fin field effect transistor sense amplifier circuitry and related a...
- Patent number 12,243,580
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Yuan He
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-up table initialize
- Patent number 12,242,852
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output driver level-shifting latch circuit for dual-rail memory
- Patent number 12,243,581
- Issue date Mar 4, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, memory system having the same and method of operatin...
- Patent number 12,236,995
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Jungmin You
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoder architectures for three-dimensional memory devices
- Patent number 12,236,999
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell biasing techniques during a read operation
- Patent number 12,237,002
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Andrea Locatelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power static random access memory
- Patent number 12,237,008
- Issue date Feb 25, 2025
- UNTETHER AI CORPORATION
- Katsuyuki Sato
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE
- Publication number 20250104761
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Sean S. Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
- Publication number 20250104760
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
Compute-In-Memory architecture using look-up tables
- Publication number 20250104762
- Publication date Mar 27, 2025
- Kneron Inc.
- Oscar Ming Kin Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM-ACCESS MEMORY STRUCTURE WITH HIGH SPEED AND WIDE BUS
- Publication number 20250104763
- Publication date Mar 27, 2025
- Invention And Collaboration Laboratory, Inc.
- Chao-Chun Lu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20250104759
- Publication date Mar 27, 2025
- KIOXIA Corporation
- Tsuneo Inaba
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING ROW DECODER ARRAY ARCHITECTURE
- Publication number 20250104764
- Publication date Mar 27, 2025
- Samsung Electronics Co., Ltd.
- Seungyeon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY CIRCUIT AND METHOD
- Publication number 20250104785
- Publication date Mar 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Gu-Huan LI
- G11 - INFORMATION STORAGE
Information Patent Application
CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...
- Publication number 20250095693
- Publication date Mar 20, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
BANK TO BANK DATA TRANSFER
- Publication number 20250095697
- Publication date Mar 20, 2025
- Lodestar Licensing Group LLC
- Perry L. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER...
- Publication number 20250095713
- Publication date Mar 20, 2025
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
BITLINE MULTI-LEVEL VOLTAGE SENSING CIRCUIT
- Publication number 20250095717
- Publication date Mar 20, 2025
- Korea Advanced Institute of Science and Technology
- Seong Hwan CHO
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTANCE CALIBRATION CIRCUIT, RESISTANCE CALIBRATION METHOD, AND...
- Publication number 20250095719
- Publication date Mar 20, 2025
- CXMT Corporation
- Xi WANG
- G11 - INFORMATION STORAGE
Information Patent Application
READ/WRITE CONVERSION CIRCUIT, AND WRITE DRIVER CIRCUIT
- Publication number 20250095721
- Publication date Mar 20, 2025
- CXMT Corporation
- Weibing SHANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DRIVER, MEMORY SYSTEM, AND OPERATING METHOD
- Publication number 20250095716
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Motoki TAMURA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING RESISTOR OFFSET CALI...
- Publication number 20250095711
- Publication date Mar 20, 2025
- Yangtze Memory Technologies Co., Ltd.
- Zhefan Li
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD
- Publication number 20250095715
- Publication date Mar 20, 2025
- Yangtze Memory Technologies Co., Ltd.
- Jianquan Jia
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATING METHOD THEREOF
- Publication number 20250095720
- Publication date Mar 20, 2025
- Macronix International Co., Ltd.
- Yu-Hsuan LIN
- G11 - INFORMATION STORAGE
Information Patent Application
RANDOM ACCESS MEMORY WITH METAL BRIDGES CONNECTING ADJACENT READ TR...
- Publication number 20250095722
- Publication date Mar 20, 2025
- UNITED MICROELECTRONICS CORP.
- Ming-Hsiu Wu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE
- Publication number 20250095708
- Publication date Mar 20, 2025
- Lodestar Licensing Group LLC
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES
- Publication number 20250095718
- Publication date Mar 20, 2025
- Micron Technology, Inc.
- Eric Carman
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR STORAGE DEVICE
- Publication number 20250087263
- Publication date Mar 13, 2025
- KIOXIA Corporation
- Manabu SATO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES WITH STACKING CIRCUITS AND METHODS OF OPERATING THEREOF
- Publication number 20250087287
- Publication date Mar 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Min-Shin Wu
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL DROP COMPENSATED MEMORY
- Publication number 20250087289
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Ferdinando Bedeschi
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT
- Publication number 20250087261
- Publication date Mar 13, 2025
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIVERSAL MEMORIES FOR IN-MEMORY COMPUTING
- Publication number 20250086443
- Publication date Mar 13, 2025
- Macronix International Co., Ltd.
- Feng-Min Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR TSV DATA OUTPUT CONTROL IN MULTIPLE CORE DIES
- Publication number 20250087262
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Kiyoshi Nakai
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND OPER...
- Publication number 20250087264
- Publication date Mar 13, 2025
- Samsung Electronics Co., Ltd.
- Seongjin Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL AND METHOD OF OPERATING THE SAME
- Publication number 20250087265
- Publication date Mar 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hon-Jarn LIN
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTR...
- Publication number 20250078911
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Fatma Arzum Simsek-Ege
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR STRUCTURE, ITS READ/WRITE CONTROLLING AND METHOD OF M...
- Publication number 20250081440
- Publication date Mar 6, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Qinghua HAN
- G11 - INFORMATION STORAGE

Read-write (R-W) circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Separated read BL scheme in 3T dram for read speed improvement

In-memory computing circuit and method, and semiconductor memory

Signal input buffer for effectively calibrating offset

Apparatus with power-based data protection mechanism and methods fo...

Apparatus with memory process feedback

Memory devices and methods of processing security data thereof

Complementary storage unit and method of preparing the same, and co...

Memory device interface and method

Sub-word line driver placement for memory device

Refresh and access modes for memory

Static random access memory circuit and read/write operation method...

Sense amplifier circuit architecture

Write driver boost circuit for memory cells

On-die termination of address and command signals

Semiconductor-element-including memory device

Memory device capable of performing in-memory computing

Integrated assemblies comprising vertically-stacked decks with inte...

Memory system and nonvolatile memory for improving reliability of s...

Semiconductor-element-including memory device

Layouts for sense amplifiers and related apparatuses and systems

Method for reading memory

Semiconductor apparatus with program operation control

Automated voltage demarcation (VDM) adjustment for memory device

Fin field effect transistor sense amplifier circuitry and related a...

Look-up table initialize

Output driver level-shifting latch circuit for dual-rail memory

Memory device, memory system having the same and method of operatin...

Decoder architectures for three-dimensional memory devices

Memory cell biasing techniques during a read operation

Low-power static random access memory

Patents Applicationslast 30 patents

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE

STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE

Compute-In-Memory architecture using look-up tables

DYNAMIC RANDOM-ACCESS MEMORY STRUCTURE WITH HIGH SPEED AND WIDE BUS

MEMORY DEVICE

MEMORY DEVICE HAVING ROW DECODER ARRAY ARCHITECTURE

NON-VOLATILE MEMORY CIRCUIT AND METHOD

CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...

BANK TO BANK DATA TRANSFER

APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER...

BITLINE MULTI-LEVEL VOLTAGE SENSING CIRCUIT

RESISTANCE CALIBRATION CIRCUIT, RESISTANCE CALIBRATION METHOD, AND...

READ/WRITE CONVERSION CIRCUIT, AND WRITE DRIVER CIRCUIT

MEMORY DRIVER, MEMORY SYSTEM, AND OPERATING METHOD

MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING RESISTOR OFFSET CALI...

NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD

MEMORY DEVICE AND OPERATING METHOD THEREOF

RANDOM ACCESS MEMORY WITH METAL BRIDGES CONNECTING ADJACENT READ TR...

APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE

CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES

SEMICONDUCTOR STORAGE DEVICE

MEMORY DEVICES WITH STACKING CIRCUITS AND METHODS OF OPERATING THEREOF

SIGNAL DROP COMPENSATED MEMORY

HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

UNIVERSAL MEMORIES FOR IN-MEMORY COMPUTING

APPARATUS FOR TSV DATA OUTPUT CONTROL IN MULTIPLE CORE DIES

NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND OPER...

MEMORY CELL AND METHOD OF OPERATING THE SAME

METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTR...

SEMICONDUCTOR STRUCTURE, ITS READ/WRITE CONTROLLING AND METHOD OF M...