SENSOR CIRCUITS FOR X-RAY IMAGERS

Abstract

An active pixel sensor includes thin-film transistors (TFTs) fabricated on a glass substrate, the TFTs include a gate electrode patterned on the glass substrate; a gate insulator layer disposed over the gate electrode; an amorphous indium-tin-zinc-oxide (a-ITZO) active semi-conductor layer disposed on the gate insulator layer and patterned over the gate electrode; and a source electrode and a drain electrode patterned from a metal layer deposited over the a-ITZO layer.

Description

TECHNICAL FIELD

The present disclosure relates generally to active pixel sensor (APS) circuits for indirect and direct X-ray imagers, and in particular, to high-performance APS circuits for next-generation large area, low noise, high resolution X-ray imagers.

BACKGROUND

Ideally, to achieve the best imaging performance in terms of higher detective quantum efficiency (DQE), an imaging system should be quantum limited, which means that the only source of noise is the x-ray quantum noise. However, this is seldom the case, as the conventional amorphous silicon (a-Si) thin film transistor (TFT)-based passive pixel sensor (PPS) backplane of x-ray imagers are a source of the additive electronic noise, which becomes a significant component of the total noise of the imaging system. While this high electronic noise can be tolerated for high exposure applications, such as mammography and general radiography, for low-dose imaging modalities, like digital breast tomosynthesis (DBT), it is crucial to reduce the electronic noise component as much as possible.

One approach to improve the noise performance (noise power spectrum (NPS)) is by employing an active pixel sensor (APS) instead of the currently used PPS backplane.

SUMMARY

According to one aspect of the invention, there is provided an active pixel sensor that includes thin-film transistors (TFTs) fabricated on a glass substrate. The TFTs include a gate electrode patterned on the glass substrate; a gate insulator layer disposed over the gate electrode; an amorphous indium-tin-zinc-oxide (a-ITZO) active semi-conductor layer disposed on the gate insulator layer and patterned over the gate electrode; and a source electrode and a drain electrode patterned from a metal layer deposited over the a-ITZO layer.

According to another aspect of the invention, there is provided an active pixel sensor imaging array for large-area x-ray imagers. The array includes a plurality of active pixel sensors arranged in rows and columns, wherein each of the plurality of active pixel sensors are coupled to an external readout circuit and includes a reset thin-film transistors (TFT), an amplifier TFT, and a readout TFT fabricated on a glass substrate. Each of the TFTs include a gate electrode patterned on the glass substrate; a gate insulator layer disposed over the gate electrode; an amorphous indium-tin-zinc-oxide (a-ITZO) active semi-conductor layer disposed on the gate insulator layer and patterned over the gate electrode; and a source electrode and a drain electrode patterned from a metal layer deposited over the a-ITZO layer; a photodetector fabricated over each of the active pixel sensors to form a vertically-stacked imaging pixel.

According to another aspect of the invention, there is provided an x-ray imaging device that includes an active pixel sensor imaging array having a plurality of active pixel sensors arranged in rows and columns, each of the plurality of active pixel sensors include thin-film transistors (TFTs) fabricated on a glass substrate. The TFTs include a gate electrode patterned on the glass substrate; a gate insulator layer disposed over the gate electrode; an amorphous indium-tin-zinc-oxide (a-ITZO) active semi-conductor layer disposed on the gate insulator layer and patterned over the gate electrode; and a source electrode and a drain electrode patterned from a metal layer deposited over the a-ITZO layer; a photodetector fabricated over the over each active pixel sensor forming vertically-stacked imaging pixel; and a readout circuit coupled to each of the plurality of active pixel sensors.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments of the invention will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and wherein:

FIGS. 1A-C illustrate cross-sectional views of an a-ITZO TFT, an organic photodiode, and an a-Si photodiode in accordance with an embodiment of the invention;

FIG. 2 illustrates an exemplary CsI:Tl scintillator/a-Si PD structure in accordance with an embodiment of the invention;

FIGS. 3A-C illustrate readout circuits for a MOS-based readout circuit, a charge integrator, and a trans-impedance amplifier (TIA), respectively, in accordance with an embodiment of the invention;

FIGS. 4A-B illustrate pixel sensor schematics and corresponding timing diagrams for a SF V-APS in accordance with an embodiment of the invention;

FIGS. 5A-B illustrate pixel sensor schematics and corresponding timing diagrams for a CS V-APS in accordance with an embodiment of the invention;

FIGS. 6A-B illustrate pixel sensor schematics and corresponding timing diagrams for a TA SO C-APS in accordance with an embodiment of the invention;

FIGS. 7A-B illustrate pixel sensor schematics and corresponding timing diagrams for a TA DO C-APS in accordance with an embodiment of the invention;

FIGS. 8A-B illustrate pixel sensor schematics and corresponding timing diagrams for a an a-ITZO APS and a TIA readout circuit in accordance with an embodiment of the invention;

FIGS. 9A-B illustrate a pixel pitch layout for an a-ITZO TFT C-APS and a cross-section view of the a-ITZO TFT C-APS layer, respectively, in accordance with an embodiment of the invention;

FIGS. 10A-B illustrate a pixel pitch layout for the a-ITZO TFT V-APS and a cross-section view of the a-ITZO TFT V-APS layer, respectively, in accordance with an embodiment of the invention;

FIGS. 11A-J illustrate cross-sectional views of the fabrication steps for the a-ITZO TFT C-APS according to the pixel layout shown in FIG. 9A in accordance with an embodiment of the invention;

FIG. 12 illustrates a cross-sectional view (B to B′) of the data line, V_RS and V_M pads according to the pixel layout shown in FIG. 9A in accordance with an embodiment of the invention;

FIG. 13 illustrates a cross-sectional schematic of TRD and the data line series resistance (RDATA) and parasitic capacitances (CDATA) for a TFT in accordance with an embodiment of the invention;

FIG. 14 illustrates a cross-section view of a DO a-ITZO TFT and the a-Si:H photodiode fabrication with no additional layer for GND bus line in accordance with an embodiment of the invention;

FIG. 15 illustrates a cross-section view of a DO a-ITZO TFT and the a-Si:H photodiode fabrication with an additional layer for GND bus line in accordance with an embodiment of the invention;

FIGS. 16A-F illustrate cross-sectional views of various configurations for an a-ITZO TFT C-APS in accordance with an embodiment of the invention;

FIGS. 17A-D depict schematics of equivalent circuits and cross-sectional views for a-Se TFT C-APS imager in accordance with an embodiment of the invention.

DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Thin film transistor (TFT)-based active pixel sensors (APS) for large-area, low noise, high resolution X-ray imagers are disclosed. Various TFT APS configurations disclosed herein include a source output (SO) current-mode APS (C-APS), a drain output (DO) current-mode C-APS (C-APS), a source follower (SF) voltage-mode APS (V-APS), and a common source (CS) V-APS. The disclosed TFT APSs use metal oxides for the active semiconductor layer. More specifically, an amorphous indium-tin-zinc-oxide (In—Sn—Zn—O) is used as it boasts of higher field effect mobilities (μ_eff>30 cm²/V s), lower off-current (I_OFF, <10⁻¹⁴ A) and a steep subthreshold slope (SS<200 mV/decade), and a low OFF-current (I_OFF<10⁻¹⁴ A), which are suitable for applications such as X-ray imagers. The active semiconductor layer may also be an amorphous indium-gallium-zinc-oxide (In—Ga—Zn—O).

The disclosed TFT APSs further include a top-illuminated photodetector such as, for example, an organic photodiode (OPD), an amorphous silicon p+-i-n+ photodiode (a-Si p+-i-n+ PD), a photoconductive material such as amorphous selenium, mercury iodide, or an organometallic halide perovskite. The photodiode structures may be configured as top-anode (TA) or top-cathode (TC). Using a stack-up structure the disclosed TFT APS has a 50-micrometer pixel pitch.

An x-ray imager employing an imaging array of the disclosed TFT APSs includes readout circuitry for generating images, including, for example, a MOS-based readout circuit, a charge integrator, and a trans-impedance amplifier.

Device Fabrications

A. Amorphous Indium-Tin-Zinc-Oxide Thin-Film Transistor

The fabrication process of the back-channel-etched a-ITZO TFT includes first forming a gate electrode (Mo) on a glass substrate. After patterning the gate electrode, a 470-nm-thick amorphous silicon dioxide (SiO_x) as a gate insulator is deposited using plasma-enhanced chemical vapor deposition (PECVD). Next, a 30-nm-thick a-ITZO film is deposited by DC sputtering with an O₂ flow ratio of 5%, subsequently patterned by a wet etching process, and then annealed at 300° C. Afterward, the source and drain electrodes (Mo) are deposited by sputtering and patterned by phosphoric acid, acetic acid, and nitric acid etchant. A second annealing process at 200° C. is applied in ambient air. Finally, an organic or inorganic film acting as a passivation layer is deposited over the a-ITZO TFT. FIG. 1 (a) shows a cross-sectional view of the a-ITZO TFT.

B. Photodiodes (PDs)—Indirect Imaging

Organic Photodiode (OPD): The OPD fabrication process is briefly summarized. A combination of Molydenum (Mo) for the source and drain electrodes and ITO is used as the bottom cathode electrode. A synthesized polyethylenimine ethoxylated (PEIE) solution is spin-coated on the top of ITO and annealed at 100° C. to form a 10-nm-thick layer. Afterward, a 90-nm-thick phenyl C61-butyric acid methyl ester (PCBM) layer (electron acceptor) is deposited by spin coating. Subsequently, a 90-nm-thick poly (3-hexylthiophene) (P3HT) (electron donor) is transferred by a double transfer stamping method from a high-surface-energy polydimethylsiloxane stamp onto the PCBM/PEIE/ITO/Mo structure. The P3HT/PCBM/PEIE/ITO/Mo structure is next annealed at 110° C. to generate an inter-diffusion layer between P3HT and PCBM (P3HT/inter-diffusion heterojunction/PCBM/PEIE/ITO/Mo). Finally, a 5-nm-thick MoO₃, a 10-nm-thick Ag, and a 35-nm-thick MoO₃ are sequentially deposited on the top to form a transparent anode electrode. The OPD is illuminated through the top transparent anode. FIG. 1(b) shows the cross-sectional view of the OPD.

Amorphous Silicon p+-i-n+ Photodiode: The fabrication process of the a-Si p+-i-n+ PD is briefly summarized. Mo is used for the source and drain electrodes as the bottom cathode electrode. Using PECVD, a 50-nm-thick heavily P-doped (n+) layer, a 1-μm-thick undoped/intrinsic a-Si layer, and a 50-nm-thick heavily B-doped (p+) layer are sequentially deposited. Next, ITO, a transparent anode electrode, is deposited on the top of the p+ layer. Then, the a-Si p+-i-n+ PD is annealed at 150° C. to suppress the excess current coming from extrinsic defect generation. The a-Si p+-i-n+ PD is top-illuminated through the transparent ITO anode. This PD structure is adopted to realize a low dark current under reverse bias and high quantum efficiency (Q.E.). FIG. 1(c) shows the cross-sectional view of the a-Si PD.

Signal Generation and Transfer in Active Pixel Sensor

An example of a CsI:Tl scintillator/a-Si PD structure is shown in FIG. 2. In the a-Si PD, the ITO/B-doped p⁺ a-Si and Mo/P-doped n⁺ a-Si layers are considered as an anode and a cathode, respectively. First, x-rays projected on the scintillator will generate visible light/photon emission whose quantity is defined by the flux and energy of x-rays. The fiber optic plate (FOP) is used to convey the photons emitted from the scintillator to the a-Si PD. Next, the a-Si PD, subjected to reverse-biased condition, will absorb the photons, and produce electron-hole pairs, resulting in carriers. Electrons are attracted by the high-voltage a-Si PD cathode; holes move toward to the low-voltage a-Si PD anode. The movement of holes and electrons forms a-Si PD photocurrents, flowing from the a-Si PD cathode to anode. The density of the photo-generated carriers is linearly proportional to the density (flux) of the photons. Subsequently, PPS and/or APS act as mediators to convert different levels of photo-induced signals/photocurrents into different levels of electrical signals (currents and voltages). The a-Si PD can have TA or TC structure. In both configurations V_RD is used to activate readout TFT (T_RD), allowing the transfer of the photo-induced signals from a pixel to the external readout circuit. V_PD and V_REF of the readout circuit are voltages used to reversely bias the a-Si PD. In TA structure, V_PD and V_REF are set at a low voltage and a high voltage, respectively; the cathode of the a-Si PD is connected to the TFT (T_RD), and the anode is illuminated through a transparent indium-tin oxide (ITO)/p⁺ a-Si electrode. In TC configuration, V_PD and V_REF are set at a high voltage and a low voltage, respectively; the connection of the a-Si PD is reversed and the diode is illuminated through a transparent ITO layer/n⁺ a-Si electrode.

Readout Circuits

As shown in FIGS. 3A-C, readout circuits for the disclosed TFT APS include a MOS-based readout circuit, a charge integrator, and a trans-impedance amplifier (TIA). The MOS-based readout circuit shown in FIG. 3A converts the voltage at its input node into the corresponding output voltage. The MOS-based readout circuit has a simple and compact structure as compared to the charge integrator and trans-impedance amplifier, but doesn't provide any signal amplification.

The charge integrator shown in FIG. 3B consists of an operational amplifier op-amp, a feedback capacitor (C_F), and an external reset switch (SW). Another possible readout mechanism is the trans-impedance amplifier shown in FIG. 3C, which has a circuit is similar to that of the charge integrator but consists of a feedback resistance (R_F) instead of the switch. In essence, both the readout mechanisms can be considered to convert current into output voltages.

There are some differences amongst the two readout schemes. If the input signal is small, a large feedback resistance is needed for the trans-impedance to produce a utilizable output voltage. With the charge-integrator circuit, the timing can be changed by modulating the switch to enable longer readout duration for smaller input signals. At the same time, the reset switch in the charge integrator circuit can give rise to large switching noise which can be a disadvantage for low noise applications like digital breast tomosynthesis. Another advantage of the transimpedance amplifier is that the large integration feedback capacitor can be elimated making it cheaper for fabrication.

Voltage-Mode Active Pixel Sensor and MOSFET Readout Circuit

FIGS. 4A and 4B and FIGS. 5A and 5B show the pixel sensor schematics and corresponding timing diagrams for SF and CS V-APS, respectively. In this example, the APS consists of one PD, one storage capacitor/capacitance (C_ST), and three a-ITZO TFTs (T_RESET, T_AMP, and T_READ). The PD detects photoinduced signals (electrons) caused by photons emitted by a scintillator subjected to X-ray radiation. Both C_ST and C_PD (represent pixel sensor total capacitance C_PIX) store detected photoinduced signals. T_RESET is used to remove photoinduced signals stored in C_PIX (i.e., to reset the gate voltage of T_AMP, V_IN, to an initial value). T_AMP is operated to amplify detected photoinduced signals. T_READ controls the transfer of amplified photoinduced signals from the pixel sensor to the external readout circuit.

The readout circuit is composed of one n-type or p-type MOSFET (T_BIAS, n-MOSFET and p-MOSFET for SF V-APS and CS V-APS, respectively) and a column capacitor/capacitance (C_COL), which includes the column wire capacitor and total gate-to-source capacitors (C_GS) of T_READ. T_BIAS acts as an active load and C_COL stores readout voltages (V_OUT).

For large-area imaging applications, such as X-ray imagers, the operation for illustrated APS is divided into three periods, reset (t_RS), integration (t_INT), and readout (t_RD).

Reset Period: V_RS is high (10 V) to turn ON T_RESET and V_RD is low (−5 V) to keep T_READ OFF. Hence, electrons (photoinduced signals) stored in C_PIX are removed to V_DD through T_RESET. At the same time, V_IN (the PD cathode) increases to V_DD (stored by C_ST and C_PD, i.e., C_PIX). A reverse-biased condition for PD (anode: V_PD, cathode: V_DD; V_DD>V_PD) is hence established. To prevent I_OFF of T_READ, which is very low, from affecting V_OUT, the always-on n-type T_BIAS in SF V-APS maintains V_OUT at ground; the always-on p-type T_BIAS in CS V-APS keeps V_OUT at V_DD.

Integration Period: Both V_RS and V_RD are low (−5 V) to turn OFF T_RESET and T_READ, respectively. In the meantime, X-rays are projected on APS and absorbed by a scintillator, which subsequently releases photons. These photons strike PD generating electron-hole pairs, which are separated into electrons and holes by the electrical field inside PD. Different flux of photons induces different quantities of electron-hole pairs. Holes move toward to the low-voltage PD anode/V_PD; electrons are attracted by the high-voltage PD cathode/V_IN and stored in C_PIX. The movement of holes and electrons forms PD photocurrents flowing from the PD cathode to the PD anode, which accordingly decreases V_IN during t_INT. Again, to prevent I_OFF of T_READ from affecting V_OUT, the always-on T_BIAS in SF V-APS and in CS V-APS holds V_OUT at ground and at V_DD, respectively.

Readout Period: V_RS is still low (−5 V) to turn OFF T_RESET and V_RD goes high (10 V) to activate T_READ, and V_IN obtained by the end of integration period are converted into a corresponding V_OUT, which is then processed by the external circuitry and software to display X-ray images. The V_IN-to-V_OUT conversion process in SF V-APS is different from that in CS V-APS. In SF V-APS, T_AMP drains out a current flowing into the readout circuit through T_READ, so COOL is thus charged up from the ground level to higher voltages based on different V_IN, namely, a higher V_IN results in a higher V_OUT. In CS V-APS, T_AMP sinks a current from the readout circuit through T_READ, so that C_COL is hence discharged from V_DD to lower voltages based on different V_IN, which means that a higher V_IN leads to a lower V_OUT.

Current-Mode Active Pixel Sensor and Readout Circuit

FIGS. 6A and 6B and FIGS. 7A and 7B show pixel sensor schematics and corresponding examples of timing diagrams for TA SO and TA DO C-APS, respectively. The APS consists of one a-Si PD and three a-ITZO TFTs (T_RS, T_AMP, and T_RD). TA SO C-APS generates currents flowing into the readout circuit and requires four voltage signal lines (V_DD, V_PD, V_RS, and V_RD). On the other hand, TA DO C-APS sinks currents flowing out of the readout circuit and requires five voltage signal lines (V_DD, V_PD, V_RS, V_RD, and ground). Due to the opposite current directions in both C-APS, the polarities of voltages generated by the readout circuit are also inverse. The circuit model for the a-Si PD is composed of a basic diode (D), a shunt resistor (R_SH) that can affect the reverse-biased dark current (I_DARK), a photodiode capacitor (C_D), a current source (I_PH) imitating photocurrents (photo-induced signals) impinging on the a-Si PD, and a series resistor (R_S) that dominates the forward-biased current-voltage (I-V) characteristics. C_D and all parasitic capacitors (C_PAR), such as gate-to-drain and gate-to-source capacitors (C_GD and C_GS) of T_AMP and C_GS of T_RS, connected to the a-Si PD cathode will store photo-induced signals. In C-APS, T_RS is used to reset the photo-induced signals accumulated in C_D and C_PAR (i.e. pixel capacitor, C_PIX=C_D+C_PAR) to zero. T_AMP amplifies detected photo-induced signals and acts as a constant current source (I_OUT) whose value is controlled by its gate voltage (V_IN). T_RD is treated like an access controlling the connection between APS and the external readout circuitry.

In terms of readout circuitries, both charge integrator and transimpedance amplifier can be considered to convert currents into voltages. In this example, a charge integrator is used, which includes an operational amplifier (OPAMP), a feedback capacitor (C_FB), and an external reset switch (SW_ER). The OPA provides a high gain to sustain the virtual short between its positive and negative inputs. Herein, the positive input of the OPA is connected to ground, which implies that the negative input can be seen as a virtual ground. C_FB integrates I_OUT to produce readout voltages (V_OUT) used for reconstructing x-ray images by the back-end signal processing. SW_ER is used to reset V_OUT.

The operation of TA SO C-APS, containing three stages, reset (t_RS), integration (t_INT), and readout (t_RD) is described as follows.

Reset stage: V_RS and V_RD are set at high and low levels, respectively, so that T_RS is on and T_RD is off to isolate APS and the charge integrator (e.g. the readout circuit) from each other. Hence, detected electrons in the last frame, stored by C_PIX, are forced to move to V_DD, a high-voltage source, through T_RS, increasing the gate voltage of T_AMP (V_IN, also the cathode voltage of the a-Si PD) to V_DD. Because V_PD, the anode voltage of the a-Si PD, is set to a value lower than V_DD, the a-Si PD is reversely biased (ensuring the device is operated in photoconductive mode). At the same time, for both TA SO and TA DO C-APS, SW_ER is activated, so V_OUT is shorted to the negative input (V_M) of the OPA which is a virtual ground. V_OUT is hence kept at the ground level.

Integration stage: V_RS is set low to turn off T_RS and V_RD remains at low level to keep T_RD off. Next, photons, produced by the CsI:Tl scintillator under x-ray exposure, will impinge the a-Si PD, leading to the production of photo-induced electrons-hole pairs which are then separated to electrons and holes by the reverse bias established during Reset Stage. Electrons go to the high-voltage a-Si PD cathode/V_IN and are stored in C_PIX; holes are driven to the low-voltage a-Si PD anode/V_PD. The resulting photocurrents, flowing from the cathode to anode, will decrease V_IN during t_INT. V_OUT remains shorted to V_M, the virtual ground. t_INT can be adjusted for a given applications.

Readout stage: Before APS and the charge integrator are connected together, SW_ER must be turned off, which allows C_FB to integrate I_OUT to produce V_OUT. Then, V_RS is still held at low and V_RD changes to high to turn T_RD on. For TA SO C-APS, the source voltage (V_S) of T_AMP is fixed during Read stage because of the connection with V_M, and T_AMP produces I_OUT flowing into the charge integrator through T_RD. Since V_DD is higher than V_IN minus the threshold voltage of T_AMP (V_{TH_AMP}), acquired at the end of Integration stage, T_AMP is operated in saturation region.

Hence, I_OUT can be expressed as:

$\begin{array}{cc}{I}_{\mathrm{OUT}}=\frac{1}{2}{\mu }_{\mathrm{EFF}}C_{\mathrm{OX}}\frac{W}{L}{\left(V_{\mathrm{IN}}-V_S-V_{\mathrm{TH}\_\mathrm{AMP}}\right)}^2& \left(1\right)\end{array}$

where μ_EFF is the field-effect mobility, C_OX is the oxide capacitance per unit area, and W and L are the channel width and length of T_AMP, respectively. V_OUT can be calculated by:

$\begin{array}{cc}{I}_{\mathrm{OUT}}t_{\mathrm{RD}}=C_{\mathrm{FB}}\left(V_M-V_{\mathrm{OUT}}\right)=I_{\mathrm{OUT}}t_{\mathrm{RD}}=C_{\mathrm{FB}}\left(0-V_{\mathrm{OUT}}\right)\Rightarrow V_{\mathrm{OUT}}=-\frac{I_{\mathrm{OUT}}t_{\mathrm{RD}}}{C_{\mathrm{FB}}}& \left(2\right)\end{array}$

Notably, V_OUT is negative in TA SO C-APS. For TA DO C-APS, the drain voltage (V_D) of T_AMP is fixed during Readout stage because of the connection with V_M, and T_AMP produces I_OUT flowing out of the charge integrator via T_READ. V_D and V_IN can influence the operation region of T_AMP and thus I_OUT calculation. If V_D>(V_IN−V_TH), I_OUT can be computed by:

$\begin{array}{cc}{I}_{\mathrm{OUT}}=\frac{1}{2}{\mu }_{\mathrm{EFF}}C_{\mathrm{OX}}\frac{W}{L}\left[2\left(V_{\mathrm{IN}}-V_{\mathrm{SS}}-V_{\mathrm{TH}\_\mathrm{AMP}}\right)\left(V_D-V_{\mathrm{SS}}\right)-{\left(V_D-V_{\mathrm{SS}}\right)}^2\right]& \left(3\right)\end{array}$

where V_SS is the source voltage of T_AMP. If V_D<(V_IN−V_TH), I_OUT can be given by:

$\begin{array}{cc}{I}_{\mathrm{OUT}}=\frac{1}{2}{\mu }_{\mathrm{EFF}}C_{\mathrm{OX}}\frac{W}{L}{\left(V_{\mathrm{IN}}-V_{\mathrm{SS}}-V_{\mathrm{TH}\_\mathrm{AMP}}\right)}^2& \left(4\right)\end{array}$

V_OUT can also be calculated by:

$\begin{array}{cc}{I}_{\mathrm{OUT}}t_{\mathrm{RD}}=C_{\mathrm{FB}}\left(V_{\mathrm{OUT}}-V_M\right)\Rightarrow V_{\mathrm{OUT}}=\frac{I_{\mathrm{OUT}}t_{\mathrm{RD}}}{C_{\mathrm{FB}}}& \left(5\right)\end{array}$

In contrast with TA SO C-APS, V_OUT is positive in TA DO C-APS. From the system design point of view, for a given I_OUT, which is controlled by C-APS, adjusting t_RD and C_FB values can modulate V_OUT, which is then translated into digital number (DN representing grayscale) by analog-to-digital converters (ADCs) by the back-end signal processing.

The timing diagram used here is based on a rolling shutter method. Reset Stage for pixels in x-ray imagers is executed row-by-row, starting from the top to the bottom of TFT arrays; when reset for pixels in the last rows is done, Readout Stage of pixels then also proceeds row-by-row from the top to the bottom of TFT arrays. For a row of pixels, the timing gap between Reset Stage and Readout Stage means t_INT (Integration stage).

Active Pixel Sensor and Transimpedance Amplifier

FIGS. 8A-B show the pixel sensor schematics and corresponding timing diagrams for an embodiment using an a-ITZO APS and a TIA readout circuit. The APS consists of one PD, one storage capacitor (C_ST), and three a-ITZO TFTs (T_RESET, T_AMP, and T_READ). The PD detects photo-induced signals (electrons) caused by photons absorbed by an OPD layer. Both C_ST and C_PD (represent pixel sensor total capacitance, C_PIX) store detected photo-induced signals. T_RESET is used to remove photo-induced signals stored in C_PIX (i.e. to reset the gate voltage of T_AMP, V_IN, to an initial value). T_AMP is operated to amplify detected photo-induced signals. T_READ controls the transfer of amplified photo-induced signals from the pixel sensor to the external readout circuit.

For large-area imaging applications, such as X-ray imagers, the operation for illustrated APS is divided into three periods, reset (t_RS), integration (t_INT), and readout (t_RD):

Reset period: V_RS is set high (10 V) to turn on T_RESET and V_RD is low (−5 V) to keep T_READ off to isolate APS from the TIA readout circuit. Next, electrons (photo-induced signals) stored in C_PIX are moved to V_DD through T_RST. Hence, V_IN (the PD cathode) increases to V_DD. A reverse-biased condition for OPD (anode: V_PD, cathode: V_DD; V_DD>V_PD) is kept while Vout is kept at the ground level.

Integration period: Both V_RS and V_RD are set low (−5 V) to turn off T_RST and T_READ, respectively. In the meantime, illuminated light (e.g. X-rays) are absorbed by OPD and generate excitons. These excitons are dissociated into electron-hole pairs which are separated into electrons and holes by the electrical field inside OPD formed by reverse bias. Different flux of photons induces different quantities of electron-hole pairs. Holes move toward to the low-voltage PD anode/V_PD; electrons are attracted by the high-voltage PD cathode/V_IN and stored in C_PIX. The movement of holes and electrons forms PD photocurrents flowing from the PD cathode to the PD anode, which accordingly decreases V_IN during t_INT.

Readout period: V_RS is kept low (−5 V) to turn off T_RST and V_RD goes high (10 V) to activate T_READ, and V_IN obtained by the end of integration period are converted into a corresponding V_OUT which is then processed by the TIA external circuit. The source voltage (V_S) of T_AMP is fixed during readout stage because of the connection with TIA, and T_AMP produces I_OUT flowing into the TIA external circuit through T_RD. Since V_DD is higher than Vin minus the threshold voltage of T_AMP (V_{TH_AMP}) acquired at the end of Integration stage, T_AMP is operated in saturation region. Hence, I_OUT can be expressed as:

$\begin{array}{cc}{I}_{\mathrm{OUT}}={\mu }_{\mathrm{eff}}C_{\mathrm{ox}}\frac{W}{2L}{\left(V_{\mathrm{IN}}-V_S-V_{\mathrm{TH}\_\mathrm{AMP}}\right)}^2& \left(1\right)\end{array}$

where μ_eff is the field-effect mobility, and W and L are the channel width and length of T_AMP, respectively. V_OUT can be calculated by:

V _OUT =−I _OUT R _F  (2)

By knowing the maximum expected I_OUT, R_F is selected to optimize the signal-to-noise ratio.

The capacitance C_F between the OP Amps inverting input and V_OUT stabilizes the circuit against potential oscillation problem or gain peaking due to impedance mismatch when operating frequency varies.

Pixel Circuit Layout and Fabrication Process

FIG. 9A illustrates a 50 μm pixel pitch layout for the a-ITZO TFT C-APS. Considering the TFT layout, the half-Corbino TFT structure with the inner-drain configuration is adopted to acquire higher operation current (I_OUT) for T_AMP. The VIA is used to connect the photodiode bottom electrode to T_AMP gate and T_RS source. V_M is the data line output voltage connected to the negative input node of the op-amp. On the other hand, the outer-drain bias condition is used for T_RD to reduce the gate-to-source capacitance and data line parasitic capacitance. The critical dimension (minimum width) of metal lines is 3 μm. FIG. 9B illustrates a cross-section view of the a-ITZO TFT C-APS layer.

FIG. 10A illustrates a 50 μm pixel pitch layout for the a-ITZO TFT V-APS. FIG. 10B illustrates a cross-section view of the a-ITZO TFT V-APS layer.

FIG. 11A-J illustrates a 10-mask processing steps and cross-sectional views (A to A′) of the C-APS pixel and the a-Si:H photodiode fabrication according to the pixel layout shown in FIG. 9A. First, metal #1 (Mo, for gate electrodes of T_RS, T_AMP, and T_RD, and V_RS and V_RD lines) is formed by DC sputtering on glass substrate. The standard photolithography is used for metal definition (mask #1). Next, a 470-nm amorphous silicon oxide (a-SiO_x) as the gate insulator is deposited using PECVD. Then, a 30-nm a-ITZO films DC sputtered using the optimized O₂ flow ratio of 5%, subsequently patterned into active islands by a wet etching process (mask #2) and annealed at 300° C. The gate contact VIA is defined (mask #3) to connect V_IN and the gate of T_AMP using the reactive-ion etching (RIE). At the same time, contact VIAs for V_RS and V_RD pads are created. Afterward, metal #2 (Mo, for S/D electrodes of T_RS, T_AMP, and T_RD and V_DD and V_M lines) are deposited by sputtering and patterned using the back channel etch process (mask #d). A 3 μm a-SiO_x passivation layer (PSV #1) is deposited over the fabricated a-ITZO TFTs. A contact VIA is generated using RIE (mask #5) to electrically connect the source electrode of T_RS/the gate electrode of T_AMP to the patterned bottom Mo electrode (cathode) of the a-Si:H photodiode (mask #6). Also, VIAs for the four contact pads (V_RS, V_RD, V_M, and V_DD) are etched using mask #5. The opaque bottom electrode of a-Si:H photodiode also serves as a light shield for a-ITZO TFTs. Using PECVD, a 50-nm n+ layer, a 1-μm thick undoped/intrinsic a-Si:H layer, and a 50-nm p+ layer are sequentially deposited and patterned by photolithography (mask #7). A second passivation layer (PSV #2) can be deposited on top of the p+ layer. Next, the photodiode top electrode area and VIAs for all four contact pads are defined (mask #8). A transparent indium-tin oxide (ITO) layer is deposited as the top electrode of the a-Si:H photodiode. Then, the a-Si:H photodiode is annealed at 150° C. to suppress the excess current coming from extrinsic defect generation. The ITO layer is patterned out of the active-matrix array as the top conductive layer for four contact pads (mask #9). After etching ITO, the ITO needs to be thermally annealed at around 230° C. [209]. A third passivation layer (PSV #3) is deposited to protect the entire structure. Finally, contact VIAs for pads VRS, VRD, VM, VDD and VPD are defined out of the active-matrix array by etching the PSV #3 (mask #10). A 150-μm CsI:Tl scintillator can be directly deposited (or attached using a FOP) on top of the passivated a-Si:H photodiode layer to complete the detector fabrication.

FIG. 12 shows the final cross-sectional view (B to B′) of the data line, V_RS and V_M pads after the entire process according to the pixel layout shown in FIG. 9A. The cross-sectional view (C to C′) of the V_DD and V_RD pads (not shown) is the same as FIG. 12 by replacing V_RS with V_RD and V_M with V_DD.

It should be noted that the a-Si:H photodiode bottom electrode is also used as a light shield for a-ITZO TFTs. At the same time, since the photodiode bottom electrode voltage is the same as the gate voltage of T_AMP, T_AMP behaves like a dual-gate TFT with top and bottom gates biased together.

FIG. 13 illustrates a cross-sectional schematic of T_RD and the data line series resistance (R_DATA) and parasitic capacitances (C_DATA). As shown in FIG. 13, based on the layout described above, C_DATA consists of the gate-to-source overlapping capacitance (C_GS) of T_RD, the overlapping capacitance (C_RD) between the data line and V_RD, the overlapping capacitance (C_RS) between the data line and V_RS, and the overlapping capacitance (C_PSV) between the data line and the a-Si:H photodiode bottom electrode. Hence, C_DATA can be estimated by

C _DATA =N(C_G+C_RD+C_RS+C_PSV)=N[C_OX(L_SL+2L²)+C_OX,PSV(a_pixL)]

where N is the number of pixels on a data line, L is the both process critical dimension and line width (3 μm), L_S is the length of the T_RD source electrode (˜15 μm), a_pix is the pixel pitch (50 μm), Cox is the gate oxide (470 nm a-SiOx) capacitance (7.34 nF/cm2), Cox,PSV is the passivation layer (e.g., 3 μm a-SiOx) capacitance (1.15 nF/cm2).

FIG. 14 illustrates a cross-sectional view of a DO a-ITZO TFT and the a-Si:H photodiode fabrication with no additional layer for GND bus line. The 10-mask processing steps for this configuration are as follows.

First, metal #1 (Mo, for gate electrodes of T_RS, T_AMP, and T_RD, and V_RS and V_RD lines) is formed by DC sputtering on glass substrate. The standard photolithography is used for metal definition (mask #1). Next, amorphous silicon oxide (a-SiOx) as the gate insulator is deposited using PECVD. Then, a thin a-ITZO film is DC sputtered using the optimized O₂ flow ratio of 5%, subsequently patterned into active islands by a wet etching process (mask #2) and annealed at 300° C. The gate contact VIA is defined (mask #3) to connect V_IN and the gate of T_AMP using the reactive-ion etching (RIE). At the same time, contact VIAs for V_RS and V_RD pads are created. Afterward, metal #2 (Mo, for S/D electrodes of T_RS, T_AMP, and T_RD and GND, V_SS and V_M lines) are deposited by sputtering and patterned using the back channel etch process (mask #4). A a-SiOx passivation layer (PSV #1) is deposited over the fabricated a-ITZO TFTs. A contact VIA is generated using RIE (mask #5) to electrically connect the source electrode of T_RS/the gate electrode of T_AMP to the patterned bottom Mo electrode (cathode) of the a-Si:H photodiode (mask #6). Also, VIAs for the five contact pads (GND, V_RS, V_RD, V_M, and V_SS) are etched using mask #5. The opaque bottom electrode of a-Si:H photodiode also serves as a light shield for a-ITZO TFTs. Using PECVD, a 50-nm n+ layer, a 1-μm thick undoped/intrinsic a-Si:H layer, and a 50-nm p+ layer are sequentially deposited and patterned by photolithography (mask #7). A second passivation layer (PSV #2) can be deposited on top of the p+ layer. Next, the photodiode top electrode area and VIAs for all four contact pads are defined (mask #8). A transparent indium-tin oxide (ITO) layer is deposited as the top electrode of the a-Si:H photodiode. Then, the a-Si:H photodiode is annealed at 150° C. to suppress the excess current coming from extrinsic defect generation. The ITO layer is patterned out of the active-matrix array as the top conductive layer for four contact pads (mask #9). After etching ITO, the ITO needs to be thermally annealed at around 230° C. A third passivation layer (PSV #3) is deposited to protect the entire structure. Finally, contact VIAs for pads GND, V_RS, V_RD, V_M, V_SS and V_PD are defined out of the active-matrix array by etching the PSV #3 (mask #10). A 150-nm CsI:Tl scintillator can be directly deposited (or attached using a FOP) on top of the passivated a-Si:H photodiode layer to complete the x-ray detector fabrication.

FIG. 15 illustrates a cross-sectional view of a DO a-ITZO TFT and the a-Si:H photodiode fabrication with an additional layer for GND bus line. The 12-mask processing steps for this configuration are as follows.

First, metal #1 (Mo, for gate electrodes of T_RS, T_AMP, and T_RD, and V_RS and V_RD lines) is formed by DC sputtering on glass substrate. The standard photolithography is used for metal definition (mask #1). Next, amorphous silicon oxide (a-SiOx) as the gate insulator is deposited using PECVD. Then, a thin a-ITZO film is DC sputtered using the optimized O₂ flow ratio of 5%, subsequently patterned into active islands by a wet etching process (mask #2) and annealed at 300° C. The gate contact VIA is defined (mask #3) to connect V_IN and the gate of T_AMP using the reactive-ion etching (RIE). At the same time, contact VIAs for V_RS and V_RD pads are created. Afterward, metal #2 (Mo, for S/D electrodes of T_RS, T_AMP, and T_RD and GND, V_SS and V_M lines) are deposited by sputtering and patterned using the back channel etch process (mask #4). A a-SiOx passivation layer (PSV #1) is deposited over the fabricated a-ITZO TFTs. Contact VIAs for gate electrode of T_AMP (V_IN) and GND bus line are generated using RIE (mask #5). GND bus lines are deposited and defined on top of PSV #1 (mask #6) followed by deposition of another PSV layer (PSV #2), VIA for V_IN is defined (mask #7) to electrically connect the source electrode of T_RS/the gate electrode of T_AMP to the patterned bottom Mo electrode (cathode) of the a-Si:H photodiode (mask #8). Also, VIAs for the five contact pads (GND, V_RS, V_RD, V_M, and V_SS) are etched using mask #7. The opaque bottom electrode of a-Si:H photodiode also serves as a light shield for a-ITZO TFTs. Using PECVD, a 50-nm n+ layer, a 1-μm thick undoped/intrinsic a-Si:H layer, and a 50-nm p+ layer are sequentially deposited and patterned by photolithography (mask #9). A third passivation layer (PSV #3) can be deposited on top of the p+ layer. Next, the photodiode top electrode area and VIAs for all four contact pads are defined (mask #10). A transparent indium-tin oxide (ITO) layer is deposited as the top electrode of the a-Si:H photodiode. Then, the a-Si:H photodiode is annealed at 150° C. to suppress the excess current coming from extrinsic defect generation. The ITO layer is patterned out of the active-matrix array as the top conductive layer for four contact pads (mask #11). After etching ITO, the ITO needs to be thermally annealed at around 230° C. The last passivation layer (PSV #4) is deposited to protect the entire structure. Finally, contact VIAs for pads GND, V_RS, V_RD, V_M, V_SS and V_PD are defined out of the active-matrix array by etching the PSV #3 (mask #12). A 150-μm CsI:Tl scintillator can be directly deposited (or attached using a FOP) on top of the passivated a-Si:H photodiode layer to complete the x-ray detector fabrication.

FIGS. 16A-F illustrate various cross-sections for an a-ITZO TFT C-APS. FIG. 16A illustrates a cross-section of a DO a-ITZO TFT C-APS (no photodiode) with a GND bus line on S/D layer. FIG. 16B illustrates a cross-section of a DO a-ITZO TFT C-APS (no photodiode) with a GND bus line on a separate layer. FIG. 16C illustrates a cross-section of DO a-ITZO TFT C-APS (w/a-Si:H photodiode) with a GND bus line on S/D layer. FIG. 16D illustrates a cross-section of a DO a-ITZO TFT C-APS (w/a-Si:H photodiode) with a GND bus line on a separate layer. FIG. 16E illustrates a cross-section of a DO a-ITZO TFT C-APS (w/OPD) with a GND bus line on S/D layer. FIG. 16F illustrates a cross-section of a DO a-ITZO TFT C-APS (w/OPD) with a GND bus line on a separate layer.

Current-Mode Active Pixel Sensor for Direct Imaging

The disclosed TFT APS may be integrated with photodetectors configured for direct image sensing. In one example, a-Se detector is incorporated with a current-mode APS (C-APS) backplane. A schematic of an equivalent circuit this a-Se a 3-TFT C-APS imager is shown in FIGS. 17A-B. FIG. 17A illustrates a top cathode APS circuit schematic with, for example, a trans-impedance amplifier readout circuit (R_F and C_F are the feedback resistor and capacitor). The C-APS circuit consists of three TFTs—reset, amplifying and read (T_RST, T_AMP and T_READ). In the reset mode, only T_RST is switched on (by V_RST), which sets the voltage V_IN to V_REF. Next, in the integration mode, the charge generated due to the incident x-rays accumulates on the storage capacitor (C_s), which changes the voltage V_IN. After the integration stage, T_READ is switched on (by V_READ), which transfers an amplified signal (through T_AMP) to the data-line and external readout circuit. Thus, the APS circuit provides a charge gain, which cannot reduce the effect of any pre-amplifying noise (originating from T_RST leakage current shot noise and reset noise), but can eliminate the influence of the post-amplifying noise (thermal and flicker noise from T_AMP and T_READ and external readout circuit noise). FIG. 17B illustrates a top cathode Source follower V-APS circuit schematic with, for example, a MOS-based readout circuit. In this case, T_BIAS in the readout circuit acts as an active load and C_col stores the readout voltage, V_OUT. The a-Se detector layer is represented by a current source (I_se), diode (D_se) and the capacitance related to it (C_se). FIG. 17C illustrates cross-sectional views of a-Se imager and FIG. 17D illustrates a circuit diagram for a-Se/a-IGZO TFT APS. Other photodetectors such as, but not limited to, mercury iodine or perovskites detectors may be used.

It is to be understood that the foregoing description is of one or more embodiments of the invention. The invention is not limited to the particular embodiment(s) disclosed herein, but rather is defined solely by the claims below. Furthermore, the statements contained in the foregoing description relate to the disclosed embodiment(s) and are not to be construed as limitations on the scope of the invention or on the definition of terms used in the claims, except where a term or phrase is expressly defined above. Various other embodiments and various changes and modifications to the disclosed embodiment(s) will become apparent to those skilled in the art.

As used in this specification and claims, the terms “e.g.,” “for example,” “for instance,” “such as,” and “like,” and the verbs “comprising,” “having,” “including,” and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open-ended, meaning that the listing is not to be considered as excluding other, additional components or items. Other terms are to be construed using their broadest reasonable meaning unless they are used in a context that requires a different interpretation.

Claims

1. An active pixel sensor, comprising: thin-film transistors (TFTs) fabricated on a glass substrate, the TFTs comprising: a gate electrode patterned on the glass substrate;a gate insulator layer disposed over the gate electrode;an amorphous indium-tin-zinc-oxide (a-ITZO) active semi-conductor layer disposed on the gate insulator layer and patterned over the gate electrode; anda source electrode and a drain electrode patterned from a metal layer deposited over the a-ITZO layer.

2. The active pixel sensor of claim 1, wherein the TFTs form an active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

3. The active pixel sensor of claim 1, wherein the TFTs form a source output current-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

4. The active pixel sensor of claim 1, wherein the TFTs form a drain output current-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

5. The active pixel sensor of claim 1, wherein the TFTs form a source follower voltage-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

6. The active pixel sensor of claim 1, wherein the TFTs form a common source voltage-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

7. The active pixel sensor of claim 1 having a pixel pitch of 50 μm.

8. The active pixel sensor of claim 1, further comprising a photodiode layer fabricated over the over the TFTs forming a vertically-stacked imaging pixel.

9. The active pixel sensor of claim 8, wherein the photodiode is an organic photodiode or an amorphous Silicon p+-i-n+ Photodiode.

10. The active pixel sensor of claim 1, further comprising a photoconductive material layer fabricated over the over the TFTs forming a vertically-stacked imaging pixel.

11. The active pixel sensor of claim 10, wherein the photoconductive material is amorphous selenium, mercury iodide, or organometallic halide perovskite.

12. An active pixel sensor imaging array for large-area x-ray imagers, the array comprising: a plurality of active pixel sensors arranged in rows and columns, wherein each of the plurality of active pixel sensors are coupled to an external readout circuit and include a reset thin-film transistors (TFT), an amplifier TFT, and a readout TFT fabricated on a glass substrate, each of the TFTs comprising: a gate electrode patterned on the glass substrate;a gate insulator layer disposed over the gate electrode;an amorphous indium-tin-zinc-oxide (a-ITZO) active semi-conductor layer disposed on the gate insulator layer and patterned over the gate electrode; anda source electrode and a drain electrode patterned from a metal layer deposited over the a-ITZO layer;a photodetector fabricated over each of the active pixel sensors to form a vertically-stacked imaging pixel.

13. The active pixel sensor imaging array of claim 12, wherein the photodetector includes a photodiode layer or a photoconductive material layer.

14. The active pixel sensor imaging array of claim 12, wherein each of the plurality of active pixel sensors has a pixel pitch of 50 μm.

15. An x-ray imaging device, comprising: an active pixel sensor imaging array having a plurality of active pixel sensors arranged in rows and columns, each of the plurality of active pixel sensors include thin-film transistors (TFTs) fabricated on a glass substrate, the TFTs comprising: a gate electrode patterned on the glass substrate;a gate insulator layer disposed over the gate electrode;an amorphous indium-tin-zinc-oxide (a-ITZO) active semi-conductor layer disposed on the gate insulator layer and patterned over the gate electrode; anda source electrode and a drain electrode patterned from a metal layer deposited over the a-ITZO layer;a photodetector fabricated over the over each active pixel sensor forming vertically-stacked imaging pixel; anda readout circuit coupled to each of the plurality of active pixel sensors.

16. The x-ray imaging device of claim 15, wherein the photodetector includes a photodiode layer or a photoconductive material layer.

17. The x-ray imaging device of claim 15, wherein the TFTs form an active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

18. The x-ray imaging device of claim 15, wherein the TFTs form a source output current-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

19. The x-ray imaging device of claim 15, wherein the TFTs form a drain output current-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

20. The x-ray imaging device of claim 15, wherein the TFTs form a source follower voltage-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

21. The x-ray imaging device of claim 15, wherein the TFTs form a common source voltage-mode active pixel sensor circuit that includes a reset TFT, an amplifier TFT, and a readout TFT.

22. The x-ray imaging device of claim 15, wherein each of the plurality of active pixel sensors has a pixel pitch of 50 μm.