Patent Application
20240079455
The present disclosure relates to an electronic device, in particular a power MOSFET or a Schottky diode, and to a manufacturing method of the electronic device.
As is known, semiconductor materials having a wide bandgap, in particular having a high value of the bandgap, low on-state resistance (Ro N), high value of thermal conductivity, high operating frequencies and high saturation velocity of charge carriers, are ideal for producing electronic components, such as diodes or transistors, in particular for electrical applications. A material having said characteristics, and adapted to be used for manufacturing electronic components, is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g., 3C—SiC, 4H—SiC, 6H—SiC), is preferable to silicon as regards the properties listed above.
The hexagonal SiC polytype (4H—SiC) is by far the most studied polytype and mass production of 4H—SiC wafers are currently commercially available, albeit at a higher cost than typical silicon wafers. The 3C—SiC has a significant cost advantage over 4H—SiC as it may be grown directly on Si by CVD deposition. The availability of 3C—SiC epitaxial layers of good quality of Silicon enables the implementation of cost-effective SiC-based power devices, for example adapted to work in the interval 650V-1200V.
Electronic devices provided with a silicon carbide substrate, compared to similar devices provided with a silicon substrate, have further advantages, such as low output resistance in conduction, low leakage current, and high operating frequencies. In particular, SiC Schottky diodes have demonstrated higher switching performances, making SiC electric devices particularly favorable for high-frequency applications.
Numerous scientific papers have also reported good switching performances of silicon carbide (SiC) MOSFET devices. From an industrial point of view, in addition to switching performances, SiC MOSFET devices also have good structural robustness which is a desirable characteristic in power systems.
A relevant structural element in SiC (in particular 4H-SiC) MOSFET devices is the gate dielectric (or oxide). The properties of the gate dielectric (permittivity, fixed charges, etc.) and the dielectric/SiC interface quality (interface state density Dit, near interface oxide traps, NIOTs) have a significant impact on relevant parameters of the MOSFET, such as the field effect channel mobility μFE, the ON-state resistance and the threshold voltage Vth. Therefore, the gate dielectric optimization is the prerequisite for fully exploiting the performances of SiC MOSFETs.
Furthermore, in designing a MOSFET, a solution should be found to overcome the undesired reduction of the Vth when the on-state resistance is decreased. In particular, a solution is desirable to increase the Vth while maintaining a low on-state resistance.
Silicon oxide (SiO2) is commonly used in commercial SiC MOSFETs as a gate dielectric, owing to the ease of manufacturing by thermal oxidation of SiC. However, the oxidation rate of SiC is lower than that of Silicon and the interface state density is of about 2-3 orders of magnitude higher than that of the SiO2/Si stack. To reduce the interface state density Dit and improve the channel mobility μFE of 4H—SiC MOSFETs that use SiO2 as gate dielectric, a post-oxidation annealing (POA) or post-deposition annealing (PDA) step is typically performed in environments rich in nitrogen (N2O, NO). However, thermal oxidation of SiC, as well as POA and PDA processes, typically require high temperatures (>1100° C.) and long annealing times (up to 8 hours in some cases). Furthermore, all these processes lead to the formation of a “disordered” region at the SiO2/SiC interface as a consequence of the inevitable interfacial reoxidation that occurs during high-temperature annealing with NO or N2O. This disordered interface is characterized by the presence of SiOx and C non-stoichiometric defects, which have a negative effect on both channel mobility and stability of the threshold voltage (Vth).
Furthermore, due to the low permittivity of SiO2 compared to 4H—SiC, under high-voltage operating conditions the electric field inside the SiO2 is about 2.5 times higher than that of SiC. Therefore, when the electric field reaches the critical field of 4H—SiC (which is about 3-4 MV/cm), the SiO2 gate dielectric, according to Gauss's law, is subject to an electric field of about 2.3 times greater, i.e., about 7-9 MV/cm. Therefore, the SiO2 dielectric will be under high-stress and poor-reliability conditions.
According to a solution known to the Applicant, in order to reduce the thermal budget necessary for the SiC oxidation, the SiO2 layers deposited by CVD may be used as gate insulators in SiO2 MOSFETs.
According to a solution known to the Applicant, high-permeability dielectrics (such as Al2O3, HfO2, La2O3) have been proposed to attenuate the electric field in the gate insulator. However, in this process, a SiO2 layer may form at the interface, resulting in the creation of carbon-related defects (such as vacancies, interstitials, C—C dimers, carbon clusters, etc.) which may give rise to instability of the voltage VFB (flat-band voltage) in MOSCAPs (“Metal Oxide Semiconductor Capacitors”).
According to a solution known to the Applicant, Al2O3 films have been proposed as gate insulators to adjust the Vth value in the SiC MOSFETs. High-k insulators (known as “high-k” materials) may be used, in particular, to increase the Vth value in on-state in SiC MOSFETs. However, the integration of high-k dielectrics is limited by their susceptibility to crystallization phenomena at the thermal budgets required for forming contacts in SiC devices (>800° C.). Furthermore, the bandgap of the insulators decreases as their permittivity increases; consequently, the choice of a simple high-k generally causes a small band-offset with SiC and, consequently, a high leakage current.
The need is therefore felt to provide a solution to the problems set forth above.
According to the present disclosure, an electronic device and a manufacturing method thereof are provided, as defined in the attached claims.
For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:
In greater detail, the transistor 20 comprises a semiconductor body 48, in particular of SiC, having a first and a second face 48a, 48b opposite to each other along the direction of the Z axis. In particular, in the present embodiment, the term “semiconductor body” means a structural element or solid body that may comprise one or more epitaxial layers grown on a base substrate. In particular,
According to one aspect of the present disclosure, the polytype of the semiconductor body 48 is the cubic polytype of Silicon Carbide, or 3C-SiC. Alternatively, and according to a further aspect of the present disclosure, the polytype of the semiconductor body 48 is 4H—SiC. However, the present disclosure also finds application for further and different silicon carbide polytypes.
The gate terminal G extends on the first face 48a of the semiconductor body 48; a body region 45, having a second conductivity opposite to the first conductivity (here, a P-type implanted region), extends into the semiconductor body 48 (more in particular, into the structural layer 38) at (facing) the first face 48a; the source region 26, having the first conductivity, extends into the body region 45 at (facing) the first surface 48a; and the drain metallization 27 extends at the second face 48b of the semiconductor body 48. The transistor 20 is therefore of vertical-conduction type (i.e., the conductive channel extends along a main direction which is along the Z axis).
The gate terminal G includes a gate metallization 53, and a gate dielectric 52. The gate metallization 53 extends on the gate dielectric 52.
According to the present disclosure, the gate dielectric 52 is a stack, 100 including a plurality of superimposed layers, as illustrated in
An insulating, or dielectric, layer 56 extends on the gate region 24 and is, in particular, of silicon dioxide (SiO2) or silicon nitride (SiN) with a thickness, measured along the Z axis, comprised between 0.5 μm and 1.5 μm. Furthermore, a source terminal 58, in particular of metal material, for example Aluminum, with a thickness, measured along the Z axis, comprised between 0.5 μm and 2 μm, extends in proximity of the insulating layer 56.
The source terminal 58 extends up to contacting the source region 26, possibly through an ohmic contact region 59, optional.
The metal layer 27, for example of Ti/Ni/Au, which forms the gate terminal D, extends on the second face 48b of the semiconductor body 48. An interface layer to allow the ohmic contact, not shown, for example of nickel silicide, may be present between the semiconductor body 48 and the metal layer 27.
With reference to the gate dielectric 52 and to
In particular, the stack 100 comprises: a first insulating layer 102, in particular of Silicon Oxide (SiO2), having a thickness, along Z, comprised between 0.5 nm and 5 nm; a second insulating layer 104 on the first insulating layer 102, in particular of Hafnium Oxide (HfO2), having a thickness, along Z, comprised between 0.5 nm and 5 nm; a third insulating layer 106 on the second insulating layer 104, in particular of an alloy including aluminum (e.g., Al2O3, AlN, AlON), having a thickness, along Z, comprised between 10 nm and 100 nm. In one embodiment, the third insulating layer 106 is formed by a plurality of (e.g., two) sub-layers 106a, 106b, wherein the sub-layer 106a is of Aluminum Oxide (e.g., Al2O3) and the sub-layer 106b is of a Hafnium Oxide (e.g., HfO2).
Variants to what has been described above are possible, in particular the first insulating layer 102 may alternatively be of Al2O3, SiN or AlN; the second insulating layer 104 may alternatively be of HfSiOx, ZrO2, ZrSiOx; the sub-layer 106a of the third insulating layer 106 may alternatively be of AlSiOx and/or the sub-layer 106b may alternatively be of HfSiOx.
The insulating layer 102 has a reduced thickness to allow the tunneling of the electrons from the semiconductor body 48 and has a bandgap greater than the bandgap of the insulating layer 104. The insulating layer 102 therefore has a thickness such that it may be traversed by tunnel effect by the electrons which, confined in the potential well and in a number limited by the states allowed by the well, produce a positive Vth of the MOSFET 20.
The layer which acts as a trap for the electric charges is the insulating layer 104, with a reduced bandgap, which forms a quantum-well between the insulating layer 102 and the insulating layer 106. In one embodiment, the hafnium oxide represents a potential well for the electrons confined on one side by the insulating layer 102 and on the other side by the insulating layer 106.
The insulating layer 106 is configured to have a bandgap greater than the bandgap of the insulating layer 104. Since the layer 106 comprises the two sub-layers 106a and 106b previously described (or a plurality thereof), it allows to combine the advantages of high bandgap (e.g., the Al2O3 bandgap which may be comprised between 7 and 9 eV) and high dielectric constant (e.g., the HfO2 dielectric constant which is about 20).
In one embodiment:
In one embodiment:
The stack 100 according to the present disclosure, with respect to a single layer of a high-k material or of a set of sub-layers other than that described herein, allows to combine the advantages of high bandgap of the insulating layer 106 and the advantages of high dielectric constant of the insulating layer 104.
The stack 100 is steady, and has the aforementioned properties, when the materials forming it are amorphous (and non-crystalline). A further additional positive effect is that the proposed structure has a higher capacitance with respect to a gate dielectric of sole Silicon Oxide, allowing to have a higher RC constant, consequently limiting ringing phenomena induced by the fast switching of the MOSFET device 20.
With reference to the flowchart of
Step 200 comprises steps, known per se and therefore not described in detail, of forming the semiconductor body 48, including providing the substrate 36 and forming, on the substrate 36, the epitaxial layer 38 (by epitaxy).
Then, step 202, doping species implants are performed for forming the implanted regions 45 (body wells) and 26 (source regions). An annealing step is then performed (e.g., at a temperature comprised between 1600 and 1800° C.) for activating the dopants of the body 45 and source 26 implanted regions.
Then, step 204, the method proceeds with the formation of the source 59 and drain 27 metallizations (which form the respective ohmic contacts). This step includes depositing a metal layer (typically Ni, Ti, or a combination of Ni/Ti) at the source/body implants. This step is followed by a suitable high-temperature annealing (rapid thermal process, between 800° C. and 1100° C. for a time interval from 1 minute to 120 minutes). This allows the ohmic contacts (e.g., of Nickel Silicide, Ni2Si, in the event that the metal layer is of Ni) to be formed, by chemical reaction between the deposited metal and the Silicon present in the semiconductor body 48 (which, in this embodiment, is of SiC). In fact, the deposited metal reacts where it is in contact with the surface material of the semiconductor body 48, forming the ohmic contact.
Then, step 206, steps are performed for forming the stack 100.
In particular, the first insulating layer 102 is formed by depositing a Silicon Oxide layer, on the semiconductor body 48 (more precisely on the epitaxial layer 38) between the source metallizations 59. This step may be implemented by thermal oxidation or by bath in oxidizing solution (H2O2). This step is performed at temperatures comprised between 900° C. and 1400° C. for times that may vary between 30 s and 5 minutes depending on the temperature. The baths in aqueous solution of hydrogen peroxide may be carried out in a range of temperatures comprised between room temperature (25° C.) up to temperatures of 80-90° C. for a duration that may reach 120 minutes.
Alternatively, the insulating layer 102 may be deposited by ALD (“Atomic Layer deposition”) technique.
Then, the second insulating layer 104 is formed, on the first insulating layer 102, also by ALD technique. In one embodiment, the second insulating layer 104 is of HfO2 and may be deposited by a thermal process or Plasma, using the parameters according to the following table:
Then, the third insulating layer 106 is formed, on the second insulating layer 106, also by ALD technique. In one embodiment, the third insulating layer 106 is of Al2O3 and may be deposited by a thermal process or Plasma, using the parameters according to the following table:
As an alternative to deposition by ALD, one or all of the insulating layers 102, 104, 106 may be deposited by CVD technique, or reactive ion sputtering.
Then, step 208, a post-deposition annealing step is performed, in an environment containing oxygen, or in an inert environment such as Argon and/or Nitrogen.
Finally, step 210, the remaining steps are performed to complete the formation of the MOSFET device 20, including the formation of the gate conductive terminal (gate metallization 53 and insulating layer 56), in a per se known manner. The formation of the source terminal is also completed, forming the metallization 58.
With reference to the gate dielectric (stack 100), the latter is designed in such a way as to have a high density of electron traps.
Further specific treatments, as said, may allow the formation of electron traps. Such treatments include:
The negative charges that occur in the gate dielectric, as a consequence of what has been discussed above, compensate for the reduction of the threshold voltage Vth of the device as the channel resistance decreases. A MOSFET device is thus obtained having a high threshold voltage Vth and a low RON.
The Schottky device 60 includes a semiconductor body 68, in particular of SiC, more particularly of 3C—SiC; however, what described herein also applies to other SiC polytypes, for example 4H—SiC. The semiconductor body 68 has a first and a second face 68a, 68b opposite to each other along the direction of the Z axis. In particular, in the present embodiment, the term “semiconductor body” means a structural element which may comprise one or more epitaxial layers grown on a base substrate.
The Schottky device 60 further includes a cathode terminal 72, of metal material, which extends on the second face 68b of the semiconductor body 68; and an anode terminal 74, of metal material, which extends on the first face 68a of the semiconductor body 68. In use, by suitable biasing, a conductive channel is established between the anode terminal and the cathode terminal.
The Schottky device 60 has one or more trenches 73 extending in depth into the semiconductor body 68, in particular into the drift layer 70, along a main direction parallel to the Z axis. Exemplarily, each trench 73 has a depth d1, measured from the first face 68a towards the second face 68b, having a value comprised between 100 nm and 1000 nm. In the event that multiple trenches 73 are present, each trench 73 is spaced from a trench 73 immediately adjacent, along the direction of the X axis, from a portion of the structural layer 70. This portion of the structural layer 70 has an extension d2, along the direction of the X axis, having a value comprised, for example, between 100 nm and 5000 nm.
Each trench 73 is partially filled by a dielectric or insulating layer 80, which covers the side walls and the bottom of each respective trench 73. Furthermore, the filling of each trench 73 is completed by conductive portions 82 of the anode terminal 74 which penetrate and/or cover the trenches 73. Each of the portions 82 is therefore insulated from the structural layer 70 by a respective insulating layer 80.
The insulating layer 80 is a multilayer, or stack, of the same type as the stack 100 previously described and formed according to the same process steps (described in step 206 of
Schottky junctions 71 are formed by the plurality of metal-semiconductor junctions present at the interface between the drift layer 70 and the metal layer of the anode metallization 74. In particular, the Schottky junctions 71 (semiconductor-metal) are formed by portions of the drift layer 70 (N-doped) in direct electrical contact with respective portions of the anode metallization 74.
The presence of a net negative charge at the insulating layer 80 allows a positive charge balancing at the interface with the structural layer 70 and thus allows the interdiction characteristics of the diode 60 to be optimized. In particular, the surface depletion layer may be optimized by modifying both the switch-on voltage of the diode and the interdiction characteristics for negative biasing on the Schottky contact.
From an examination of the characteristics of the disclosure made according to the present disclosure, the advantages that it affords are evident.
According to the present disclosure it is in fact possible to reduce the thermal budget required for the manufacturing of the gate terminal, increase the reliability of the gate dielectric, reduce the RON and increase the Vth. These advantages are, at least in part, obtained owing to the high-permittivity high-k gate dielectric, whose properties may be adjusted by the process described above.
Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.
For example, the present disclosure may be applied to devices based on a SiC polytype other than 3C—SiC or 4H-SiC, in general transistors and diodes.
Furthermore, the present disclosure may be applied to devices based on a material other than SiC, for example GaN and AlGaN/GaN (normally-off HEMTs).
Furthermore, the present disclosure finds applications in various electronic devices other than those described in the aforementioned particular embodiments, for example VMOS (“Vertical-channel MOS”), DMOS (“Diffused MOS”), CMOS (“Complementary MOS”).
The present disclosure is also applicable to horizontal-channel devices.
An electronic device (20; 60) may be summarized as including a semiconductor body (48; 68), in particular of Silicon Carbide, having a first (48a; 68a) and a second face (48b; 68b), opposite to each other along a first direction (Z); an electrical terminal (G; 82, 74) at the first face (48b; 68b), including a conductive layer (53) and an electrical insulation region (52; 80), the electrical insulation region (52; 80) extending between the semiconductor body (48; 68) and the conductive layer (53), characterized in that said electrical insulation region (52; 80) is a multilayer including a first insulating layer (102) in contact with the semiconductor body, having a first bandgap value and a first thickness, configured to be traversed by the tunnel effect, during use, by electric charge carriers coming from the semiconductor body (48; 68); a second insulating layer (104) on the first insulating layer (102), having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness, configured to form a potential well for said electric charge carriers; and a third insulating layer (106) on the second insulating layer (104), having a third bandgap value between the first and the second bandgap values and a third thickness greater than the second thickness.
The first insulating layer (102) may have a thickness between 0.5 nm and 1 nm; the second insulating layer (104) may have a thickness between 1.5 nm and 2.5 nm; and the third insulating layer (106) may have a thickness between 10 and 100 nm.
The first insulating layer (102) may be of one from among: SiN, SiO2, AlN; the second insulating layer (104) may be of one from among: HfO2, HfSiOx, ZrO2, ZrSiOx; and the third insulating layer (106) may include two or more alternating layers of an Aluminum Oxide and a Hafnium Oxide.
The third insulating layer (106) may include two or more alternating layers of Al2O3 and HfO2, or two or more alternating layers of AlSiOx and HfSiOx.
The electronic device may further include a channel region (38, 36; 69, 70) in said semiconductor body (48; 68), configured to accommodate, in use, an electric current, said electrical insulation region (52; 80) extending at said channel region.
The electronic device may have positive charge carriers at said first face (48a; 68a) defining a positive interface charge, said electrical insulation region (52; 80) may be designed in such a way as to have trap states of electrons, which generate a negative charge such as to balance, at least in part, said positive interface charge.
Said electronic device may be a MOSFET including a source terminal (S, 26, 59) and a drain terminal (D, 27), said electrical terminal being a gate terminal (G, 53) of the MOSFET, the conductive layer being a gate metallization (53), and the electrical insulation region (52) forming, as a whole, a gate dielectric.
Said electronic device may be a diode and may include a cathode terminal (72) extending at the second face (68b) of the semiconductor body (68); at least one trench (73) extending from the first face (68a) towards the second face (68b), said electrical insulation region (80) extending into said trench (73); wherein said electrical terminal may form an anode terminal (74) of the diode and includes a metal layer having a portion (82) extending into said trench (73), said electrical insulation region (80) extending between said portion (82) of the anode terminal (74) and the semiconductor body (68).
The diode may be a Schottky diode including at least one metal-semiconductor junction formed by an electrical contact region between the anode terminal (74) and the semiconductor body (68) laterally to said trench (73).
A method of manufacturing an electronic device (20; 60) may be summarized as including the steps of providing a semiconductor body (48; 68), in particular of Silicon Carbide, having a first (48a; 68a) and a second face (48b; 68b), opposite to each other along a first direction (Z); forming an electrical terminal (G; 82, 74) at the first face (48b; 68b), including forming a conductive layer (53) and an electrical insulation region (52; 80) between the conductive layer (53) and the semiconductor body (48; 68), configured to electrically insulate the electrical terminal (G; 82, 74) from the semiconductor body (48; 68), characterized in that the step of forming said electrical insulation region (52; 80) includes forming a multilayer, including forming a first insulating layer (102) in contact with the semiconductor body, having a first bandgap value and a first thickness, configured to be traversed, by tunnel effect, during use, by electric charge carriers coming from the semiconductor body (48; 68); forming a second insulating layer (104) on the first insulating layer (102), having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness, configured to form a potential well for said electric charge carriers; and forming a third insulating layer (106) on the second insulating layer (104), having a third bandgap value between the first and the second bandgap values and a third thickness greater than the second thickness.
The first insulating layer (102) may have a thickness between 0.5 nm and 1 nm; the second insulating layer (104) may have a thickness between 1.5 nm and 2.5 nm; and the third insulating layer (106) may have a thickness between 10 and 100 nm.
The first insulating layer (102) may be of one from among: SiN, SiO2, AlN; the second insulating layer (104) may be of one from among: HfO2, HfSiOx, ZrO2, ZrSiOx; and the third insulating layer (106) may include two or more alternating layers of an Aluminum Oxide and a Hafnium Oxide.
The third insulating layer (106) may include two or more alternating layers of Al2O3 and HfO2, or two or more alternating layers of AlSiOx and HfSiOx.
Forming the second and the third insulating layers (104, 106) may include performing respective depositions by ALD technique.
The method may further include a channel region (38, 36; 69, 70) in said semiconductor body (48; 68), configured to accommodate, in use, an electric current, said electrical insulation region (52; 80) being formed at said channel region.
Said electronic device is a MOSFET, the manufacturing steps may further include forming a source terminal (S, 26, 59) and a drain terminal (D, 27) of the MOSFET, said electrical terminal being a gate terminal (G, 53) of the MOSFET, the conductive layer (53) being a gate metallization (53), and the electrical insulation region (52) forming, as a whole, a gate dielectric.
Said electronic device may be a diode, the manufacturing steps may further include forming a cathode terminal (72) extending at the second face (68b) of the semiconductor body (68); forming at least one trench (73) extending from the first face (68a) towards the second face (68b), said electrical insulation region (80) extending into said trench (73);
wherein said electrical terminal may be an anode terminal (74) of the diode and may include a metal layer having a portion (82) extending into said trench (73), said electrical insulation region (80) extending between said portion (82) of the anode terminal (74) and the semiconductor body (68).
The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102022000017730 | Aug 2022 | IT | national |
