Patent Grant
11717227
The present application claims priority of the Chinese Patent Application No. 201910081039.3, filed on Jan. 28, 2019 and entitled “Signal Processing Device and Signal Processing Method”, the disclosure of which is incorporated herein by reference in its entirety as part of the present application.
Embodiments of the present disclosure relate to a signal processing device and a signal processing method.
Non-stationary random signals refer to signals whose distribution parameters or distribution laws vary with time. At present, the research on analysis and processing of the non-stationary random signals has attracted widespread attention and has been increasingly developed.
Electroencephalogram signals are electrical pulse signals generated by a human brain, which are relatively common non-stationary random signals. The electroencephalogram signals contain information about emotions, thinking activities, or nervous system diseases of a human. Analysis and decoding of the electroencephalogram signals are widely used in fields such as brain-computer interface (BCI) and medical treatment.
At present, a common electroencephalogram signal processing method is to decode an electroencephalogram signal by using a digital signal processing method such as Fourier transform and wavelet transform, etc., in a computer or a digital signal processor, after anti-aliasing filtering and analog-digital signal conversion. In other words, the current electroencephalogram signal decoding is implemented by software. However, an electroencephalogram signal processing system based on a software decoding method requires the support of a hardware system with a large volume and high power consumption.
At least one embodiment of the present disclosure provides a signal processing device. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal; the memristor array comprises a plurality of memristor units, each of the plurality of memristor units comprises a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit in the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array; and the classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.
For example, in the signal processing device according to some embodiments of the present disclosure, the memristor array further includes a plurality of word lines, a plurality of bit lines and a plurality of source lines; and each of the plurality of memristor units is correspondingly connected with one word line in the plurality of word lines, one bit line in the plurality of bit lines, and one source line in the plurality of source lines, respectively.
For example, in the signal processing device according to some embodiments of the present disclosure, the memristor array is configured to: apply the first signal to at least one memristor unit in the plurality of memristor units through at least one bit line in the plurality of bit lines, and output the second signal through at least one source line in the plurality of source lines; or apply the first signal to at least one memristor unit in the plurality of memristor units through at least one source line in the plurality of source lines, and output the second signal through at least one bit line in the plurality of bit lines.
For example, in the signal processing device according to some embodiments of the present disclosure, the memristor array is further configured to segment the first signal that has been received to form signal segments, and apply respective signal segments to corresponding memristor units in the plurality of memristor units.
For example, in the signal processing device according to some embodiments of the present disclosure, the memristor array is configured to receive a switch control signal through at least one word line in the plurality of word lines, and select a memristor unit to be applied with the first signal based on the switch control signal.
For example, in the signal processing device according to some embodiments of the present disclosure, each of the plurality of memristor units further includes a transistor connected in series with the memristor in each of the plurality of memristor units.
For example, in the signal processing device according to some embodiments of the present disclosure, the memristor in each of the plurality of memristor units is a continuously adjustable multi-resistance state memristor.
For example, the signal processing device according to some embodiments of the present disclosure further includes a pre-processing circuit, wherein the pre-processing circuit is configured to pre-process the first signal received by the receiver, so as to form a pre-processed signal having an amplitude within a predetermined range.
For example, in the signal processing device according to some embodiments of the present disclosure, the pre-processing circuit includes at least one of an amplifying circuit and a level shift circuit.
For example, in the signal processing device according to some embodiments of the present disclosure, the predetermined range is a resistive voltage interval of the memristor or a read voltage interval of the memristor.
For example, in the signal processing device according to some embodiments of the present disclosure, the first signal received by the receiver is an electroencephalogram signal.
At least one embodiment of the present disclosure further provides a signal processing method. The signal processing method includes: receiving, by a receiver, a first signal; applying, by a memristor array, the first signal that has been received to at least one memristor unit in a plurality of memristor units of the memristor array, and outputting, by the memristor array, a second signal based on a memristor resistance value distribution of the memristor array, wherein the memristor unit includes a memristor; and classifying, by a classifier, the second signal outputted from the memristor array to obtain a type of the first signal.
For example, in the signal processing method according to some embodiments of the present disclosure, the memristor array further includes a plurality of word lines, a plurality of bit lines and a plurality of source lines; the applying, by the memristor array, the first signal that has been received to at least one memristor unit in the plurality of memristor units of the memristor array, includes: applying the first signal to at least one memristor unit in the plurality of memristor units through at least one bit line in the plurality of bit lines; and the outputting, by the memristor array, the second signal based on the memristor resistance value distribution of the memristor array, includes: outputting the second signal through at least one source line in the plurality of source lines.
For example, in the signal processing method according to some embodiments of the present disclosure, the memristor array further includes a plurality of word lines, a plurality of bit lines and a plurality of source lines; the applying, by the memristor array, the first signal that has been received to at least one memristor unit in the plurality of memristor units of the memristor array, includes: applying the first signal to at least one memristor unit in the plurality of memristor units through at least one source line in the plurality of source lines; and the outputting, by the memristor array, the second signal based on the memristor resistance value distribution of the memristor array, includes: outputting the second signal through at least one bit line in the plurality of bit lines.
For example, in the signal processing method according to some embodiments of the present disclosure, the applying, by the memristor array, the first signal that has been received to at least one memristor unit in the plurality of memristor units of the memristor array, includes: segmenting the first signal that has been received to form signal segments, and applying respective signal segments to corresponding memristor units in the plurality of memristor units.
For example, in the signal processing method according to some embodiments of the present disclosure, the memristor array further includes a plurality of word lines, a plurality of bit lines and a plurality of source lines, and the applying, by the memristor array, the first signal that has been received to at least one memristor unit in the plurality of memristor units of the memristor array, includes: receiving a switch control signal through at least one word line in the plurality of word lines, and selecting a memristor unit to be applied with the first signal based on the switch control signal.
For example, the signal processing method according to some embodiments of the present disclosure further includes: pre-processing, by a pre-processing circuit, the first signal that has been received, so as to form a pre-processed signal having an amplitude within a predetermined range.
For example, in the signal processing method according to some embodiments of the present disclosure, the pre-processing includes at least one selected from the group consisting of amplifying the first signal that has been received and level shifting the first signal that has been received.
For example, in the signal processing method according to some embodiments of the present disclosure, the predetermined range is a resistive voltage interval of the memristor or a read voltage interval of the memristor.
For example, the signal processing method according to some embodiments of the present disclosure, before the applying, by the memristor array, the first signal that has been received to at least one memristor unit in the plurality of memristor units of the memristor array, further includes: initializing the memristor array, so that initial states of respective memristors in the memristor array are substantially the same.
In order to clearly illustrate the technical solutions of the embodiments of the disclosure, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the disclosure and thus are not limitative to the disclosure.
In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.
The terms used herein to describe embodiments of the present application are not intended to restrict and/or limit the scope of the present disclosure.
For example, unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.
It should be understood that the terms “first,” “second,” etc., which are used in the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Unless clearly otherwise indicated in the context, the terms “a,” “an” or “the,” etc., are not intended to indicate a limitation of quantity, but rather indicate the presence of at least one.
In should be further understood that, the terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases “connect”, “connected”, etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. “On,” “under,” “right,” “left” and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly.
Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals or numbers may refer to components or elements that perform substantially the same function.
At least one exemplary embodiment of the present disclosure provides a signal processing device. The signal processing device includes a receiver, a memristor array and a classifier, wherein the receiver is configured to receive a first signal; the memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit in the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array; and the classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.
At least one exemplary embodiment of the present disclosure provides a signal processing method. The signal processing method includes: receiving, by a receiver, a first signal; applying, by a memristor array, the first signal that has been received to at least one memristor unit in a plurality of memristor units of the memristor array, and outputting, by the memristor array, a second signal based on a memristor resistance value distribution of the memristor array, wherein the memristor unit includes a memristor; and classifying, by a classifier, the second signal outputted from the memristor array to obtain a type of the first signal.
A memristor is a passive electronic device; and electrical pulse excitations with different amplitudes/frequencies will cause redistribution of ions in the memristor, which will be further presented as different resistance values. For example, the resistance value of the memristor may vary with a voltage or a current applied.
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In the signal processing device 1, the receiver 11 can be configured to receive a first signal, wherein the first signal is a signal to be identified. For example, the first signal can be a non-stationary random signal. For example, the non-stationary random signal can be an electroencephalogram signal. For example, the number of the first signals can be one or more. That is to say, the signal processing device 1 according to the exemplary embodiment of the present disclosure can identify one first signal or a plurality of first signals to obtain a type(s) of the first signal(s).
In the signal processing device 1, the memristor array 12 can be configured to apply the first signal that has been received to at least one memristor unit in a plurality of memristor units of the memristor array, and output a second signal based on a memristor resistance value distribution of the memristor array. Thus, the memristor array 12 can encode the first signal into the second signal based on the memristor resistance value distribution of the memristor array 12. Because the memristor is small in volume, low in power consumption and easy to be integrated with high density, the signal processing device 1 according to the embodiment of the present disclosure has advantages of small volume, low power consumption and easy integration. In addition, because the memristor array 12 converts the first signal into the second signal, no additional analog-to-digital conversion component is required to process the first signal, and the second signal obtained can be used for classification; and therefore, the signal processing device 1 according to the embodiment of the present disclosure further reduces the volume and cost.
In the signal processing device 1, the classifier 13 can be configured to classify the second signal outputted by the memristor array, to obtain the type of the first signal.
For example, the classifier 13 can include a neural network classifier. For example, the classifier 13 can be further configured to classify the second signal outputted from the memristor array by using a neural network classification method, to obtain the type of the first signal. For example, the neural network classification method can include a back propagation (BP) neural network method, a radial basis function (RBF) neural network method, a convolutional neural network method, etc. Because the second signal is based on the memristor resistance value distribution of the memristor array 12, the second signal can be easily classified and identified by the classifier. Further, by classifying and identifying the second signal, the type of the first signal can be obtained.
For example, the classifier 13 can be implemented by at least one selected from the group consisting of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) and a graphics processing unit (GPU); or the classifier 13 can be implemented by hardware, firmware or software, as well as any combination thereof. In addition, these classifiers are trained with a large number of training sample sets, and these training sample sets include historical data obtained with respect to different situations. After being trained to a certain degree, the classifier can classify a new second signal being inputted.
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For example, the memristor array 12 can be configured to: apply the first signal to a corresponding memristor unit through at least one bit line in the bit lines BL1 to BLM; and output a second signal through at least one source line in the source lines SL1 to SLN. For example, when the number of first signals that have been received is one, one bit line can be selected from the bit lines BL1 to BLM to apply the first signal to the corresponding memristor unit therethrough, and one source line can be selected from the source lines SL1 to SLN to output a second signal. For example, when the number of first signals that have been received is three, three bit lines can be selected from the bit lines BL1 to BLM to receive the three first signals, respectively, and corresponding source lines can be selected from the source lines SL1 to SLN to output second signals.
The embodiment in which the memristor array 12 is configured to receive a first signal through a bit line and output a second signal through a source line is described above, but the present disclosure is not limited thereto. For example, as another example, the memristor array 12 can be configured to receive a first signal through a source line and output a second signal through a bit line. For example, the memristor array 12 can be configured to: apply the first signal to a corresponding memristor unit through at least one source line in the source lines SL1 to SLN; and output the second signal through at least one bit line in the bit lines BL1 to BLM. For example, when the number of first signals that have been received is one, one source line can be selected from the source lines SL1 to SLN to receive the first signal, and a corresponding bit line can be selected from the bit lines BL1 to BLM to output the second signal. For example, when the number of first signals that have been received is three, three source lines can be selected from the source lines SL1 to SLN to receive the three first signals, respectively, and corresponding bit lines can be selected from the bit lines BL1 to BLM to output second signals.
For example, the memristor array 12 can be further configured to segment the first signal that has been received to form signal segments, and apply respective signal segments to memristor units that correspond to source lines receiving the first signal among the N*M memristor units, for example, different memristor units correspond to different segments of the first signal. After each memristor unit receives a corresponding segment of the first signal, a resistance value of the memristor in the memristor unit is changed under an action of the corresponding signal segment of the first signal.
For example, the memristor array 12 can be further configured to receive a switch control signal through at least one word line in the word lines WL1 to WLN, and select a memristor unit to be applied with the first signal based on the switch control signal. For example, the switch control signal can include a set signal or a reset signal, for selecting a corresponding memristor or not selecting a corresponding memristor.
For example, the signal processing device 1 can further include a word line decoder (not shown) connected with the word lines WL1 to WLN of the memristor array, and the word line decoder can be configured to receive the switch control signal and send the same to at least one word line in the word lines WL1 to WLN.
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For example, the pre-processing circuit 14 may include an amplifying circuit 141 and a level shift circuit 142. For example, the amplifying circuit 141 can be configured to amplify the first signal. For example, an amplification factor can be selected according to the amplitude of the first signal itself, for example, 1000. For example, the level shift circuit 142 can be configured to perform a level shift on the first signal being amplified so that the amplitude of the first signal is within the predetermined range.
For example, the signal processing device can further comprise a signal acquisition circuit (not shown). The signal acquisition circuit can be configured to acquire the first signal and send the same to the receiver.
It should be noted that, the signal processing device according to the embodiments of the present disclosure as described above is merely an exemplary structure. However, the present disclosure is not limited thereto. For example, some components therein may be omitted or additional components may be added.
Referring to
Step S101: receiving, by a receiver, a first signal. The first signal is a signal to be identified. For example, the first signal can be a non-stationary random signal. For example, the first signal can be an electroencephalogram signal. For example, the number of first signals may be one or more. That is to say, one first signal or a plurality of first signals can be identified to obtain a type(s) of the first signal(s) by using the signal processing method according to the exemplary embodiment of the present disclosure.
For example, before step S101, the signal processing method can further include: initializing a memristor array, so that initial states of respective memristors in the memristor array are substantially the same. For example, an initial state includes a high-resistance state and a low-resistance state. For example, a high-resistance state of a memristor may be 10 megohms (MΩ), and a low-resistance state of a memristor may be 50 kilo-ohms (KΩ).
Step S102: applying, by a memristor array, the first signal that has been received to at least one memristor unit in a plurality of memristor units of the memristor array, and outputting, by the memristor array, a second signal based on a memristor resistance value distribution of the memristor array, wherein the memristor unit includes a memristor. As a result, the memristor array can encode the first signal into the second signal based on the memristor resistance value distribution of the memristor array.
For example, in the signal processing method provided by the embodiment of the present disclosure, the memristor array further includes a plurality of word lines, a plurality of bit lines and a plurality of source lines; and the memristor unit further includes a transistor connected in series with the memristor in the memristor unit. Step S102 can further include: applying the first signal to a corresponding memristor unit through at least one bit line in the plurality of bit lines; and outputting the second signal through at least one source line in the plurality of source lines. For example, when the number of first signals that have been received is one, one bit line can be selected from the plurality of bit lines to apply the first signal to the corresponding memristor unit therethrough, and one corresponding source line can be selected from the plurality of source lines to output the second signal. For example, when the number of first signals that have been received is three, three bit lines can be selected from the plurality of bit lines to receive the three first signals, respectively, and corresponding source lines can be selected from the plurality of source lines to output second signals.
The embodiment in which the first signal is received through a bit line and the second signal is outputted through a source line is described above, but the present disclosure is not limited thereto. For example, as another example, step S102 can include: applying the first signal to a corresponding memristor unit through at least one source line in the plurality of source lines; and outputting the second signal through at least one bit line in the plurality of bit lines. For example, when the number of first signals that have been received is one, one source line can be selected from the plurality of source lines to receive the first signal, and a corresponding bit line can be selected from the plurality of bit lines to output the second signal. For example, when the number of first signals that have been received is three, three source lines can be selected from the plurality of source lines to receive the three first signals, respectively, and corresponding bit lines can be selected from the plurality of bit lines to output second signals.
For example, in the signal processing method provided by the embodiment of the present disclosure, the memristor array further includes a plurality of word lines, a plurality of bit lines and a plurality of source lines; and the memristor unit further includes a transistor connected in series with the memristor in the memristor unit. Step S102 can further include: segmenting the first signal that has been received to form signal segments, and applying respective signal segments to memristor units that correspond to source lines receiving the first signal among the memristor units in the memristor array, for example, different memristor units correspond to different segments of the first signal. After each memristor unit receives a corresponding segment of the first signal, a resistance value of the memristor in the memristor unit is changed under an action of the corresponding signal segment of the first signal. For example, a detailed method of segmenting the first signal can be referred to
For example, in the signal processing method provided by the embodiment of the present disclosure, the memristor array further includes a plurality of word lines, a plurality of bit lines and a plurality of source lines; and the memristor unit further includes a transistor connected in series with the memristor in the memristor unit. Step S102 can further include: receiving a switch control signal through at least one word line in the plurality of word lines, and selecting a memristor unit to be applied with the first signal based on the switch control signal. For example, the switch control signal can include a set signal or a reset signal, for selecting a corresponding memristor or not selecting a corresponding memristor.
For example, before step S102, the signal processing method can further include: pre-processing, by a pre-processing circuit, the first signal that has been received, to form a pre-processed signal having an amplitude within a predetermined range. For example, the pre-processing includes at least one selected from the group consisting of amplifying the first signal that has been received and level shifting the first signal that has been received. For example, the predetermined range is a resistive voltage interval of the memristor or a read voltage interval of the memristor.
Step S103: classifying, by a classifier, the second signal outputted from the memristor array to obtain a type of the first signal. As described above, with respect to different first signals, different memristor resistance distributions of the memristor array can be obtained, so the second signal based on the memristor resistance distribution of the memristor array can be classified to obtain the type of the first signal.
For detailed contents of step S102 and step S103, corresponding description in the above-described signal processing device can be referred to, and details will not be repeated here.
For example, in step S103, the second signal outputted from the memristor array can be classified by a neural network classifier using a neural network classification method, to obtain the type of the first signal. For example, the neural network classification method can include a back propagation (BP) neural network method, a radial basis function (RBF) neural network method, a convolutional neural network method, etc., and may be selected according to needs.
For example, the signal processing method according to the embodiment of the present disclosure further includes training the neural network classifier with a training sample set to set parameters of the neural network classifier. For example, in a case where the first signal is an electroencephalogram signal and the type of the first signal includes a first-type electroencephalogram signal, a second-type electroencephalogram signal, and a third-type electroencephalogram signal, training samples can include: a plurality of first-type training samples obtained after processing a plurality of first-type electroencephalogram signals at least through step S101 and step S102; a plurality of second-type training samples obtained after processing a plurality of second-type electroencephalogram signals at least through step S101 and step S102; and a plurality of third-type training samples obtained after processing a plurality of third-type electroencephalogram signals at least through step S101 and step S102; and the plurality of first-type training samples, the plurality of second-type training samples and the plurality of third-type training samples as described above are combined to obtain the training sample set. The above is only a case in which the type of the first signal includes three different types, but the present disclosure is not limited thereto; cases in which the type of the first signal includes two or more different types can also be processed by using a similar method, and details will not be repeated here. In addition, it should be noted that, for a specific method of training the neural network classifier with the training sample set, the neural network classification methods in the prior art can be referred to, which is not be limited in the present disclosure.
It should be noted that, the step of training a classifier with training samples to set parameters of the classifier can be executed before step S101, can be executed before step S102, or can be executed before step S103.
What have been described above are only specific implementations of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Any changes or substitutions easily occur to those skilled in the art within the technical scope of the present disclosure should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined based on the protection scope of the claims.
| Number | Date | Country | Kind |
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| 20200237311 A1 | Jul 2020 | US |
