Patent Application
20060006394
The field of invention is diodes and other semiconductor devices having SiC substrates, and more particularly power Schottky Diodes/Rectifiers in silicon carbide (SiC).
High voltage SiC Schottky diodes, which can handle voltages between 300 V and 3.5 kV, are expected to compete with silicon p-doped-intrinsic-n-doped (PIN) diodes fabricated of similar voltage ratings. Such diodes may handle up to 100 Amps of current, depending on their size. High voltage Schottky diodes have a number of applications, particularly in the field of power conditioning, distribution and control.
The basic conventional structure of a Schottky diode is shown in
In addition, the back side of the device may be implanted with n-type dopants to lower the resistance of the back side ohmic contact. These implants must be annealed at a high temperature prior to deposition of the Schottky contact, which cannot be annealed.
An important advantage of a SiC Schottky diode in such applications is its switching speed. Silicon-based PIN devices exhibit relatively poor switching speeds. A silicon PIN diode may have a maximum switching speed of approximately 20 kHz, depending on its voltage rating. In contrast, silicon carbide-based devices are theoretically capable of much higher switching speeds, in excess of 100 times better than silicon. In addition, silicon carbide devices are capable of handling a higher current density than silicon devices.
Although there are significant advantages of SiC Schottky diodes, and other SiC devices, reliable fabrication of such devices is difficult. The two aspects that need particular attention in this respect are: (a) Optimally doped and substantially defect-free epitaxial layers for their voltage blocking layers; and (b) Edge termination designs that allow blocking of high voltages where the critical field is close to the theoretical maximum of the material.
Unique SiC epitaxial layer methods and new edge termination designs for allowing high voltage operation are presented.
Embodiments of the invention provide a semiconductor device and method of formation wherein a disjointed termination layer is formed around a Schottky metal region. Preferably a SiC substrate is provided, on top of which a SiC blocking is disposed. The disjointed termination layer is formed above the SiC blocking layer. The termination is preferably an epitaxial SiC layer. The Schottky region is patterned on the blocking region and metal is deposited on the region. It has been found to be advantageous to form the Schottky metal region on the C-face of the blocking layer. The method is particularly applicable to Schottky diodes but can be implemented to form other semiconductor devices.
The invention is best understood from the following detailed description when read with the accompanying drawings.
FIGS. 7A-H depict a Schottky diode formation process according to an illustrative embodiment of the invention.
Embodiments of the invention provide Schottky diodes that utilize the C-face of 4H-SiC for the growth of epitaxial layers. As used herein “C-face” is not limited to the on-axis C-face but includes the off-axis C-face. The scope of the invention includes off-axis substrates to 90°. Illustrative off-axis amounts that may be suitable for particular applications include less than 60°, less than 30°, less than 8°, less than 4°, less than 2°, and less than 1°. In an exemplary embodiment of the invention, substrates are 8° off-axis toward the [11-20] direction or [1-100] direction, where the C-face is the [000-1] plane. The crystal structure of 4H-SiC is such that most wafers manufactured on its basal plane have two faces—a Si face with Si atoms, and another with C-face with mostly C atoms. Most of the devices made presently are on the Si-face because it is difficult to grow high quality epitaxial layers on C-face of SiC. However, there are many potential advantages of using the C-face of SiC for Schottky diode manufacture. First, the C-face is “flatter” in the sense that step bunching does not substantially exist as with the Si-face. Flatter surfaces result in reduced leakage of the diodes. Second, the incorporation of dopants is different, i.e. nitrogen (n-type) is easier to incorporate and Al (p-type) is more difficult which result in a better control of the doping, and quality of the drift layer since compensation effects of the p-type dopant is eliminated. There is a drawback with this namely, that Al-doping in excess of 1019 cm−3 is difficult to achieve on the C-face. This is, however, well within the levels needed for the present application. It is noted that other p-type dopants are within the spirit and scope of the invention.
(1) From a device processing standpoint, C-face offers a tremendous advantage over Si-face for the commercial manufacture of Schottky diode. This advantage primarily stems from the faster oxidation rate offered by C-face as compared to the Silicon face, making it much more suitable for adaptation to conventional silicon fabrication facilities. This may result in devices that are much cheaper, while offering better performance than those made using Si-face.
(2) From a device design and performance standpoint, C-face Schottky diodes can result in lower on-state voltage drop because of the different Schottky barrier heights offered by various Schottky metals. The on-state voltage drop of a Schottky diode depends on (a) The metal-semiconductor barrier height of the Schottky metal used; and (b) the resistance of the Schottky diode. The on-state voltage drop of a Schottky diode is directly proportional to the metal-semiconductor barrier height. However, the blocking capability (leakage current in blocking state) of a Schottky diode suffers exponentially with barrier height. On Si-face typical metal-semiconductor barrier heights for common metals are Tantalum (0.6 eV), Titanium (1.1 eV), Nickel (1.6 eV), Gold (1.9 eV). Although little research has been done to exactly determine these numbers for C-face, indications are that on C-face, metal-semiconductor barrier heights of common metals are about 0.2 eV higher than those on Si-face. In case of Si-face SiC Schottky diodes, Tantalum (0.6 eV) has not been found to be practical because of very large leakage currents observed in such diodes. Titanium (1.1 eV) results in higher on-state drop than Si PIN diodes, making them somewhat un-competitive. Hence, the ideal barrier height seems to be in the 0.7-0.9 eV range, which is where Tantalum is expected to be in case of C-face SiC Schottky diodes.
(3) The resistance of a Schottky diode has three components, namely: n− drift resistance, n+ substrate resistance, and backside contact resistance. The n− drift resistance is unavoidable as a practical matter; as its doping and thickness, and therefore the resistance, of the region must be sufficient to accommodate high voltages. The backside implants are annealed to help reduce backside contact resistance, which may become significant for low voltage applications.
Since ion implantation results in damage to the edge termination part of the SiC crystal that severely affects the leakage currents of high voltage devices, epitaxially-created edge termination regions may result in higher yielding, lower leakage current high voltage Schottky diodes.
This differs from junction termination extension (JTE), because it utilizes higher doped p-epitaxial layers than optimally doped JTE layers. (Optimum JTE charge is defined as Epsilon*Critical Electric Field)/Electronic Charge Illustrative doping levels for the termination layer include: greater than about 1×1017 cm−3; about 1×1017 cm−3 to about 1×1020 cm−3; and about 5×1017 cm−3 to about 5×1018 cm−3.
The doping and thickness of the termination p-layer can vary, but optimum values will depend on one another. With a thinner termination layer a higher doping is necessary so that the field can be contained within the layer. An illustrative example of values is a thickness of approximately 0.5 μm with a doping of approximately 1×1018. Thicknesses of greater than 0.5 μm become more difficult to etch. Therefore, thinner layers are more advantageous. An illustrative range of termination layer thickness is about 0.05 μm to about 2.0 μm, with a preferred range of about 0.1 μm to about 0.5 μm.
The disjointed termination region also differs from a guard ring termination because it may be used for higher voltage designs. Typically, the voltage limit for a guard ring construction is 1000 V. Embodiments of the inventive device can be used for voltages greater than 300 V. It is noted that the epitaxial disjointed p-region can be used in planar termination regions other than the illustrative embodiments described herein.
Preferably the length of the floating p-epilayer is less than 1.5× the n-epilayer thickness. Other illustrative p-epilayer length ranges include 1.25×-1.5× the n-epilayer and 1.2×-1.4× the n-epilayer thickness.
Following is a description of some key advantages to disjointed termination regions as provided by embodiments of the invention:
(1) The disjointed design may reduce termination length for higher voltage devices as compared to JTE and guardrings. Higher dopings allow substantial pinning of electric field lines as compared to JTE. Since JTE requires precise p-type doping, which is usually targeted below the optimum value from practical considerations, it results in a larger termination length for high voltage devices. Higher doping used in embodiments of the present invention will allow substantial reduction in electric fields for smaller termination lengths.
(2) The disjointed edge termination may offer lower leakage current because the leakage current path formed by the p-edge termination region is not continuous, but is physically interrupted. Termination of field lines creates leakage current in the p-type regions if there exists a leakage path to the Anode contact. Since only a small part of the p-edge termination is in contact with the Anode contact, only a small leakage will result as compared to a JTE termination, which has a substantial region to collect the leakage currents.
(3) Embodiments of the present invention may allow a simplified fabrication process as compared to conventional processes because of lack of any p-type implants. Typical edge terminations in SiC Schottky diodes require ion implantation of p-type dopants into the crystal. Such implants cause substantial damage to the crystal lattice, which can be repaired only by annealing at high temperature. This high-temperature anneal step (>1500° C.) is undesirable for a number of reasons. Most importantly, it tends to degrade the surface of SiC on which the Schottky contact is to be made, as silicon tends to dissociate from exposed surfaces of the crystal under such a high-temperature anneal. Loss of silicon in this manner results in a non-ideal Schottky contact between metal and the semiconductor surface. High temperature anneals have other drawbacks as well. Namely, they are typically time-consuming and expensive. Moreover, implantation of p-type (Al) dopants causes substantial lattice damage, or other species (B) have poor activation rates. Finally, they are typically less reproducible as compared to growing the p-layer epitaxially.
(4) Tests comparing the disjointed termination design with a standard JTE show that the disjointed design can provide a more robust design giving better performance and significantly less variation of the performance both in the reverse and forward directions resulting in higher yields.
Following are the basic steps for fabrication of a device according to an illustrative embodiment of the invention. The layers described may each be formed of one or more layers or materials. Doped layers may be uniform or graded.
(1) First an n-type epitaxial structure with a high doped p-type termination region is formed using an epitaxial growth technique. Preferably both the n-type and the p-type layers are grown in the same epitaxial run. It is noted that the reverse configuration may be used wherein a p-type epitaxial structure with a high doped n-type termination is formed.
(2) A plasma assisted SiO2 (oxide) is then deposited on the termination layer, and patterned by a photolithographic technique only to be in regions where the termination region is required.
(3) The p-type SiC is then removed where it is not required (where Schottky metal is to be deposited, in the disjoint space, and in the rest of the wafer surface) using reactive ion etch (RIE) or similar.
(4) A thin sacrificial oxide is thermally grown and a photoresist is deposited and hard baked on the front side to protect the Schottky surface. The wafer is dipped in a buffered oxide etch to remove the oxide on the backside. Thereafter the photoresist is removed on the front side.
(5) A suitable ohmic metal, such as Nickel, is deposited on the back side of the device and annealed using a rapid thermal annealing step to form the back side contact. The backside contact is protected with photoresist, which is hard baked.
(6) Thereafter, a buffered oxide etch is used to remove the thermal oxide and using a photolithographic step, Schottky regions are defined and a Schottky metal is deposited. The photoresist is then removed everywhere. The Schottky metal can be any metal with a suitable barrier height to SiC, like Tantalum, Nickel, Chromium, Titanium or Platinum. The Schottky metal may slightly overlap the p-type termination region.
Methods according to illustrative embodiments of the invention will now be described as depicted in FIGS. 7A-H.
As used herein, “above” means on the front side of the device, such as on the side the Schottky metal region would be located on a Schottky diode. “Below” means on the back side or the side opposite to the front side. When layers are described as “above”, “below” or “on” they need not be immediately adjacent to one another or directly on, however, the order of the layers will be relevant. The terms are used merely as a relative placement indication.
The surface of termination layer 706 preferably undergoes a cleaning process prior to further formation of the device. RCA clean is the standard cleaning for such devices and is an example of a cleaning process that can be used in the inventive processes.
A buffer layer may optionally, but advisably, be positioned between the n-type blocking layer and the n+ substrate.
FIGS. 7B-C depict the termination layer etching stage. An oxide layer 708 is formed on termination layer 706. Oxide layer 708 is preferably formed by plasma enhanced chemical vapor deposition (PECVD). A photoresist is applied to the oxide, preferably at a thickness of 0.05μ. The photoresist is exposed using a patterned mask, and the oxide is etched to the termination layer according to the pattern. Other patterning methods may be used that are compatible with the materials being used.
A nickel layer 710 is then deposited on the patterned oxide layer. (This of course means that the nickel will coat both the oxide layer and the exposed termination layer.) Although Ni is preferred, other metals may be used. Preferably Ni layer 710 is deposited using an e-beam evaporation method to a thickness of approximately 0.1 μm. Ni layer 710 is then patterned, preferably by a lift off process. A typical lift off process would include defining the pattern on oxide layer 708 using a photoresist, blanket-depositing the Ni over oxide layer 708, and lifting-off the Ni according to the pattern by dissolving the photoresist under Ni layer 710. The patterned Ni and oxide layers 708, 710 form a mask by which termination layer 706 can be etched. Preferably an inductively coupled plasma (ICP) etch is used on termination layer 706. Oxide layer 708 and Ni layer 710 can then be removed, for example by dipping in a buffered oxide etch (BOE) and Pirana Solution. The resulting patterned termination layer 706 is shown in
Formation of the Schottky metal region 716 is depicted in
Additional potential benefits of embodiments of the present invention are described as follows:
The inventive methods and devices are particularly applicable to Schottky diodes, however, application to other semiconductor devices is within the spirit and scope of the invention.
The invention includes the methods described herein and devices fabricated using the methods. The invention further includes integrated circuits and computer chips incorporating the devices.
While the invention has been described by illustrative embodiments, additional advantages and modifications will occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to specific details shown and described herein. Modifications, for example, to the metals used and growth and deposition techniques, may be made without departing from the spirit and scope of the invention. Accordingly, it is intended that the invention not be limited to the specific illustrative embodiments, but be interpreted within the full spirit and scope of the appended claims and their equivalents.
This application is based on, and claims priority to, provisional application having Ser. No. 60/575,332, having a filing date of May 28, 2004, entitled C-face SiC Power Schottky Diodes with Disjointed p-Epitaxial termination.
| Number | Date | Country | |
|---|---|---|---|
| 60575332 | May 2004 | US |
