Patent Application
20080014739
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.
The term “interconnect” is used interchangeably herein with terms including interconnect line, metal lines, trace, wire, conductor, signal path, and signaling medium. Interconnects are generally made of aluminum, copper or an alloy of copper and aluminum. Interconnects are conductors that provide signal paths for coupling or interconnecting electrical circuitry. Conductors other than the above mentioned metals include, for example, doped polysilicon, doped single crystal silicon, titanium, molybdenum, tungsten, and refractory metal silicides.
One of ordinary skill in the art will understand that silicon nitride refers to a composition of the type SixNyHz, in both stoichiometric and solid solution ratio and silicon oxy-carbide refers to a composition of the type SiwOxCyHz, in both stoichiometric and solid solution ratio. According to various embodiments, copper in the semiconductor structure can be copper or an alloy of copper.
In various embodiments, the first etch stop layer 110 can have a thickness from about 10 Å to about 500 Å and the second etch stop layer 120 can have thickness from about 50 Å to about 500 Å. In some embodiments, the first etch stop layer 110 can have thickness from about 20 Å to about 50 Å and the second etch stop layer 120 can have thickness from about 100 Å to about 400 Å.
The dielectric constant, k of silicon oxy-carbide can be in the range of about 3.5 to about 5.0 and is lower than that of silicon nitride which can be in the range of about 6.0 to about 7.0. The actual dielectric constant of the silicon oxy-carbide layer and the silicon nitride layer depend on the deposition process parameters. The effective dielectric constant of the etch stop bi-layer stack 101 is the combined dielectric constant of the first etch stop layer 110 and the second etch stop layer 120. The effective dielectric constant can be adjusted by changing the process parameters during the deposition of the first etch stop layer 110 and the second etch stop layer 120 and also by adjusting the thickness ratio of the first etch stop layer 110 and the second etch stop layer 120. The effective dielectric constant of the etch stop bi-layer stack 101 can vary from about 4.1 to about 5.9. In the exemplary etch stop bi-layer stack 101, the effective dielectric constant can be around 4.7.
In certain embodiments of the invention, the first etch stop layer 210 can be silicon nitride. One of ordinary skill in the art would know that there are various techniques for the deposition of silicon nitride including, but not limiting to CVD, LPCVD, PECVD, glow discharge, thermo catalytic (or hot wire) CVD, and atomic layer deposition (ALD). While not intending to be bound by any specific deposition method, in some embodiments; a mixture of gases such as silane, ammonia, and nitrous oxide can be used for the deposition of silicon nitride in a reactor. The silane flow rate can be in the range of about 50 sccm to about 500 sccm. The ammonia flow rate can be in the range of about 500 sccm to about 7000 sccm and nitrous oxide flow rate can be in the range of around 500 sccm to about 3000 sccm. The operating pressure of the reactor can be from around 3 Torr to around 12 Torr. The silicon nitride can be deposited at a reactor operating temperature ranging from about 350° C. to about 500° C. and typically high frequency RF power can range from about 0 to about 1000 W.
According to various embodiments, the second etch stop layer 220 can be oxygen doped silicon carbide. One of ordinary skill in the art would know that there are various methods for the deposition of silicon oxy-carbide including, but not limiting to CVD, LPCVD, PECVD, and ALD. While not intending to be bound by any specific deposition method, in certain embodiments, a mixture of gases including but not limiting to carbon dioxide, hydrogen, helium, tri-methyl silane (TMS), can be used in a reactor. The flow rate of carbon dioxide, hydrogen, tri-methyl silane, silane, and oxygen can be in the range of about 50 sccm to about 5000 sccm. The flow rate of helium can be in the range of about 100 sccm to about 10000 sccm. The silicon oxy-carbide can be deposited at a reactor operating temperature in the range of about 300° C. to about 400° C. and reactor pressure in the range of about 2.0 Torr to about 10 Torr. The power range for silicon oxy-carbide deposition can be from about 100 W to about 1000 W and low frequency RF power can be from about 50 W to about 400 W.
Turning back to the method of making a semiconductor device 200, the method can further include forming a damascene opening 260 to expose the underlying copper interconnect 240 as shown in
The method can further include forming another etch stop bi-layer stack 201 over the dielectric layer 230 containing the at least one copper interconnect 240, depositing another dielectric layer 230 over the dielectric stack 201, forming a damascene opening, filling the damascene opening with copper or copper alloy and repeating the process as many times as required as shown in
In various embodiments, the exemplary etch stop bi-layer stack 101, as shown in
According to the various embodiments, the exemplary etch stop bi-layer stack 101 of the present teachings either meets or exceeds the reliability requirements for the 45 nm etch stop films. In certain embodiments, the use of four times thinner first etch stop layer 110 in the exemplary etch stop bi-layer stack 101 as compared to the first etch stop layer of the conventional etch stop bi-layer can result in about a 9% reduction in the effective dielectric constant of the etch stop bi-layer stack 101. The about 9% reduction of the effective dielectric constant can result in about a 9% reduction in line to line capacitance. In other embodiments, the electrical breakdown field of the exemplary etch stop bi-layer stack 101 (8.0 MV/cm) can be about 12% higher than the conventional etch stop bi-layer stack (7.15 MV/cm). Furthermore in some embodiments, though the electromigration t50 of the exemplary etch stop bi-layer stack 101 does not differ in value from that of the conventional etch stop bi-layer, there can be, however, a 27% reduction in sigma, where t50 is the time to failure for 50% of the distribution and sigma is the standard deviation of the fail distribution. The reduction of sigma indicates the possibility for longer lifetime on a higher percentage of semiconductor devices.
In certain embodiments, the etch selectivity to the organo silicate glass (ULK-OSG) etch of the exemplary etch stop bi-layer 101 of the present teachings can be the same as that of the conventional etch stop bi-layer. The reason for no difference in the etch selectivity is due to the fact that the second etch stop layer of both the conventional etch stop bi-layer stack and the exemplary etch stop bi-layer stack 101 include a 400 Å thick layer of silicon oxy-carbide. Since, silicon oxycarbide layer is adjacent to the organo silicate glass layer (ULK-OSG), the etch selectivity to ULK-OSG of the exemplary and the conventional etch stop bi-layer can be the same. In some embodiments, the etch stop etch thickness of the exemplary etch stop bi-layer stack 101 can be lower than that of the conventional etch stop bi-layer stack. The reason for the lower etch stop etch thickness of the exemplary etch stop bi-layer stack 101 is probably because the thickness of silicon nitride (about 50 Å) which is the first etch stop layer 110 of the exemplary etch stop bi-layer stack 101 is about one fourth the thickness of corresponding layer of silicon carbo-nitride (about 200 Å), which is the first etch stop layer of the conventional etch stop bi-layer. Silicon nitride is considered to be a better dielectric barrier than the silicon carbon-nitride and therefore the thickness of the silicon nitride, the first etch stop bi-layer 110 of the exemplary etch stop bi-layer stack 101 can be decreased four times without any adverse effect to the reliability.
Photo-poisoning of photoresist is considered to be caused by a diffusion of reactive nitrogeneous species such as amine out of silicon and nitrogen containing layer and into the photo-resist layer. A layer of silicon oxy-carbide between the photoresist and silicon and nitrogen containing layer is known to prevent photo-poisoning. In certain embodiments, both the exemplary and the conventional etch stop bi-layer showed no significant difference in the photo-poisoning effect because the thickness of the silicon oxy-carbide is the same in the two cases. In other embodiments, about 28% reduction in deposition/cleaning cost can be observed in the exemplary etch stop bi-layer stack 101 as compared to the conventional etch stop bi-layer stack due to lower overall etch stop thickness with the silicon nitride thickness reduction.
According to various embodiments, the exemplary etch stop bi-layer 101 including a layer of silicon oxy-carbide 120 over a layer of silicon nitride 110 can provide numerous advantages such as improvement in electrical breakdown field, no impact to sheet resistance due to absence of silane step needed previously to improve adhesion to copper, improvement in electromigration, and/or a reduction in cleaning costs. Further, shorter etch stop times can help with ultra low k preservation and also center-to-edge non-uniformity requirement for over-etch.
According to various embodiments, there is a method of forming a film stack 101 in an integrated circuit. The method can include forming a first etch stop layer 110 of silicon nitride over a semiconductor structure containing at least one copper interconnect, forming a second etch stop layer 120 of oxygen doped silicon carbide over the first etch stop layer 110; and depositing a dielectric layer 130 over the second etch stop layer 120.
In certain embodiments, a semiconductor device 200 can include a semiconductor structure 270 including at least one copper interconnect 240. The semiconductor device 200 can also include a first etch stop layer 210 of silicon nitride disposed over the semiconductor structure 270, a second etch stop layer 220 of silicon oxy-carbide disposed over the first etch stop layer 210 of silicon nitride layer, and a dielectric layer 230 over the second etch stop layer 220.
While not intending to be bound to any particular theory, it is believed that the exemplary etch stop bi-layer meet or exceed the requirements of the 45 nm etch stop films because the first etch stop layer including silicon nitride prevents the formation of copper oxides and the second etch stop layer including silicon oxy-carbide prevents the diffusion of nitrogeneous species.
While the invention has been illustrated with respect to one or more implementations, alterations and/or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations. as may be desired and advantageous for any given or particular function. Furthermore, to the extent that the terms “including”, ”includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
