The subject matter disclosed herein relates to sputtering targets for use in physical vapor deposition (PVD) processes, more specifically, silicon sputtering targets.
In typical sputtering processes, silicon atoms from the sputtering target are deposited onto a substrate in a physical vapor deposition (PVD) atmosphere. Most of the sputtered atoms travel, as desired, directly to the substrate. However, a significant portion of the sputtered particles become scattered in the gas during the PVD process and can deposit on various unintended surfaces of the chamber, such as the shield, and target sidewall or flange.
The scattered sputtered particles that deposit onto the various undesired surfaces of the sputter chamber such as the shield or target sidewall and flange, tend to build-up and flake off during later sputtering processes. Deposition of scattered sputtered particles on the target is especially troublesome. For instance, the repeated heating and cooling of the target, including the undesired deposited particles on the sidewalls of the target, render flaking of the particles even more likely, or may result in chipping or cracking of the target or redeposited particles.
In many cases, these deleterious particles are propelled to the substrate. These particles on the wafer may create uneven sputtered films or defects in the sputtered pattern that can lead to a failed circuit. Target lifetime should be determined primarily by target thickness. In practice, however, the target life is often limited by accumulation of deposits or cracks on the target, particularly in the center, near the edges or on the sidewall portion.
Normal silicon (Si) sputtering targets have a flat top surface and straight sidewall. Redeposited silicon with resistivity and amorphous structure is easily built up at the target surface center and edge areas sputtered in radio frequency physical vapor deposition (RF PVD) systems and processes. This results in target surface chipping or cracking and ultimately a short target life time.
By contrast, the sputtering target of the present invention has an enhanced surface profile that surprisingly reduces redeposition of target material and depresses target chipping thereby increasing the target lifetime, improving target sputtering performance and the deposited film quality.
Accordingly, in one embodiment, a sputtering target assembly with an enhanced surface profile is disclosed. The target assembly may comprise a target blank and a backing plate. The target blank may have at least one planar surface with a thickness T1 and a concave center with a thickness T2, wherein T2 may be less than T1. In another embodiment, the target blank may further comprise a beveled edge with a thickness T3 around the perimeter of the target blank. The thickness T3, may be less than T1. In another embodiment, the sputtering target assembly may be generally circular and the first beveled edge may be a continuous beveled edge around the circumference of the target blank.
In yet another embodiment, the target blank may comprise silicon (Si). The silicon target blank may have a diameter up to 550 mm and can be intrinsic, p-type doped, or n-type doped. The silicon blank can have polycrystalline, single crystal, or semi-single crystal structure. In yet another embodiment, the target blank may comprise n-type doped silicon or silicon with n-type conductivity.
In another embodiment, the backing plate may be made of materials including, but not limited to, Al, Mo, Ti, Zr, Ta, Hf, Nb, W, Cu, combinations thereof, and alloys thereof, such as Mo/Cu or Ti/Al composites. In one embodiment, the backing plate may be pure molybdenum with a purity of 2N5 or higher. In yet another embodiment, the target backing plate may be a molybdenum copper composite with copper diffusion bonded or coated to a molybdenum blank. In another embodiment, the backing plate may be a titanium and aluminum composite with aluminum diffusion bonded or coated to a titanium blank.
Methods of manufacturing silicon sputtering targets with an enhanced surface profile are also disclosed. The methods may comprise machining a target blank to have a machined surface having at least one planar surface with a thickness T1 and a concave center with a thickness T2, wherein T2 may be less than T1. In another embodiment, the method may further comprise machining a first beveled edge with a thickness T3 around the perimeter of the target blank. The thickness T3 may be less than T1.
In another embodiment, the target blank may be solder bonded and/or braze bonded to a backing plate to form a target assembly. In yet another embodiment, the solder may be, but is not limited to, indium, tin-silver, laminated foil, and brazed foil.
In another embodiment, the target blank may be generally circular and the first beveled edge may be a continuous beveled edge around the circumference of the target blank. The machined surface may be cleaned and polished after machining to the desired smoothness. The target blank may be obtained by cutting a silicon (Si) slice from a Si ingot and then machining the target blank as described above. Thus, in another embodiment, the target blank may comprise silicon (Si).
The sputtering target assembly of the present invention may comprise a target blank and a backing plate. The target blank may have at least one planar surface with a thickness T1 and a concave center with a thickness T2, wherein T2 is less than T1. In another embodiment, the target blank may further comprise a beveled edge with a thickness T3 around the perimeter of the target blank. The thickness T3 may be less than T1.
The target blank may be rectangular or circular with a concave center 4 with a thickness T2 that is recessed with respect to the planer surface. The concave center 4 may be a depression with a flat bottom surface and sides that are generally perpendicular with respect to the bottom surface. In one embodiment, the target blank may have a rectangular cross-section. In another embodiment, the target blank may be circular. The target blank may have a first beveled edge with a thickness T3 around the outer perimeter or circumference of the target blank. The thickness T3 may be less than T1. In another embodiment, the sputtering target assembly may be generally circular and the first beveled edge may be a continuous beveled edge around the circumference of the target blank. Turning to
As shown in
The edge 8 may a have a first beveled edge 6 around the circumference of the target. As shown in
The length of the first and second beveled edges 6 and 10 may be the same or different. The beveled edge (6 or 10) length may vary and may be any suitable length anticipated by those of ordinary skill of the art.
In one embodiment, the target blank may have an outer diameter OD1. In one embodiment, the OD1 may be less than or equal to 550 mm. The bevel of the first beveled edge 6, may start from a distance, D from the center of the circular target 2, and extend to the target's outer diameter OD1 and form a concentric circle with an inner diameter ID1 within the target's outer diameter OD1. ID1 may range from equal to or greater than about 81% to about 99% of the target blank's outer diameter OD1. In another embodiment, ID1 may range from about 85% to about 95% of the target blank's outer diameter OD1. In yet another embodiment, ID1 may be about 88% of the target blank's outer diameter OD1.
The concave center 4 may have an outer diameter OD2. OD2 may range from about 50% to about 80% of the target blank's diameter OD1. The remaining area of the target between the outer diameter OD2 of the concave center 4 and the inner diameter ID1 may be a planar or flat surface 5. The remaining area of the target with a planar or flat surface 5 may have a thickness, T1.
This is in contrast to the prior art, or flat, target 12 shown in
Without limiting this disclosure to one theory of operation, it is thought that redeposition layers have a different structure and higher resistivity and different type of conductivity, (e.g. n-type redeposition can form on P-type target materials or vice versa) as compared to the target matrix material. This may result in local current or energy that is generated on the accumulated redeposition layers, thereby causing chipping or cracking of the redeposition layers and target material itself during the sputtering process. Test results showed that redeposited material comprised mostly n-type silicon whereas the blank target material comprised mostly p-type silicon. The n-type to p-type junction between the blank target material and the n-type redeposited material may also be prone to chipping or cracking.
Accordingly, in another embodiment, the target blank may comprise silicon and can be intrinsic, p-type doped, or n-type doped or have n-type conductivity. The silicon blank can have polycrystalline, single crystal, or semi-single crystal structure. In yet another embodiment, the silicon blank may be made of n-type doped silicon to avoid forming junctions between more than one type of silicon thereby reducing chipping or cracking.
The backing plate may be made of materials including, but not limited to, Al, Mo, Ti, Zr, Ta, Hf, Nb, W, Cu, combinations thereof, and alloys thereof. Exemplary combinations of backing plate materials include Mo/Cu or Ti/Al composites. In one embodiment, the backing plate may be pure molybdenum with a purity of 2N5 or higher. In yet another embodiment, the backing plate blank may be a molybdenum copper composite with copper diffusion bonded or coated to a molybdenum blank. In another embodiment, the baking plate may be a titanium and aluminum composite with aluminum diffusion bonded or coated to a titanium blank.
The target 2 may have an improved target lifetime over the prior art target 12. Accordingly, in one embodiment, the sputtering target assembly may have a lifetime greater than 250 kW·h or greater than 5,000 wafers.
Methods of manufacturing silicon sputtering targets with an enhanced surface profile are also disclosed. The methods may comprise machining a target blank to have a machined surface having at least one planar surface with a thickness T1 and a concave center with a thickness T2, wherein T2 may be less than T1. In another embodiment, the method may further comprise machining a first beveled edge with a thickness T3 around the perimeter of the target blank. The thickness T3 may be less than T1.
In another embodiment, the target blank may be solder bonded and/or braze bonded to a backing plate to form a target assembly. In yet another embodiment, the solder may be, but is not limited to, indium, tin-silver, brazed foil, and laminated foil. An exemplary laminated foil is NanoFoil® available from Indium Corporation, Utica, N.Y.
In another embodiment, the target blank may be generally circular and the edge may be a continuous beveled edge around the circumference of the target blank. The machined surface may be cleaned and polished after machining to the desired smoothness. The target blank may be obtained by cutting a silicon (Si) slice from a Si ingot and then machining the target blank as described above. Thus, in another embodiment, the target blank may comprise silicon (Si).
Films prepared using the target 2 may have a film uniformity of about 1-2% versus about 5% for films made with a prior art target 12. In some embodiments of the invention, the target 2, may produce films with low particle counts, equal to or less than, 5 particles per wafer. The target 2, may also have a short burn-in time less than or equal to 8 hours.
A flat, prior art test target 32 as shown in
The test target 32 thickness after 201 kW·h was measured and plotted to create an erosion profile shown in
Various portions (A-I) shown in
A target 2, according to one aspect of the invention, with an improved profile comprising a concave center 4 and a first beveled edge 6 was also sputtered in a RF PVD process. The target 2 had an improved target lifetime over the test target 32 with the profile 12. The target had a lifetime greater than 250 kW·h or greater than 5,000 wafers. By reducing the amount of redeposited material on the target, the target lifetime may increase. Reducing the amount of redeposited material may reduce the amount of flaking or chipping in the target thereby reducing the amount of particles that are propelled to the substrate or wafer. Accordingly, in some embodiments of the invention, the target 2, may produce films with low particle counts, equal to or less than, 5 particles per wafer.
Likewise, films prepared using the inventive target may exhibit a film uniformity of about 1-2% versus about 5% for films made with a prior art target 12. The inventive target, may also have a shorter burn-in time compared to a prior art target 12. The burn-in time of the target 2 may be less than or equal to 8 hours.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
This PCT application claims the priority benefit of U.S. Provisional Patent Application Ser. No. 61/848,472 filed Jan. 4, 2013 and herein incorporated in its entirety by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/US2014/010142 | 1/3/2014 | WO | 00 |
Number | Date | Country | |
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61848472 | Jan 2013 | US |