Patent Application
20200083060
The present invention relates to a silicon wafer and particularly to a silicon wafer suitable even for a low-temperature device process.
An epitaxial silicon wafer is known, which has a sufficient gettering capability even when the heat treatment in a production step for semiconductor devices is performed under a low temperature (Patent Document 1: JP2014-201468A). The epitaxial silicon wafer is cut out from a silicon single crystal grown by the Czochralski method and has a diameter of 300 mm or more. When the crystal is grown, the required time for lowering the temperature of each part of the silicon single crystal from 800° C. to 600° C. is 450 minutes or less. The interstitial oxygen concentration is 1.5×1018 to 2.2×1018 atoms/cm3 (old ASTM), and the nitrogen concentration and the carbon concentration are not higher than respective predetermined values. The entire surface of the silicon wafer consists of a COP region. A wafer bulk part at the epitaxial layer surface has a BMD density of 1×104/cm2 or less after heat treatment of 1000° C.×16 hours.
In the above conventional technique, however, long-time heat treatment of 1000° C.×16 hours is performed as evaluation heat treatment to ensure the gettering capability owing to the BMD density after the heat treatment. It is thus necessary to ensure the gettering capability with more reliable evaluation heat treatment adapted to a lowered temperature of the heat treatment in a production step for semiconductor devices.
A problem to be solved by the present invention is to provide a silicon wafer suitable even for a low-temperature device process.
According to a first aspect of the present invention, the above problem is solved by providing a silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 μm to 285 μm from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C≤X≤1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec, the time Y and the temperature X satisfying Y=7.88×1067×X−2.25.
According to a second aspect of the present invention, the above problem is solved by providing a silicon wafer having an average BMD size of 16 nm or more and 28 nm or less in a region of 80 μm to 285 μm from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.≤X≤1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec, the time Y and the temperature X satisfying Y1=7.88×1067×X−2.25 and 1.0≤Y/Y1≤1.5.
According to a third aspect of the present invention, the above problem is solved by providing a silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 μm to 285 μm from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.≤X≤1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec, the time Y and the temperature X satisfying Y=7.88×1067×X−2.25,
the silicon wafer having an average BMD size of 16 nm or more and 28 nm or less in the region of 80 μM to 285 μm from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.≤X≤1000° C.) for a time Y (min) and then subjected to the infrared tomography method in which the laser power is set to 50 mW and the exposure time of the detector is set to 50 msec, the time Y and the temperature X satisfying Y1=7.88×1067×X−2.25 and 1.0≤Y/Y1≤1.5.
In the above invention, the surface may be formed with an epitaxial layer having a thickness of 1 to 5 μm. Additionally or alternatively, the silicon wafer may have a nitrogen concentration of 1×1012 to 5×1014 atoms/cm3 and an oxygen concentration of 8×1017 to 15×1017 atoms/cm3.
According to the present invention, when the time is represented by Y (min) and the temperature is represented by X (° C., 700° C.≤X≤1000° C.), the evaluation heat treatment is performed with the time Y and the temperature X which satisfy Y=7.88×1067×X−2.25, and the gettering capability can therefore be ensured with high reliability under a condition of relatively low temperature and short time. As a result, a silicon wafer suitable even for a low-temperature device process can be provided.
The silicon wafer according to the present invention is a silicon wafer that is obtained by slicing a silicon single crystal grown, for example, by the Czochralski method, and the surface of the silicon wafer is formed with an epitaxial layer as necessary. The thickness of the epitaxial layer is preferably 1 to 5 μm. When growing the silicon single crystal, the nitrogen concentration in the crystal is preferably 1×1012 to 5×1014 atoms/cm3 and the oxygen concentration is preferably 8×1017 to 15×1017 atoms/cm3.
The density and average size of oxygen precipitates (BMD) of the silicon wafer obtained through the above-described production steps can be evaluated, for example, using a crystal defect measurement apparatus (such an apparatus is available from Semilab Japan KK) by an infrared tomography method after performing heat treatment for evaluation. As evaluation indices, the BMD density and average BMD size in a region of 80 μm to 285 μM from the surface of an epitaxial silicon wafer are measured under a specific measurement condition in which the laser power of the crystal defect measurement apparatus by an infrared tomography method is set to 50 mW and the exposure time of a detector (CCD camera) is set to 50 msec.
Here, according to the knowledge acquired by the present inventors, provided that the temperature X of the heat treatment for evaluation is 700° C. to 1000° C. and the time Y of the heat treatment satisfies Y=7.88×1067×X−2.25, when the BMD density is 5×108/cm3 or more, a silicon wafer having sufficient gettering capability can be obtained, for example, even in a low-temperature device process of 1000° C. or less, which is included in a semiconductor device process. Conversely, provided that the same heat treatment for evaluation is performed, when the BMD density is less than 5×108/cm3, sufficient gettering capability is not exhibited, for example, in a low-temperature device process of 1000° C. or less, which is included in a semiconductor device process.
Moreover, according to the knowledge acquired by the present inventors, provided that the temperature X of the heat treatment for evaluation is 700° C. to 1000° C. and the time Y of the heat treatment satisfies Y1=7.88×1067×X−2.25 and 1.0≤Y/Y1≤1.5, when the average BMD size is 16 nm or more and 28 nm or less, a silicon wafer without occurrence of dislocations can be obtained. Conversely, provided that the same heat treatment for evaluation is performed, when the average BMD size is less than 16 nm or exceeds 28 nm or the time Y of the heat treatment does not satisfy 1.0≤Y/Y1≤1.5, dislocations occur.
Thus, to obtain a silicon wafer that exhibits sufficient gettering capability in a low-temperature device process and does not cause dislocations, the silicon wafer more preferably has a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 μm to 285 μm from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.≤X≤1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec, the time Y and the temperature X satisfying Y=7.88×1067×X−2.25, the silicon wafer having an average BMD size of 16 nm or more and 28 nm or less in the region of 80 μm to 285 μm from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.≤X≤1000° C.) for a time Y (min) and then subjected to the infrared tomography method in which the laser power is set to 50 mW and the exposure time of the detector is set to 50 msec, the time Y and the temperature X satisfying Y1=7.88×1067×X−2.25 and 1.0≤Y/Y1≤1.5.
Epitaxial wafers were obtained through growing various silicon single crystals with varying nitrogen doping concentration (1×1012 to 5×1014 atoms/cm3) and oxygen concentration (8×1017 to 15×1017 atoms/cm3) in the crystals using the Czochralski method, preparing silicon wafers from the silicon single crystals, and performing epitaxial growth on these silicon wafers under the same condition (the thickness of the epitaxial layers was 1 to 5 μm).
These epitaxial wafers were subjected to evaluation heat treatment at various temperatures and times, and oxygen precipitates (BMD) densities of the heat-treated epitaxial silicon wafers were measured using a crystal defect measurement apparatus (available from Semilab Japan KK) by an infrared tomography method. The BMD density in a region of 80 μm to 285 μm from the surface of each epitaxial silicon wafer was measured under a specific measurement condition in which the laser power was set to 50 mW and the exposure time of a detector (CCD camera) was set to 50 msec.
The evaluation results of the BMD densities are illustrated in
On the assumption of contamination with heavy metal, the epitaxial silicon wafers of the same level for which the above measurement was performed were contaminated with Ni of 1×1012/cm2, and heat treatment simulating low-temperature device treatment of a semiconductor production process was then performed (Heat Treatment 1 or Heat Treatment 2 described below). After the simulated heat treatment, the silicide formed on the surface of each wafer was made into pits (shallow pits) using a Wright etching liquid, and the presence or absence of shallow pits was observed.
First step: Held at 650° C. for 100 minutes
Second step: Held at 900° C. for 20 minutes
Third step: Held at 825° C. for 30 minutes
Fourth step: Held at 725° C. for 100 minutes
(In all cases, the heating/cooling rate was 5° C./min.)
First step: Held at 650° C. for 100 minutes
Second step: Held at 1000° C. for 60 minutes
Third step: Held at 875° C. for 30 minutes
Fourth step: Held at 825° C. for 100 minutes
(In all cases, the heating/cooling rate was 5° C./min.)
As a result, no shallow pits were observed in the epitaxial silicon wafers of the heat treatment level of “∘” indicated in
That is, in a low-temperature device process of a semiconductor production process, after heat treatment of Y=7.88×1067×X−2.25 (700° C.≤X≤1000° C.) with the time Y (min) and the temperature X (° C.) (i.e., the time Y is set so as not to be less than a certain value defined by the temperature X), when the BMD density in a region of 80 μm to 285 μm from the surface of an epitaxial silicon wafer is measured using a crystal defect measurement apparatus (available from Semilab Japan KK) by an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector (CCD camera) is set to 50 msec, the wafer exhibiting the gettering capability is a wafer on which the detected BMD density is 5×108/cm3 or more. It is to be noted that the measurement upper limit of the above crystal defect measurement apparatus is 2.5×1010/cm3, so the upper limit when using the apparatus is this numerical value.
Epitaxial wafers were obtained through growing various silicon single crystals with varying nitrogen doping concentration (1×1012 to 5×1014 atoms/cm3) and oxygen concentration (8×1017 to 15×1017 atoms/cm3) in the crystals using the Czochralski method, preparing silicon wafers from the silicon single crystals, and performing epitaxial growth on these silicon wafers under the same condition (the thickness of the epitaxial layers was 1 to 5 μm).
These epitaxial silicon wafers were subjected to the evaluation heat treatment at various temperatures and times as described in Example 1, and the average sizes (nm) of oxygen precipitates (BMD) of the heat-treated epitaxial silicon wafers were measured using a crystal defect measurement apparatus (available from Semilab Japan KK) by an infrared tomography method. The average BMD size (nm) in a region of 80 μm to 285 μm from the surface of each epitaxial silicon wafer was measured under a specific measurement condition in which the laser power was set to 50 mW and the exposure time of a detector (CCD camera) was set to 50 msec.
The evaluation heat treatment at that time was performed as follows. First, from the relationship represented by Y1=7.88×167×X−2.25 (700° C.≤X≤1000° C.), the temperature X (° C.) was initially determined to obtain the time Y1 . Then, the evaluation heat treatment was carried out with the actual treatment time Y within a range of 1.5Y1>Y>1.0 (i.e., 1.5>Y/Y1>1.0).
The heat treatment for low-temperature device production described in Example 1 (the above Heat Treatment 1 or Heat Treatment 2) was performed for the epitaxial silicon wafers grown with the BMDs of various sizes as described in the above evaluation heat treatment. After the heat treatment, as a thermal-stress load test, millisecond annealing at a maximum achieving temperature of 1200° C. was sequentially carried out five times for the epitaxial silicon wafers using a flash lamp annealing heat treatment furnace. Thereafter, Wright etching was performed on the surface of each epitaxial silicon wafer, and the presence or absence of dislocation etch pits on the surface of the epitaxial silicon wafer was confirmed.
The results are listed in Table 1. In the columns of “Thermal-stress load test” in Table 1, epitaxial silicon wafers on which dislocation etch pits were observed (results of the thermal-stress load test were not good) are indicated by “×,” and epitaxial silicon wafers on which no dislocation etch pits were observed (results of the thermal-stress load test were good) are indicated by “∘.” Large warpage occurred in the epitaxial silicon wafers on which dislocation etch pits were observed.
In the epitaxial silicon wafers with average BMD sizes of more than 28 nm (Samples 5, 8, 10, 13, and 14) among the epitaxial silicon wafers with Y/Y1 of 1 to 1.5, dislocations occurred after the flash lamp heat treatment subsequent to the low-temperature device heat treatment, and warpage occurred in the wafers. It can be considered that, in these samples, Slip dislocations occurred due to the BMDs grown in the low-temperature device production. In contrast, occurrence of dislocations was not observed on the epitaxial silicon wafers with average BMD sizes of 16 nm to 28 nm, which thus exhibited good results. In Sample 13, however, dislocations occurred despite the average BMD size being 28 nm or less. This is because Y/Y1 is 2 and not 1.5 or less, which is not appropriate as an index representing the wafer strength.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2017-124294 | Jun 2017 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2018/023218 | 6/19/2018 | WO | 00 |
