BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be more clearly understood from consideration of the following detailed description and drawings in which:
FIG. 1 (prior art) is a top view representative of a strip containing several arrays of numerous block-molded semiconductor devices prior to singulation showing an overview of an example of a context in which methods embodying the invention may be practiced;
FIG. 2 (prior art) is a side view of the strip of FIG. 1 containing several arrays of numerous block-molded semiconductor devices prior to ball attach and singulation shown for the purpose of illustrating an example of warpage in a context in which methods embodying the invention may be practiced;
FIG. 3A is a partial side view of an array of joined block-molded semiconductor devices illustrating an example of steps in the methods of preferred embodiments of the invention;
FIG. 3B is a partial side view of the array of FIG. 3A containing block-molded semiconductor devices illustrating an example of steps in the methods of preferred embodiments of the invention;
FIG. 3C is a partial side view of the block-molded semiconductor devices of FIGS. 3A and 3B illustrating an example of further steps in the methods of preferred embodiments of the invention;
FIG. 4A is a partial side view of an array of joined block-molded semiconductor devices illustrating an example of steps in the methods of alternative preferred embodiments of the invention;
FIG. 4B is a partial side view of the array of FIG. 4A containing block-molded semiconductor devices illustrating an example of further steps in the methods of preferred embodiments of the invention;
FIG. 4C is a partial side view of the block-molded semiconductor devices of FIGS. 4A and 4B illustrating an example of further steps in the methods of preferred embodiments of the invention;
FIG. 5 is a partial side view of an example of alternative steps in representative embodiments of block-molded semiconductor devices pursuant to methods of the invention;
FIG. 6 is a simplified process flow diagram providing an alternative overview of a method for fabricating integrated circuit chip packages according to the invention; and
FIG. 7 is a simplified process flow diagram providing an overview of an alternative embodiment of a method for fabricating integrated circuit chip packages according to the invention.
References in the detailed description correspond to like references in the various drawings unless otherwise noted. Descriptive and directional terms used in the written description such as first, second, top, bottom, upper, side, etc., refer to the drawings themselves as laid out on the paper and not to physical limitations of the invention unless specifically noted. The drawings are not to scale, and some features of embodiments shown and discussed are simplified or amplified for illustrating the principles, features, and advantages of the invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
Referring initially to FIG. 1 (prior art), a top view, and FIG. 2 (prior art), a corresponding side view, the figures are representative of an arrangement 10 of arrays 12 of block-molded semiconductor device assemblies 14 prior to the singulation of the individual packages 14. In conventional fashion, semiconductor package arrays 12 are formed by block-molding, for example, on a leadframe or multilayer substrate strip 16. The individual semiconductor packages 14 that are yet to be singulated from the semiconductor package arrays 12 are typically held down by the application of a vacuum, supported on a tape, held in a jig, or otherwise secured for singulation. Conventionally, the individual packages 14 are sawn apart from one another by sawing through the assembly 10 in a single pass along saw streets 18 of sacrificial material between the individual packages 14. Often, the array 10 may become warped, as shown with some exaggeration in FIG. 2, leading to problems with singulation, ball attachment, or both.
Now referring to the partial side views of FIGS. 3A-3C, a portion of a block-molded package assembly 100 is shown containing an array 102 of encapsulated ICs 104 prepared using block-molding techniques familiar to those skilled in the arts. Preferably, saw streets 105 are provided in the ordinary manner to facilitate singulation. The array 102 is held firmly in place for sawing, preferably using a vacuum chuck to force the array 102 down against a flat surface. As shown in FIG. 3B, a series of partial cuts 106 are made beginning at the outer surface 108 of the encapsulant 110. The partial cuts 106 are preferably made in a predetermined singulation pattern using conventional sawing equipment. It should be recognized that the partial cuts 106 are a departure from conventional singulation methods, in that they do not extend completely through all layers of the package assembly structure 100. Making the partial cuts reduces or eliminates warpage of the array 102 and facilitates effective securing of the array 102 by the vacuum chuck or other securing method. As can be seen in FIG. 3C, final cuts 112 are subsequently made substantially aligned with the partial cuts 106 of FIG. 3B such that the individual packages 114 are ultimately severed from one another and from any remaining material 116, such as scrap. It should be appreciated by skilled practitioners of the relevant arts that the partial cutting step may be reiterated one or more additional times intermediate to the final cutting step. It should also be understood that the partial and final cutting steps may be performed in a variety of patterns selected based on the particular application, and that the cutting steps may be performed either by repeated use of the same equipment or by using different equipment in sequence. For example, it may in some instances be advantageous to make the partial cuts and final cuts in two or more passes with the same saw blade. In other applications, it may be desirable to use different equipment for the sequence of cuts, e.g., using one saw blade for one or more partial cuts followed by another saw blade for the final cuts.
An example of one alternative embodiment of a singulation method of the invention is shown in partial side view in FIGS. 4A-4C. Referring first primarily to FIG. 4A, a portion of a block-molded package assembly 120 is shown containing an array 122 of encapsulated ICs 124. A series of partial cuts 126, shown in FIG. 4B, are made beginning at the outer surface 128 and extending part way, but not entirely, through the package assembly 120, preferably in a predetermined singulation pattern using conventional cutting equipment. The partial cuts 126 extend into, but not through, the array structure 120. As illustrated in FIG. 4C, final cuts 130 are thereafter made substantially in alignment with the partial cuts 126 of FIG. 4B such that the individual packages 132 are severed from one another, and from any additional material 134. As in the case of the above examples herein, variations in the method are possible without departure from the invention, for example, the partial cutting step may be repeated one or more additional times intermediate to the final cutting step. It should also be understood that the partial and final cutting steps may be performed by cutting tools approaching from the same or opposite surfaces of the block-molded device array.
An additional technique which may be used with the methods of the invention is to implement steps for including a cutting guide in the block-molded assembly in order to facilitate singulation. As shown in FIG. 5, cutting guides 140, 142, may be provided in the encapsulant 110 of an array 102 of suitably prepared ICs 104. The cutting guides 140, 142, are preferably formed of elevated ridges 140 or indented trenches 142 for use in guiding the cutting tool, e.g. saw, particularly for the making of the initial partial cuts, although alternative cutting guidance or techniques may also be used.
Referring now to FIG. 6, a process flow diagram of exemplary methods for fabricating leadframe packages in accordance with the present invention is shown. This example of a preferred embodiment of the invention includes a package array based on a supporting metal leadframe, such as a Quad Flat No-lead (QFN) package. The method includes providing a collective leadframe structure 300 for packages that are to be assembled thereupon and subsequently singulated with respective predetermined package shapes and sizes. The required IC chips are affixed to the leadframes at selected locations, as shown at step 302. The packages are assembled in a block with encapsulant for forming individual mold caps on the leadframes 304. The arrayed packages preferably have sufficient saw streets between them to allow for cutting. The packages are cut, preferably by sawing, using successive partial 106, 126, and final cuts 112, 130, to singulate the packages, preferably reducing the dimensions of the packages to the respective predetermined package sizes.
As depicted in the simplified process flow diagram of FIG. 7, a process flow diagram of exemplary methods for fabricating BGA packages in accordance with the present invention is shown. The method includes providing a collective substrate structure 400 for packages that are to be assembled thereupon and subsequently singulated with respective predetermined package shapes and sizes. The required IC chips are affixed to the appropriate substrate locations, as shown at step 402. The packages are assembled in a block with encapsulant for forming individual mold caps over the chips 404. The arrayed packages preferably have sufficient saw streets between them to allow for cutting. The packages are cut, preferably by sawing successive partial cuts 106, 126. Solder balls are preferably attached to the package 406 for use in further employment of the packaged device in electronic apparatus. Final cuts 112, 130, ultimately singulate the packages, preferably reducing the dimensions of the packages to the respective predetermined package sizes. It should be noted that additional steps, or variations in the order of the steps, may be implemented without departure from the invention. For example, ball attachment may be performed before or subsequent to the partial cutting step(s). The presence of the partial cuts reduces or eliminates warpage, providing a flat surface suited for receiving solder balls.
The resulting package structure is an economical high integrity package that benefits from the advantages of block-mold package formation and the advantages of saw singulation while eliminating or reducing one or more of the disadvantages associated with warpage that can accompany traditional singulation methods. The invention may be used with conventional molding, ball attach, and singulation processes and tools, and may be adapted for manufacturing semiconductor packages in a wide of variety of dimensions and configurations. The methods of the invention provide one or more advantages including but not limited to reducing warpage of block-molded semiconductor devices during manufacturing. While the invention has been described with reference to certain illustrative embodiments, those described herein are not intended to be construed in a limiting sense. For example, variations or combinations of steps in the embodiments shown and described may be used in particular cases without departure from the invention. Various modifications and combinations of the illustrative embodiments as well as other advantages and embodiments of the invention will be apparent to persons reasonably skilled in the arts upon reference to the drawings, description, and claims.
Patent Application
20080003718
