Patent Application
20200227583
Embodiments of the present disclosure are in the field of renewable energy and, in particular, apparatuses for, and methods of, fabricating solar cell emitter regions using ion implantation.
Photovoltaic cells, commonly known as solar cells, are well known devices for direct conversion of solar radiation into electrical energy. Generally, solar cells are fabricated on a semiconductor wafer or substrate using semiconductor processing techniques to form a p-n junction near a surface of the substrate. Solar radiation impinging on the surface of, and entering into, the substrate creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage differential between the doped regions. The doped regions are connected to conductive regions on the solar cell to direct an electrical current from the cell to an external circuit coupled thereto.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics can be combined in any suitable manner consistent with this disclosure.
Terminology. The following paragraphs provide definitions and/or context for terms found in this disclosure (including the appended claims):
“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps.
“Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/components include structure that performs those task or tasks during operation. As such, the unit/component can be said to be configured to perform the task even when the specified unit/component is not currently operational (e.g., is not on/active). Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, sixth paragraph, for that unit/component.
“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” pair of mask openings does not necessarily imply that this pair is the first pair in a sequence; instead the term “first” is used to differentiate this pair from another pair (e.g., a “second” pair of mask openings).
“Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.
“Inhibit”—As used herein, inhibit is used to describe a reducing or minimizing effect. When a component or feature is described as inhibiting an action, motion, or condition it may completely prevent the result or outcome or future state completely. Additionally, “inhibit” can also refer to a reduction or lessening of the outcome, performance, and/or effect which might otherwise occur. Accordingly, when a component, element, or feature is referred to as inhibiting a result or state, it need not completely prevent or eliminate the result or state.
In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, “side”, “outboard”, and “inboard” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
Placement of the doped regions within the substrate is an important characteristic of a solar cell as it is directly related to the capability of the solar cell to generate power. More particularly, accuracy and uniformity of patterns of the doped regions is directly related to an efficacy of the solar cell. Accordingly, apparatuses and methods for accurately and uniformly forming doped regions within the substrate during the manufacture of solar cells is generally desirable.
Apparatuses for, and methods of, fabricating solar cell emitter regions using ion implantation, and the resulting solar cells, are described herein. In the following description, numerous specific details are set forth, such as specific process operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known fabrication techniques are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Disclosed herein are apparatuses for, and methods of, fabricating solar cells, and more particularly, solar cell emitter regions. In one embodiment, a solar cell emitter region fabrication apparatus includes a plasma source and a semiconductor wafer having a top surface. The apparatus includes a species mask located between the plasma source and the semiconductor wafer. Furthermore, the species mask can include several mask openings sized and located to compensate for causes of non-uniformity in solar cell emitter regions. More particularly, the species mask can include mask openings having respective opening widths and respective opening pitches. The opening widths and/or pitches can be nonuniform such that species from the plasma source pass through the mask openings to directly implant into the top surface of the semiconductor wafer. The implemented species can form several emitter region fingers in the semiconductor wafer, and the fingers can have uniform finger widths and uniform finger pitches.
To provide context, current methods of printing emitter region fingers in solar cell wafers through mask and ion implantation result in emitter region fingers having nonuniform width and/or pitch. Uniformity of finger width and pitch, however, is critical to cell performance. As described below, multiple factors can cause the non-uniformities. By way of example, the factors include temperature gradients in the solar cell wafers and divergence of an ion beam used to implant ions in the solar cell wafers. To date, there is no well-established solution for controlling such factors. Furthermore, proposed solutions for controlling such factors directly would likely be costly and time-consuming to implement. The solar cell emitter region fabrication apparatus described below, however, provides an inexpensive and quickly implementable solution to compensate for ion beam non-uniformity, rather than controlling the contributing factors directly.
Referring to
Semiconductor wafer 104 can include a silicon layer and/or a thin oxide layer disposed on a substrate. For example, the substrate can be a mono crystalline silicon substrate or a polycrystalline silicon substrate. The substrate can be a single crystalline N-type doped silicon substrate. It is to be understood, however, that semiconductor wafer 104 can include a layer, such as a multi-crystalline or amorphous silicon layer, disposed on a global solar cell substrate. In any case, semiconductor wafer 104 can include a top surface 108 facing plasma source 102.
In an embodiment, solar cell emitter region fabrication apparatus 100 includes a species mask 110 disposed between plasma source 102 and semiconductor wafer 104. For example, species mask 110 can be a shadow mask, e.g., a graphite shadow mask. Species mask 110 can include several mask openings 112 extending from a first side of species mask 110 facing plasma source 102 to a second side of species mask 110 facing semiconductor wafer 104. The mask openings 112 can form a slit pattern. Accordingly, species can travel directly from plasma source 102 through mask openings 112 to top surface 108 of semiconductor wafer 104. More particularly, mask openings 112 can pass or transmit the species from plasma source 102 to semiconductor wafer 104 such that the species implant into top surface 108. That is, a dopant impurity species of a conductivity type can be implanted in semiconductor wafer 104. Accordingly, emitter region fingers 114 can be printed directly on semiconductor wafer 104. Such direct printing can be contrasted with, e.g., patterning using optical lithography through photoresists. The implanted dopant impurity species form several emitter region fingers 114 on semiconductor wafer 104.
Ion beam 106 can include P+ dopant atoms, and thus, emitter region fingers 114 can be referred to as p-fingers. In contrast, ion beam 106 can include N+ dopant atoms, and thus, emitter region fingers 114 can be referred to as n-fingers. In an embodiment, boron is implanted to form the p-fingers, which imparts etch resistance to the p-fingers, and nitrogen is implanted to form the n-fingers. In an operation (not shown), the non-implanted regions of semiconductor wafer 104, e.g., the areas of top surface 108 laterally between emitter region fingers 114, can be etched by a selective etch process to preserve the modified p-doped and n-doped regions. Accordingly, interdigitated p-fingers and n-fingers can be formed in top surface 108 of semiconductor wafer 104. The interdigitated p-fingers and n-fingers can be formed by successive implantation processes utilizing a same or different mask 110.
Referring to
Still referring to
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Non-uniformity of finger pitch 204 and finger width 202 of emitter region fingers 114 as described above with respect to
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Narrow opening width 604 can result in a smaller angle of divergence of ion beam 106 as the species pass through lateral opening 506, and thus, emitter region finger 114 under lateral opening 506 can have a same finger width 202 as emitter region finger 114 under middle opening 502, despite narrow opening width 604 being smaller than wide opening width 602. In an embodiment, finger pitch 204 between emitter region fingers 114 can match distances between mask openings 112, e.g., finger pitches 204 can be uniform. In some scenarios, however, finger pitches 204 can vary even though finger widths 202 are corrected to be uniform. Accordingly, solutions for correcting pitch non-uniformity may be needed as described below.
Referring to
Electrostatic chuck 702 can induce a temperature gradient 706 within semiconductor wafer 104. For example, temperature gradient 706 of semiconductor wafer 104 can increase radially outward from center 704 such that a temperature of semiconductor wafer 104 is greater nearer to an outward edge of the wafer than a temperature of semiconductor wafer 104 nearer to centerline 504. Dynamic heating of semiconductor wafer 104 by electrostatic chuck 702, mask 110, and/or the ion beam can cause thermal expansion of the wafer such that top surface 108 expands outward while the ion beam impinges upon the surface. Accordingly, emitter region fingers 114 nearer to center 704 can be narrower than emitter region fingers 114 nearer to the rim of semiconductor wafer 104 because the surface can float under the impinging beam. Furthermore, a finger pitch 204 between pairs of laterally disposed emitter region fingers 114 can be less than finger pitch 204 between pairs of emitter region fingers 114 near center 704.
Referring to
In an embodiment, the opening widths of mask openings 112 can also vary across species mask 110. For example, mask openings 112 nearer to the rim of species mask 110 can have smaller opening widths than mask openings 112 nearer to centerline 504 of species mask 110.
Based on the nonuniform opening widths and/or opening pitches in species mask 110, ion beam 106 can pass through species mask 110 and impinge on semiconductor wafer 104 such that several emitter region fingers 114 having uniform finger widths 202 and uniform finger pitches 204 are formed on top surface 108. Accordingly, nonuniform width and pitch of emitter region fingers 114 can be corrected by compensating for one or both of opening widths or opening pitches in species mask 110.
In an embodiment, solar cell emitter region fabrication apparatus 100 can include a second species mask (not shown) between plasma source 102 and semiconductor wafer 104. The second species mask can be provided between plasma source 102 and species mask 110 or between species mask 110 and semiconductor wafer 104. Openings in the second species mask can be manipulated to alter one or more dimensions of or a uniformity of the ion beam flux. For example, reducing a width of openings in the second species mask can reduce a dimension of the ion beam flux to make the ion beam spots impinging on semiconductor wafer 104 the same. That is, the ion beam spots can have similar dimensions to form emitter region fingers 114 of uniform widths across semiconductor wafer 104. Thus, the ion beam 106 can be manipulated to compensate for variations in process parameters and form emitter region fingers 114 having uniform widths and pitches across top surface 108 of semiconductor wafer 104. In an example, one mask can have uncompensated openings and can be utilized with one or more secondary masks that provide compensation of an ion beam flux to provide emitter region fingers that have uniform widths and pitches. In another example, the species mask 110 is uncompensated and one or more dimensions of or a uniformity of the ion beam flux is compensated so that emitter region fingers are formed on a semiconductor that have uniform widths and pitches. The ion beam flux can be compensated via, for example, a second species mask as discussed above, a collimator, or another structure that provides a mask function similar to that of the second species mask discussed above.
It is to be appreciated that fabrication of a species mask can be performed by forming, e.g., cutting or etching, slits in a uniform sample of material. However, in another aspect, a species mask is fabricated using a stack of material layers that can be cut or etched to provide a slit pattern therein. In one such embodiment, individual layers of silicon wafers are stacked and bonded to one another, and slits are formed therein.
Overall, although certain materials are described specifically above, some materials can be readily substituted with others. For example, in an embodiment, a different material substrate, such as a group III-V material substrate, can be used to form semiconductor wafer 104 instead of a silicon substrate. In another embodiment, a polycrystalline or multi-crystalline silicon substrate is used. Furthermore, an ordering of N+ and P+ type doping can occur in different sequences in different embodiments.
In general, embodiments described herein can be implemented to precisely form emitter region fingers 114 on semiconductor wafer 104. Thus, apparatuses for, and methods of, fabricating solar cell emitter regions using ion implantation, and the resulting solar cells, have been disclosed.
Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.
The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims can be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims can be combined with those of the independent claims and features from respective independent claims can be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2017/055071 | 10/4/2017 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62411474 | Oct 2016 | US |
