Patent Application
20250046748
The present application claims the priority of the German patent application DE 10 2021 131 940.4 of Dec. 3, 2021, the disclosure of which is hereby incorporated by reference in its entirety.
The invention relates to an electronic component, a method for manufacturing an electronic component, an electronic component manufactured according to a method according to the invention and the use of an electronic component.
Au—Sn-based chip connections are frequently used in optoelectronics. These soldering processes require high process temperatures of over 280° C. due to the melting point of the solder material used. In many cases, these temperatures are critical for the processed opto semiconductors (e.g. lasers, UV-C LEDs, etc.) or for the substrates used. The process temperature can be reduced by the described invention, which on the one hand enables the processing of such temperature-sensitive materials, and on the other hand reduces the mechanical stresses that arise during cooling due to the different thermal expansion coefficients (CTE mismatch) of the materials in the component.
WO 2018/228891 A1 describes a solder joint in which a tin-rich primary melt reacts with a gold reservoir in the layer stack after breaking through a titanium barrier, resulting in isothermal solidification. The melting temperature of the tin-rich primary melt is reduced by adding indium. As the corresponding metallization layer is located on the very outside of the layer stack, a mixed oxide is formed on the surface, which consists at least partially of indium oxide. A covering (e.g. with a thin gold layer) could lead to the formation of high-melting intermetallic phases, which could affect the wetting behavior.
The task of the present invention was therefore to overcome the disadvantages of the prior art and to provide a new electronic component, a new method for manufacturing an electronic component and a new electronic component manufactured by a method according to the invention.
The problem of the present invention is solved by an electronic component according to claim 1, a method of manufacturing an electronic component according to claim 6, an electronic component according to claim 16 and the use of an electronic component according to claim 17. Advantageous further developments and embodiments are the subject of the dependent patent claims.
The object of the present invention is an electronic component comprising:
In the context of the present invention, an electronic component is in particular an optoelectronic component. This can be understood to mean, for example, LED (light emitting diode) encapsulations, LED packages, LED modules, etc. An electronic component can also be a housing, in particular for sealing LEDs, wavelength converters or lasers. Preferably, the electronic component is an element for generating radiation or light.
According to the present invention, the electronic component comprises a substrate. The substrate may be a carrier, such as a lead frame, a plate (e.g. a printed circuit board), or a layer. Exemplary substrates can be lead frames made of copper, plates or printed circuit boards made of fiber-reinforced plastic or ceramic, or layers made of silicon or glass or sapphire.
Furthermore, the electronic component comprises an optoelectronic component. The optoelectronic component may be an LED or an arrangement of several LEDs, a chip, wavelength converters, such as phosphors in the form of crystals, quantum dots, powders, glasses, lasers, etc. A chip can be a layer sequence comprising a layer (e.g. InGaN) that is set up to emit electromagnetic radiation. Optoelectronic components are well known to those skilled in the art.
The electronic component comprises a first intermetallic layer. An intermetallic layer is a homogeneous phase of at least two metals. The composition and structure of the intermetallic phase can be defined in more detail in a phase diagram and described by a specific stoichiometric composition of the individual metals.
In the present case, the first intermetallic phase consists of tin (Sn) and nickel (Ni). “Consisting of” in connection with the first intermetallic phase means that the material content of foreign elements, i.e. elements, in particular metals, other than Sn and Ni, is in particular not higher than 20 at. %, preferably not higher than 10 at. %, more preferably not higher than 5 at. %, even more preferably not higher than 0.5 at. %. In other words, the first intermetallic phase is formed from a SnNi mixture.
In a preferred embodiment, the first intermetallic phase has no other elements, in particular no other metals (e.g. indium).
The first intermetallic layer preferably has a Nix Sn1-x phase, where 0.3<x<0.6.
The first intermetallic phase may account for an average proportion in relation to the first, second and third intermetallic phases of less than 20 at. %, preferably less than 15 at. %, more preferably less than 10 at. %.
The electronic component further comprises a second intermetallic layer comprising tin (Sn) and titanium (Ti).
“Comprising Sn and Ti” in connection with the second intermetallic layer can mean that the material content of foreign elements, i.e. elements, in particular metals, other than Sn and Ti, is up to 20 at. %, preferably up to 10 at. %, more preferably up to 5 at. %. In one embodiment, the second intermetallic layer consists of Sn and Ti and has no significant foreign elements.
In one embodiment, the second intermetallic phase may comprise the elements tin, titanium and nickel. In a further embodiment, the second intermetallic phase comprises the elements tin, titanium and platinum. In a further embodiment, the second intermetallic layer comprises the elements tin, titanium, nickel and platinum.
The second intermetallic phase preferably has a Snx Ti1-x phase, where 0.3>x>0.7. Alternatively, however, the second intermetallic phase can also have a Snx Tiy Au1-x-y phase, where 0<x<0.6 and 0<y<0.8 and x+y<1.
The second intermetallic phase can make up an average proportion in relation to the first, second and third intermetallic phase of less than 5 at. %, preferably less than 3 at. %, more preferably less than 1 at. %.
The electronic component further comprises a third intermetallic layer comprising tin (Sn) and gold (Au).
“Comprising Sn and Au” in connection with the third intermetallic layer can mean that the material content of foreign elements, i.e. elements, in particular metals, other than Sn and Au is up to 10 at. %, preferably up to 5 at. %, more preferably up to 1 at. %. In one embodiment, the third intermetallic layer consists of Sn and Au and has no significant foreign elements.
In one embodiment, the third intermetallic layer may comprise the elements tin, gold and nickel. In a further embodiment, the third intermetallic phase comprises the elements tin, gold and platinum. In a further embodiment, the third intermetallic layer comprises the elements tin, gold, nickel and platinum. In a further embodiment, the third intermetallic layer comprises the elements tin, gold and palladium.
The third intermetallic phase preferably has a Snx Au1-x phase, where 0.45>x>0.7.
In one embodiment, the third intermetallic phase has a delta phase, but can also have a zeta or zeta′ phase.
The third intermetallic phase can make up an average proportion in relation to the first, second and third intermetallic phase of 80 at. %, preferably 50 at. %, more preferably 30 at. %.
According to the present invention, the amount of tin and gold in the third intermetallic layer is approximately equal.
“Approximately equal to” in the context of the third intermetallic layer means that the amount of tin is between 45 at. % to 55 at. %, preferably between 47 at. % to 53 at. %, more preferably between 49 at. % to 51 at. %. In this context, the amount of gold may be between 45 at. % to 55 at. %, preferably between 47 at. % to 53 at. %, more preferably between 49 at. % to 51 at. %. Exemplary embodiments of third intermetallic layers have 45 at. % Sn and 55 at. % Au, 47 at. % Sn and 53 at. % Au, 49 at. % Sn and 51 at. % Au. In one embodiment, “approximately equal” means that the amount of tin is 50 at. % and the amount of gold is 50 at. %. The amounts of tin and gold preferably add up to 100 at. %. In embodiments in which further elements are present in the third intermetallic layer, these amounts of material are also added and the sum of the elements present in the third intermetallic layer is added up to 100 at. %.
The amount of substance, which is denoted by “n”, indirectly indicates the number of particles in a portion of substance. The amount of substance can be calculated from n=M/m, where “M” is the molar mass in g/mol and “m” is the weight in g.
In one embodiment, the proportion by weight of tin in the third intermetallic layer is in the range from 33% to 42% by weight, preferably in the range from 36% to 40% by weight, more preferably in the range from 38% to 39% by weight, based on the total weight of the third intermetallic layer.
In one embodiment, the weight percentage of gold in the third intermetallic layer is in the range between 67 wt. % to 58 wt. %, preferably in the range between 64 wt. % to 60 wt. %, more preferably in the range between 62 wt. % to 61 wt. %, based on the total weight of the third intermetallic layer.
Further intermetallic or metallic layers can be arranged between the first, second and/or third intermetallic layer. “Between” the layers means that the further layer(s) at least partially separate(s) the existing layers from each other. If, for example, a further (inter)metallic layer is arranged between the first and second intermetallic layer, this (inter)metallic layer at least partially separates the first intermetallic layer from the second intermetallic layer so that they have no contact points with each other in this area. The same applies to the second and third intermetallic layers.
A further metallic layer can be arranged between the first intermetallic layer and the second intermetallic layer. For example, the further metallic layer may be a nickel layer, a titanium layer, a platinum layer, etc.
A further intermetallic layer can also be arranged between the first intermetallic layer and the second intermetallic layer. The further intermetallic layer may be a layer comprising nickel and titanium, a layer comprising nickel and platinum, or a layer comprising titanium and platinum, etc.
A further intermetallic layer can also be arranged between the second intermetallic layer and the third intermetallic layer. The further intermetallic layer may be a layer comprising gold and titanium, a layer comprising gold and tin, a layer comprising titanium and tin, a layer comprising gold, palladium and tin, etc.
In a preferred embodiment, the first intermetallic layer is adjacent to the substrate, i.e. the first intermetallic layer is in physical or electrical contact with the substrate, and the third intermetallic layer is adjacent to the optoelectronic component, i.e. the third intermetallic layer is in physical or electrical contact with the optoelectronic component. In some embodiments, a further metallic or intermetallic layer may be at least partially disposed between the first intermetallic layer and the substrate, or the third intermetallic layer and the optoelectronic component, thus physically or electrically separating the substrate from the first intermetallic layer in this region, or the optoelectronic component from the third intermetallic layer. In such embodiments, the second intermetallic layer is arranged between the first intermetallic layer and the third intermetallic layer. Here too, one or more (inter)metallic layer(s) can be arranged between the first intermetallic layer and the second intermetallic layer and the second intermetallic layer and the third intermetallic layer.
In an alternative embodiment, the first intermetallic layer is adjacent to the optoelectronic component, i.e. the first intermetallic layer is in physical or electrical contact with the optoelectronic component, and the third intermetallic layer is adjacent to the substrate, i.e. the third intermetallic layer is in physical or electrical contact with the substrate. In some of these embodiments, a further metallic or intermetallic layer may be at least partially disposed between the first intermetallic layer and the optoelectronic component, or the third intermetallic layer and the substrate, thus physically or electrically separating the optoelectronic component from the first intermetallic layer in this region, or the substrate from the third intermetallic layer. In such embodiments, the second intermetallic layer is arranged between the first intermetallic layer and the third intermetallic layer. Again, one or more (inter)metallic layer(s) may be disposed between the first intermetallic layer and the second intermetallic layer and the second intermetallic layer and the third intermetallic layer.
According to the embodiments mentioned, the optoelectronic component is connected to the substrate via the first intermetallic layer, the second intermetallic layer and the third intermetallic layer.
In one embodiment, the electronic component further comprises a cover layer. The cover layer may be glass, sapphire, etc. The cover layer may have a thickness of 100 μm to 500 μm, preferably from 150 μm to 350 μm, more preferably from 250 μm to 300 μm.
In a further embodiment, the electronic component further comprises a frame. The frame may be a socket, in particular a lateral socket. However, a frame can also mean a housing comprising a base and a side socket. A frame can be made of copper, aluminum oxide or aluminum nitride, for example.
In particular, a frame is present in embodiments in which the electronic component is a (ceramic) LED package or a (ceramic) laser package. Particularly in the case of laser packages that have a base plate (e.g. a ceramic base plate) and a housing (e.g. a ceramic housing), a design such as that specified here by a first, second and third intermetallic layer is advantageous. The first, second and third intermetallic layers described here make it possible to achieve optimum encapsulation, in particular airtight encapsulation.
Another object of the present invention is a method of manufacturing an electronic component, in particular an electronic component according to the present invention. A method according to the invention comprises the steps of:
According to the method of the present invention, a substrate comprising a first metallic layer comprising gold (Au) is provided. The substrate may be a substrate as described herein.
The first metallic layer can be in direct physical and/or electrical contact with the substrate. However, at least one further layer, preferably a metallic layer, may also be present between the substrate and the first metallic layer. If a further metallic layer is present between the substrate and the first metallic layer, these are preferably connecting layers that facilitate the bonding of the first metallic layer to the substrate. For example, this may be platinum or nickel.
In addition to gold, the first metallic layer can also comprise other elements, in particular metals. For example, in addition to gold, platinum and/or tin may also be present in the first metallic layer, whereby the material content of gold is greater than the material content of the sum of the other elements, if these are present.
The first metallic layer can have a thickness of 0.5 μm to 4 μm, preferably from 1 μm to 3 μm, more preferably from 1.5 μm to 2 μm.
In one embodiment, the substrate also comprises a barrier layer in addition to the first metallic layer. The barrier layer is preferably arranged on the side of the first metallic layer facing away from the substrate.
The method according to the invention further comprises the step of providing an optoelectronic component. The optoelectronic component is an optoelectronic component as described herein.
The method according to the invention further comprises the step of providing a solder metal layer sequence. The solder metal layer sequence comprises a second metallic layer consisting of tin, a third metallic layer, optionally a first barrier layer and a second barrier layer. The second barrier layer is arranged between the second metallic layer and the third metallic layer.
The solder metal layer sequence can thus have a second metallic layer, a third metallic layer and a second barrier layer between the second and third metallic layers.
In an alternative embodiment, the solder metal layer sequence may comprise a second metallic layer, a third metallic layer, a second barrier layer between the second and third metallic layers, and a first barrier layer adjacent to the second metallic layer on the side facing away from the second barrier layer. The first barrier layer is preferably present when the substrate has no barrier layer.
According to the invention, the second metallic layer consists of tin (Sn). In other words, preferably no other elements, in particular metals, are present in the second metallic layer. The material content of further elements (e.g. gold or indium) can be at most 15 at. %, preferably at most 7 at. %, more preferably at most 1 at. %, relative to the total material quantity of the second metallic layer. The second metallic layer can have a thickness of 0.5 μm to 4 μm, preferably from 1 μm to 3 μm, more preferably from 1.5 μm to 2 μm.
The solder metal layer sequence also includes a third metallic layer. The third metallic layer is preferably an oxidation protection. An oxidation protection is a compound or element that prevents oxidation, i.e. reaction with oxygen, of the underlying layers.
Exemplary third metallic layers may comprise gold, silver and/or platinum. Preferably, the third metallic layer comprises or consists of gold.
The third metallic layer can have a thickness of 15 nm to 135 nm, preferably from 30 nm to 100 nm, more preferably from 50 nm to 70 nm.
A second barrier layer is arranged between the second metallic layer and the third metallic layer. Preferably, the second barrier layer is arranged in such a way that the second metallic layer is completely physically and/or electrically separated from the third metallic layer. This means that the second barrier layer is preferably a continuous layer. The barrier layer can also be regarded as a temporary diffusion barrier in order to at least temporarily prevent a reaction between the second metallic layer and the third metallic layer.
The second barrier layer can comprise nickel, titanium or platinum. The second barrier layer can be an alloy of the metals mentioned or a pure metal layer. If the second barrier layer comprises an alloy, the alloy can comprise nickel and platinum, nickel and titanium, platinum and titanium, nickel and platinum and titanium.
In one embodiment, the second barrier layer comprises titanium. Preferably, the second barrier layer is a titanium layer.
According to one embodiment, the second barrier layer can have a thickness in the range from 3 nm to 15 nm, preferably in the range from 5 nm to 10 nm. The second barrier layer can also have a thickness in the range from 6 nm to 8 nm. Exemplary thicknesses of the second barrier layer are 5 nm, 7 nm, 9 nm, 10 nm, 13 nm and 15 nm.
The solder metal layer sequence may have a first barrier layer. The first barrier layer may be in physical and/or electrical contact with the second metallic layer on the side facing away from the second barrier layer. In an alternative embodiment, the first barrier layer is in physical and/or electrical contact with the first metallic layer on the side facing away from the substrate. The first barrier layer, like the second barrier layer, can be considered as a temporary diffusion barrier to at least temporarily prevent a reaction between the first metallic layer and the second metallic layer.
The first barrier layer can comprise nickel, titanium or platinum. The first barrier layer can be an alloy of the metals mentioned or a pure metal layer. If the first barrier layer comprises an alloy, the alloy may comprise nickel and platinum, nickel and titanium, platinum and titanium, nickel and platinum and titanium.
In one embodiment, the first barrier layer comprises titanium. Preferably, the first barrier layer is a titanium layer.
According to one embodiment, the first barrier layer can have a thickness in the range from 10 nm to 50 nm, preferably in the range from 20 nm to 40 nm. The first barrier layer can also have a thickness in the range from 25 nm to 30 nm. Exemplary thicknesses of the first barrier layer are 20 nm, 25 nm, 30 nm, 35 nm, 38 nm and 40 nm.
In one embodiment, a method according to the invention comprises applying the solder metal layer sequence to the first metallic layer, wherein a first barrier layer is present and the first barrier layer is disposed between the first metallic layer and the second metallic layer. In other words, the layer sequence in this embodiment would be: substrate-first metallic layer-first barrier layer-second metallic layer-second barrier layer-third metallic layer. In this embodiment, the solder metal layer sequence that is applied may comprise the first barrier layer, the second metallic layer, the second barrier layer and the third metallic layer, and the first barrier layer may be present on the first metallic layer.
Preferably, the first and/or the second barrier layer comprise titanium or consist of titanium. In one embodiment, a method according to the invention may further comprise applying the optoelectronic component to the solder metal layer sequence, wherein the optoelectronic component is applied directly to the third metallic layer. The optoelectronic component may be an optoelectronic component mentioned herein. In this embodiment, the layer sequence would be: substrate-first metallic layer-first barrier layer-second metallic layer-second barrier layer-third metallic layer-optoelectronic component.
The optoelectronic component can be applied by placing the optoelectronic component on the respective layer. It is particularly advantageous that no adhesives or other additional bonding agents are used in this process.
In an alternative embodiment, a method according to the invention may further comprise applying the optoelectronic component to the solder metal layer sequence, wherein the optoelectronic component is applied directly to the second metallic layer, or to the optionally present first barrier layer. Again, the optoelectronic component may be an optoelectronic component described herein. In this embodiment, the layer sequence would be: optoelectronic component-optional first barrier layer-second metallic layer-second barrier layer-third metallic layer.
In this alternative embodiment, the optoelectronic component can also be applied by placing the optoelectronic component on the respective layer. It is particularly advantageous that no adhesives or other additional bonding agents are used in this process.
In a further step, the alternative embodiment may further comprise applying the solder metal layer sequence and the optoelectronic component to the first metallic layer, wherein the third metallic layer is disposed between the first metallic layer and the second barrier layer. In this alternative embodiment, the layer sequence would be: substrate-first metallic layer-third metallic layer-second barrier layer-second metallic layer-optional first barrier layer-optoelectronic component.
A method according to the invention may further comprise applying a cover layer to the optoelectronic component. The cover layer may be a cover layer mentioned herein. Particularly preferably, the cover layer is a layer of glass.
The cover layer is preferably designed in such a way that it transmits radiation or light generated by the electronic component to the side facing away from the substrate or directs it in a specific direction.
A method according to the invention may further comprise the step of heating. The arrangement comprising the substrate, the first metallic layer, the solder metal layer sequence and the optoelectronic component can be heated.
Heating can cause a change in the aggregation states of the individual layers, i.e. the first metallic layer, the second metallic layer, the third metallic layer, the optional first barrier layer and the second barrier layer. In particular, heating is carried out in such a way that there is no change in the aggregation state of the substrate, the optoelectronic component and other optional layers and components (e.g. the cover layer, the frame, etc.).
Heating can also be understood as soldering.
Preferably, heating is carried out by applying heat to the side of the substrate. Alternatively, the heat can also be applied to the side of the optoelectronic component, in particular via a cover layer, if present. Alternatively, the heat can also be applied to both sides in parallel or alternately. Heating is carried out in particular by heat-emitting objects, such as heat plates, or by irradiation with high-energy radiation (e.g. by lasers or flash discharge lamps).
By heating the arrangement, the barrier layer closest to the heat-emitting object first becomes permeable. This causes the metallic layers adjacent to the barrier layer to come into contact with each other, resulting in the formation of a eutectic. When the eutectic melting temperature is reached, a melt comprising the metals of the neighboring metallic layers is formed. If, for example, the metallic layers are a gold layer and a tin layer and the barrier layer is a titanium layer, heating causes the titanium layer to become permeable and the gold layer comes into contact with the tin layer, forming a gold-tin eutectic. When the eutectic temperature is reached (e.g. >217° C.), a gold-tin melt is formed, which preferably solidifies isothermally in the delta phase during the further course of the process.
Through further heating, the additional barrier layer, if present, can become permeable and the neighboring metallic layer can come into contact with the eutectic formed first, whereby the metal of the neighboring metallic layer diffuses into the eutectic and thus the eutectic solidifies with the formation of intermetallic phases. If, for example, the additional barrier layer is a titanium layer, the titanium layer becomes permeable as a result of further heating. If the adjacent metallic layer is a gold layer and the eutectic is a gold-tin melt as described above, the gold in the gold layer diffuses into the gold-tin melt, whereby the melt solidifies to form at least one gold-tin phase. In particular, the gold-tin phase is a delta phase. In addition, the tin in the gold-tin melt or the gold-tin phase formed can also diffuse into the gold layer, forming at least one gold-rich gold-tin phase.
If no further barrier layer is present, i.e. only the second barrier layer is present, the melt comes into contact with the neighboring metallic layer, whereby the metal of the neighboring metallic layer diffuses into the eutectic and the eutectic solidifies, forming intermetallic phases. If, for example, the adjacent metallic layer is a gold layer and the eutectic is a gold-tin melt as described above, the gold of the gold layer diffuses into the gold-tin melt, whereby the melt solidifies with the formation of at least one gold-tin phase. In particular, the gold-tin phase is a delta phase. In addition, the tin in the gold-tin melt or the gold-tin phase formed can also diffuse into the gold layer, forming at least one gold-rich gold-tin phase.
The barrier layers prevent the individual metallic layers from reacting prematurely, which means that heating can be used to control a targeted reaction between the individual layers.
Typical temperatures for heating are 150° C. to 250° C., preferably 200° C. to 240° C., more preferably between 220° C. and 230° C.
It is particularly preferable for the individual layers to have a certain thickness in relation to each other. A defined composition of the individual intermetallic layers can be achieved by specifically selecting the thicknesses.
To form an intermetallic phase between the first metallic phase and the second metallic phase, the layer thickness ratio between the first metallic phase and the second metallic phase is preferably: 1:1 to 2:1, more preferably 0.6:0.4. In this embodiment, the first barrier layer is preferably arranged between the first metallic phase and the second metallic phase and has a thickness in the range from 10 nm to 50 nm, for example, preferably in the range from 20 nm to 40 nm.
The phase formed from the first metallic phase and the second metallic phase is preferably the third intermetallic phase in the manufactured electronic component. An electronic component according to the present invention is thus an intermetallic layer comprising tin and gold, the amount of tin and gold being approximately equal. Preferably, the third intermetallic layer is in the delta phase.
To form an intermetallic phase between the second metallic phase and the third metallic phase, the layer thickness ratio between the second metallic phase and the third metallic phase is preferably: 1:1 to 2:1, more preferably 0.6:0.4. In this embodiment, the second barrier layer is arranged between the second metallic phase and the third metallic phase and has a thickness in the range from 3 nm to 15 nm, preferably in the range from 5 nm to 10 nm, for example.
The layer formed from the second metallic layer and the third metallic layer is preferably the first intermetallic layer in the manufactured electronic component. An electronic component according to the present invention is thus an intermetallic layer consisting of tin and nickel.
As part of the process, an intermetallic layer can also be formed between the second metallic layer and the optionally present first or second barrier layer. In this case, an intermetallic layer comprising tin and titanium can be formed. Thus, in an electronic component according to the present invention, a second intermetallic layer comprising tin and titanium may be present.
A further object of the present invention is an electronic component manufactured according to a method according to the invention.
Another object of the present invention is the use of an electronic component according to the invention in laser applications, automotive lighting, general lighting, display applications, projection, etc.
Further advantageous embodiments and further embodiments of the invention result from the embodiment examples described below in conjunction with the figures.
Elements that are identical, similar or have the same effect are marked with the same reference symbols in the figures. The figures and the proportions of the elements shown in the figures should not be considered to be to scale. Rather, individual elements, in particular layer thicknesses, may be shown in exaggerated size for better visualization and/or understanding.
Adjacent to the layer 411 is a third optional layer 415 (with a thickness of e.g. 100 nm), as well as an optional layer 413. The layer 413 may be a terminal metallization (e.g. CuNiAu). The layer 415 can be an intermediate Au layer. At some distance,
The invention is not limited to the description based on the embodiments. Rather, the invention includes any new feature as well as any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2021 131 940.4 | Dec 2021 | DE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/084154 | 12/2/2022 | WO |
