Patent Application
20160307772
1. Field
Embodiments of the present disclosure generally relate to methods of patterning and etching a substrate. More specifically, embodiments described herein relate to material modification and etching processes to manufacture spacer features with a flat top profile.
2. Description of the Related Art
In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures, such as fin field effect transistors (FinFETs) have been developed. Forming sub-10 nm node structures is desired but complicated by limitations and complexities associated with various patterning and lithography processes.
For example, multiple patterning processes, such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) processes, may not adequately provide reliable patterning given the small pitch size requirements associated with formation of sub-10 nm node structures. Other lithography processes, such as litho-etch-litho-etch (LELE) processes which utilize 193 nm immersion photolithography, may increase the line width roughness (LWR) of a resist used to pattern features on the substrate.
Conventional double and quadruple double patterning schemes generally involve etching of a spacer material and removal of a mandrel material to leave a mask pattern created by individual spacers. However, conventional spacer etching processes often result in asymmetric spacer profiles. For example, rounding of a spacer shoulder region adjacent a mandrel structure may result in an undesirable pattern transfer during subsequent spacer deposition and etching processes. Inconsistencies and asymmetries in spacer etching may affect pattern transfer which can result in adjacent features having inconsistent critical dimensions, depths, shapes, etc. Moreover, current lithography and patterning processes are time consuming, which reduces throughput for device processing.
Accordingly, improved spacer etching methods are needed.
In one embodiment, a method of patterning a substrate is provided. The method includes biasing a substrate having one or more mandrel structures and a spacer material formed thereon in a processing chamber. The spacer material may be exposed to an inert plasma to implant ions in one or more regions of the spacer material at a first pressure. The implanted regions of the spacer material may be exposed to an etchant plasma to remove a portion of the spacer material in the processing chamber at a second pressure. The second pressure may be at least about three orders of magnitude greater than the first pressure. The exposing the spacer material to an inert plasma and the exposing the implanted regions of the spacer material to an etchant plasma may be repeated until a predominantly flat spacer profile is formed.
In another embodiment, a method of patterning a substrate is provided. The method includes biasing a substrate having one or more silicon mandrel structures and a silicon nitride spacer material formed thereon in a processing chamber. The silicon nitride spacer material may be exposed to a hydrogen plasma to implant hydrogen ions in one or more regions of the silicon nitride spacer material. The implanted regions of the silicon nitride spacer material may be exposed to a fluorine etchant plasma to remove a portion of the silicon nitride spacer material in the processing chamber at a pressure of between about 2 Torr and about 4 Torr.
In yet another embodiment, a method of patterning a substrate is provided. The method includes biasing a substrate having one or more silicon mandrel structures and a silicon oxide spacer material formed thereon in a processing chamber. The silicon oxide spacer material may be exposed to a helium plasma to implant helium ions in one or more regions of the silicon oxide spacer material. The implanted regions of the silicon oxide spacer material may be exposed to a fluorine etchant plasma to remove a portion of the silicon oxide spacer material in the processing chamber at a pressure of between about 2 Torr and about 4 Torr.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.
A substrate having mandrel structures and a spacer material layer disposed thereon may be processed according to the embodiments described herein. The inert plasma treatment process may utilize a capacitively-coupled plasma and a suitable chemistry to implant ions into regions of the spacer material layer without removing portions of the spacer material. The inert plasma treatment process may be biased to control implantation of ions into desired regions of the spacer material layer. An unbiased etching process may utilize a capacitively-coupled plasma with a suitable process gas to etch the implanted regions of the spacer material in a cyclic manner by repeating the plasma ion implantation and plasma etching processes until a predominantly flat top spacer profile is achieved. In one embodiment, a pressure maintained in a processing chamber during the unbiased etching process may be at least about three orders of magnitude greater than the pressure maintained in the processing chamber during the inert plasma treatment process.
The substrate processing chambers 108 may include one or more system components for modifying and/or etching a material deposited on a substrate. In one configuration, two pairs of the processing chambers, for example, 108c-108d and 108e-108f, may be used to modify a material on the substrate, and the third pair of processing chambers, for example, 108a-108b, may be used to remove material from the substrate. In another configuration, all of the processing chambers 108a-108f may be configured to modify a material on the substrate and remove material from the substrate. In this configuration, each pair of processing chambers, 108a-108b, 108c-108d, 108e-108f, may be configured to perform a plasma modification and/or ion implantation process and a selective etching process.
In one embodiment, processing chambers configured to perform a selective etching process may utilize a dry plasma etching process to remove a previously modified material. Processing chambers configured to modify material or implant ions into a material, such as a spacer material, may utilize an inert plasma modification process. In one embodiment, the processing chambers configured to modify material or implant ions may utilize an electron beam to form a plasma. However, other methods of forming a plasma may also be utilized. The processing system 101 described herein may be utilized to perform the processes described herein. Additionally, any one or more of the processes described herein may be performed in a chamber(s) separated from the processing system 101.
The above-described processing system 101 can be controlled by a processor based system controller such a controller 190. For example, the controller 190 may be configured to control flow of various process gases and purge gases from gas sources, during different operations of a substrate process sequence. The controller 190 includes a programmable central processing unit (CPU) 192 that is operable with a memory 194 and a mass storage device, an input control unit, and a display unit (not shown), such as power supplies, clocks, cache, input/output (I/O) circuits, and the like, coupled to the various components of the processing system 101 to facilitate control of the substrate processing. The controller 190 also includes hardware for monitoring substrate processing through sensors in the processing system 101, including sensors monitoring the process gas and purge gas flow. Other sensors that measure system parameters such as substrate temperature, chamber atmosphere pressure and the like, may also provide information to the controller 190.
To facilitate control of the processing system 101 described above, the CPU 192 may be one of any form of general purpose computer processor that can be used in an industrial setting, such as a programmable logic controller (PLC), for controlling various chambers and sub-processors. The memory 194 is coupled to the CPU 192 and the memory 194 is non-transitory and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. Support circuits 196 are coupled to the CPU 192 for supporting the processor in a conventional manner. Material modification/ion implantation, etching, and other processes are generally stored in the memory 194, typically as a software routine. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 192.
The memory 194 is in the form of computer-readable storage media that contains instructions, that when executed by the CPU 192, facilitates the operation of the processing system 101. The instructions in the memory 194 are in the form of a program product such as a program that implements the method of the present disclosure. The program code may conform to any one of a number of different programming languages. In one example, the disclosure may be implemented as a program product stored on computer-readable storage media for use with a computer system. The program(s) of the program product define functions of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.
The spacer material 206 may be formed from suitable spacer or hardmask materials, such as silicon containing materials, nitride containing materials, and the like. In certain embodiments, the spacer material 206 may be a silicon nitride material, a silicon oxide material, a polysilicon material, or a titanium nitride material. It is contemplated that the materials selected for the mandrel structures 204 and the spacer material 206 may be suitable for use in the fabrication of FinFET structures. It is also contemplated that the materials selected for the mandrel structures 204 and the spacer material 206 may have different characteristics to facilitate selective etching processes.
Generally, the mandrel structures 204 may extend from the substrate 202 and the spacer material 206 may be formed in a layer over the mandrel structures 204 and the substrate 202. The spacer material 206 may be deposited by various techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes. In one embodiment, the spacer material 206 may be predominantly conformally deposited over the mandrel structures 204 and the substrate 202. The spacer material 206, after deposition, may exhibit a rounded profile in a shoulder region 210 of the spacer material 206. The mandrel structures 204 may be spaced apart such that when the spacer material 206 is deposited, a trench 208 may be formed between adjacent mandrel structures. In the embodiments provided below, processing parameters are generally described with regard to the processing of a 300 mm substrate, however, it is contemplated the other size substrates, such as 200 mm or 450 mm substrates, may benefit from the embodiments described herein.
The inert plasma may be generated by a remote plasma source or may be generated in situ in the processing chamber. The inert plasma generation process may be an inductively coupled plasma process or a capacitively-coupled plasma process. Generally, a bias may be utilized during the inert plasma modification process to influence directionality of the plasma with regard to the spacer material 206. For example, the substrate 202 may be biased to direct ions toward the substrate 202. In one embodiment, ions may be directed toward a plane 310 parallel to the substrate at an angle between about normal to the plane 310 and about 45° to the plane 310. It is contemplated that the depth of penetration of the ions into the spacer material 206 at the top region 306 and the bottom region 308 may be determined, at least in part, by the angle at which the ions strike the spacer material 206. For example, the depth of penetration of the ions in the shoulder region 210 may be less than at other portions of the top region 306. Ions may strike the shoulder region 210 at a different angle resulting in a lesser penetration depth when compared to a portion of the spacer material 206 directly above the mandrel structure 204. However, it is believed that the depth of penetration of the ions in the top region 306 may be predominantly the same across the top region 306 of the spacer material 206.
Suitable process gases for forming the inert plasma 302 include H2, N2, O2, and noble gases, such as He or Ar, among others. Suitable ion species generated from the inert plasma 302 include H ions, He ions, Ar ions, N ions, O ions, and the like. Various processing parameters may also be controlled during the inert plasma modification process. For example, a bias power utilized to impart directionality to the plasma may be between about 10 W and about 1500 W, such as between about 50 W and about 200 W, for example, about 100 W. A pressure in the processing chamber during the inert plasma modification process may be maintained between about 5 mT and about 300 mT, such as between about 10 mT and about 200 mT, for example, about 20 mT.
In one embodiment, silicon nitride may be utilized as the spacer material 206 and H ions may be utilized to modify the spacer material 206. In this embodiment, it is contemplated that the H ions may be incorporated into the silicon nitride material without sputtering the silicon nitride spacer material. It is believed that sputtering may be reduced or eliminated due to the relatively small size of the H ions and the ability of the H ions to be incorporated into the silicon nitride material matrix without substantial disruption. In one example, H ions were generated from an H2 processing gas provided at a flow rate of about 100 sccm in a processing chamber environment having a pressure of about 20 mT. A bias voltage utilized to direct the H ions toward the silicon nitride spacer was maintained between about 200 V and about 600 V. Under the aforementioned processing conditions, it was found that approximately 0 Å of silicon nitride spacer were sputtered during the plasma modification process. The depth of H ion implantation into the silicon nitride spacer was between about 30 Å and about 110 Å, indicating that the depth of H ion implantation may be selectively controlled by the amount of bias power utilized.
In another embodiment, silicon oxide may be utilized as the spacer material 206 and He ions may be utilized to modify the spacer material 206. In this embodiment, it is contemplated that the He ions may be incorporated into the silicon oxide material without sputtering the silicon oxide spacer material. It is believed that sputtering may be reduced or eliminated due to the relatively small size of the He ions and the ability of the He ions to be incorporated into the silicon oxide material matrix without substantial disruption. In one example, He ions were generated from an He processing gas provided at a flow rate of about 100 sccm in a processing chamber environment having a pressure of about 20 mT. A bias voltage utilized to direct the He ions toward the silicon oxide spacer was maintained between about 200 V and about 600 V. Under the aforementioned processing conditions, it was found that approximately 0 Å of silicon oxide spacer were sputtered during the plasma modification process. The depth of He ion implantation into the silicon oxide spacer was between about 20 Å and about 120 Å, indicating that the depth of He ion implantation may be selectively controlled by the amount of bias power utilized.
In the embodiments described above, utilizing a relatively light ion, such as H ions and He ions, provides for modification of the spacer material 206 without undesirable damage to the spacer material 206. The lighter ions may also provide for a greater depth of penetration into the spacer material 206 when compared to heaver ions having a larger size. As such, the spacer material 206 may be modified to enable subsequent selective etching processes.
In one embodiment, the etchant plasma may be generated by a remote plasma source. The etchant plasma may be unbiased and the etching characteristics may be predominantly isotropic. However, the process gas chemistry utilized to form the etchant plasma may be configured to selectively remove the modified regions 304 relative to other regions of the spacer material 206, such as the sidewalls 402. Various process gases suitable for forming the etchant plasma include NF3, NH3, N2, H2, H2O2, O2, Cl2, F2, and combinations and mixtures thereof. The process gases formed into the etchant plasma may be provided to the processing chamber in the presence of a carrier gas, such as He or Ar.
A power suitable for etchant plasma generation by a remote plasma source may be between about 10 W and about 2000 W, such as between about 20 W and about 100 W, for example, about 40 W. A pressure in the processing chamber during the etchant plasma process may be maintained between about 500 mT and about 10 T, such as between about 1 T and about 5 T, for example, between about 2 T and about 4 T. In one embodiment, a silicon nitride spacer material modified with a H inert plasma may be etched by a combination of NF3 and NH3 process gases carried by He gas. In this embodiment, a ratio of NF3:NH3:He may be between about 1:10:33.3. A flow rate of the NF3 process gas may be between about 1 sccm and about 100 sccm, such as between about 25 sccm and about 50 sccm, for example, about 30 sccm. A flow rate of the NH3 process gas may be between about 100 sccm and about 1000 sccm, such as between about 200 sccm and about 400 sccm, for example, about 300 sccm. A flow rate of the He carrier gas may be between about 100 sccm and about 5000 sccm, such as between about 500 sccm and about 2000 sccm, for example, about 1000 sccm. It is contemplated that a silicon oxide spacer material modified with a He inert plasma may be etched under similar conditions as those described above.
Under the aforementioned processing conditions, a fluorine etchant plasma may be generated and the modified regions 304 of the spacer material 206 may be selectively removed. During the selective etching process, the substrate 202 or the processing environment may be heated to a temperature of between about 100° C. to about 500° C. to sublimate the reactant product of the fluorine etchant and the modified regions 304 of the spacer material 206. The reactant product may then be exhausted from the processing chamber.
The pressure utilized during the etching process may be about three orders of magnitude greater than the pressure utilized during the plasma modification process. It is believed that the increased pressure may result in the formation of ammonium salts. The ammonium salts are relatively large molecules which may be too large to exist in the trenches 208. Thus, a loading effect may be realized near the top region 306. As a result, the ammonium salts may reduce exposure of the bottom region 308 to fluorine radicals. Accordingly, the bottom region 308 may be etched more slowly than the top region 306. It is contemplated that the pressures utilized during the etching process, in combination with the implantation depth of ions during the inert plasma modification process may also contribute to the formation of a predominantly flat profile of the spacer material at the top region 306. As a result, the shoulder region 210 may be removed and top flat profile may be obtained as illustrated in
It is contemplated that less than an entire desirable amount of spacer material 206 may be removed after performing the inert plasma modification process and the etchant plasma material removal process. Accordingly, the inert plasma modification process and the etchant plasma material removal processes may be repeated in a cyclic manner until the mandrel structure in exposed or until a flat top profile of the spacer material 206 is formed. It is contemplated that the process may be cycled one or more times, for example, between about 2 times and about 5 times. After the cyclic material modification and etching process form a flat top spacer profile, the substrate 202 may by processed by various other substrate processing operations.
At operation 630, the implanted regions of the spacer material may be exposed to an etchant plasma at a second pressure. Generally, the second pressure may be about three orders of magnitude greater than the first pressure. At operation 640, operations 620 and 630 may be repeated until a predominantly flat top spacer material profile is achieved. By separating the modification and etching processes and controlling various processing conditions, directionality of the etching process may be improved and may result in an improved spacer material profile. For example, a predominantly flat spacer material profile may be achieved. The flat profile may improve pattern transfer during subsequent processing operations by more precisely defining the critical dimensions of the device features being formed.
Moreover, a polymer protective layer to protect sidewalls of the spacer material is not needed as a result of the improved spacer material etching control when utilizing the cyclic spacer material removal processes described herein. Thus, multiple patterning processes may benefit from the embodiments described herein and sub-10 nm node structures may be patterned more effectively and precisely.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
This application claims benefit to U.S. Provisional Patent Application No. 62/148,097, filed Apr. 15, 2015, the entirety of which is herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62148097 | Apr 2015 | US |
