Patent Application
20120297116
The present invention relates generally to memory devices, and particularly to methods and systems for data storage in analog memory cells.
Some memory devices, such as Flash devices, comprise arrays of analog memory cells. In some cases, neighboring memory cells in the array may cause cross-coupling interference to one another. Various techniques for reducing interference in memory devices are known in the art. Example techniques are described in U.S. Patent Application Publications 2008/0198650, 2009/0024905, 2009/0158126, 2010/0131826, whose disclosures are incorporated herein by reference.
Some memory systems employ means for protecting critical information. For example, U.S. Patent Application Publication 2009/0193184, whose disclosure is incorporated herein by reference, describes a hybrid Solid-State Disk (SSD) having Multi-Level-Cell (MLC) or Single-Level-Cell (SLC) Flash memory, or both. SLC Flash may be emulated by MLC that uses fewer cell states. Data reliability is improved since fewer MLC states are used, and noise margins may be relaxed.
An embodiment of the present invention that is described herein provides a method for data storage in a memory that includes an array of analog memory cells. A group of the memory cells is selected such that each memory cell in the group has one or more neighbor memory cells in the array that are excluded from the group. Data is stored in the group of the memory cells while excluding the neighbor memory cells from programming as long as the data is stored in the group of the memory cells.
In some embodiments, selecting the group includes excluding from the group all the immediate neighbor memory cells of each memory cell in the group. Selecting the group may include, for at least a part of the array, excluding from the group all the memory cells belonging to odd-order word lines or all the memory cells belonging to even-order word lines. In another embodiment, selecting the group includes, for at least a part of the array, excluding from the group all the memory cells belonging to odd-order bit lines or all the memory cells belonging to even-order bit lines.
In a disclosed embodiment, selecting the group includes, for each memory cell in the group, excluding from the group any neighbor memory cells that is adjacent to the memory cell and belongs to a same word line or bit line as the memory cell. In yet another embodiment, the memory cells in the array are assigned to hold n bits per cell, and storing the data includes programming the memory cells in the group with only k bits per cell, k<n.
In some embodiments, storing the data includes writing the data using programming commands that store a given data page in all the memory cells of a respective word line. In alternative embodiments, storing the data includes writing the data using programming commands that store a given data page either in odd-order or even-order memory cells of a respective word line.
In some embodiments, storing the data includes storing sensitive information in the group of the memory cells. In an embodiment, the sensitive information includes management information and/or power-down information. In a disclosed embodiment, storing the data includes applying to the data an additional protection mechanism that is not applied to other data stored outside the group. Applying the additional protection mechanism may include storing the data at a lower storage density relative to the other data; encoding the data with a stronger Error Correction Code (ECC) relative to the other data; and/or programming the memory cells in the group using a sequence of programming pulses that increase by an increment that is smaller relative to increments used outside the group.
There is additionally provided, in accordance with an embodiment of the present invention, a data storage apparatus including an interface and storage circuitry. The interface is configured to communicate with a memory including an array of analog memory cells. The storage circuitry is configured to select a group of the memory cells such that each memory cell in the group has one or more neighbor memory cells in the array that are excluded from the group, and to store data in the group of the memory cells while excluding the neighbor memory cells from programming as long as the data is stored in the group of the memory cells.
There is also provided, in accordance with an embodiment of the present invention, a data storage apparatus including a memory and storage circuitry. The memory includes an array of analog memory cells. The storage circuitry is configured to select a group of the memory cells such that each memory cell in the group has one or more neighbor memory cells in the array that are excluded from the group, and to store data in the group of the memory cells while excluding the neighbor memory cells from programming as long as the data is stored in the group of the memory cells.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:
Data is typically stored in analog memory cells by programming the memory cells to certain analog values, such as electrical charge levels or voltages. The data is retrieved from the memory cells by sensing the analog values. In some cases, memory cells may inflict cross-coupling interference on one another. This interference may distort the analog values read from the memory cells and cause read errors.
Embodiments of the present invention that are described herein provide improved methods and systems for storing data in analog memory cells. The disclosed techniques store data by programming a group of memory cells sparsely, such that each memory cell has one or more neighbor cells that remain un-programmed with data. This sort of programming helps to reduce cross-coupling interference, since the level of interference in a memory cell typically grows with the magnitudes of the analog values of its neighbors.
Several examples of sparse storage schemes are described hereinbelow. The disclosed schemes are simple to implement and do not incur considerable computational load, for example in comparison with schemes that cancel cross-coupling interference at readout time. The sparse storage schemes described herein differ from one another in the number of un-programmed neighbors per memory cell, and thus provide different trade-offs between data reliability and storage density.
The methods and systems described herein can be used both in memory devices that store different pages in different subsets of the memory cells in a word line (e.g., different pages in odd-order and even-order cells) and in All Bit Line (ABL) memory devices that store a page in all memory cells of a word line. The disclosed techniques are particularly suitable for storing sensitive information, such as management information, whose corruption would affect large amounts of stored data.
System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory array comprises multiple memory blocks 34. Each memory block 34 comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 28 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and Charge Trap Flash (CTF) Flash cells, phase change RAM (PRAM, also referred to as Phase Change Memory-PCM), Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), magnetic RAM (MRAM) and/or Dynamic RAM (DRAM) cells.
The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values, analog storage values or storage values. The storage values may comprise, for example, threshold voltages or any other suitable kind of storage values. System 20 stores data in the analog memory cells by programming the cells to assume respective programming states, which are also referred to as programming levels. The programming states are selected from a finite set of possible states, and each programming state corresponds to a certain nominal storage value. For example, a 3 bit/cell MLC can be programmed to assume one of eight possible programming states by writing one of eight possible nominal storage values into the cell.
Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to analog storage values and writes them into memory cells 32. In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. When reading data out of array 28, R/W unit 36 converts the storage values of memory cells into digital samples having a resolution of one or more bits. Data is typically written to and read from the memory cells in groups that are referred to as pages. In some embodiments, the R/W unit can erase a group of cells 32 by applying one or more negative erasure pulses to the cells. Erasure is typically performed in entire memory blocks.
The storage and retrieval of data in and out of memory device 24 is performed by a memory controller 40. The memory controller comprises an interface 44 for communicating with memory device 24, and a processor 48 that carries out the various memory management functions. In particular, processor 48 carries stores at least some of the data using sparse, high-reliability storage schemes that are described in detail below.
Memory controller 40 communicates with a host 52, for accepting data for storage in the memory device and for outputting data retrieved from the memory device. Memory controller 40, and in particular processor 48, may be implemented in hardware. Alternatively, the memory controller may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.
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In some embodiments, memory controller 40 comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.
In an example configuration of array 28, memory cells 32 are arranged in multiple rows and columns, and each memory cell comprises a floating-gate transistor. The gates of the transistors in each row are connected by word lines, and the sources of the transistors in each column are connected by bit lines. The memory array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes sub-divided into sectors. In some embodiments, each page comprises an entire row of the array. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells.
Typically, memory controller 40 programs data in page units, but erases entire memory blocks 34. Typically although not necessarily, a memory block is on the order of 106 memory cells, whereas a page is on the order of 103-104 memory cells.
A given memory cell 32 in memory array 28 may be subject to cross-coupling interference from neighboring memory cells in the array. In the present context, the term “neighboring memory cell” is used broadly and refers to any memory cell that potentially inflicts cross-coupling interference on the memory cell in question. Neighboring memory cells may be immediately adjacent to the interfered memory cell (e.g., vertical neighbors on the same bit line, horizontal neighbors on the same word line or diagonal neighbors), or non-adjacent memory cells that nevertheless potentially cause interference.
Typically, the level of interference caused by a certain neighboring cell grows with the magnitude of the interfering cell's analog value. Therefore, a neighboring cell that is programmed with data (and particularly a neighboring cell programmed with data that corresponds to a high analog value) will typically cause stronger interference than an un-programmed memory cell. Un-programmed memory cells usually cause little or no interference, because they are set to an erased state represented by a relatively small negative analog value.
In some embodiments that are described herein, processor 48 stores certain data using a storage scheme that retains, for each programmed memory cell, one or more neighboring memory cells un-programmed with data. In other words, processor 48 stores the data such that each memory cell being programmed with data has one or more neighbor cells that remain un-programmed as long as the data is stored is held in the programmed cells. Such storage schemes are referred to herein as sparse storage schemes. In the description that follows, the sparse storage scheme is defined and applied by processor 48 in the memory controller. In alternative embodiments, however, the storage scheme may be applied by R/W unit 36 in the memory device. Thus, processor 48 and/or unit 36 are referred to herein collectively as storage circuitry that carries out the disclosed storage techniques.
In some embodiments, processor 48 applies the sparse storage scheme to a selected group of memory cells, e.g., a set of word lines or a memory block. Within this group of memory cells, processor 48 selects a partial subset of memory cells for programming, such that each memory cell in the subset has at least one neighboring cell that is excluded from the subset. Processor 48 stores data in the group by programming the memory cells in the partial subset while retaining the excluded memory cells un-programmed with data. As a result of the sparse programming, each programmed memory cell suffers relatively low cross-coupling interference, and the readout error probability is therefore reduced.
In various embodiments, processor 48 may use various kinds of sparse programming schemes. In the examples given below, memory cells 32 comprise four-level memory cells, each storing two bits of data. In each memory cell, one bit is referred to as Least Significant Bit (LSB) and one bit is referred to as Most Significant Bit (MSB). The memory cells along each word line are divided into even-order and odd-order cells (i.e., the memory cells belonging to the even- and odd-order bit lines, respectively). The memory controller stores two memory pages (referred to as LSB and MSB pages) in the even-order cells, and two additional pages memory pages (LSB and MSB) in the odd-order cells. This configuration, however, is chosen purely by way of example. In alternative embodiments, any other suitable memory configuration can be used.
In one embodiment, processor 48 applies a sparse storage scheme that is defined in the following table:
In this scheme, a page is first written to the LSB page of the even-order bit lines on word line 0, then to the MSB page of the even-order bit lines on word line 0, then to the LSB page of the even-order bit lines on word line 2, then to the MSB page of the even-order bit lines on word line 2, and so on. Odd-order word lines and odd-order bit lines are not programmed at all.
As can be seen in the table, the programmed memory cells (on the intersections of the even-order word lines and even-order bit lines) have no immediate neighbors (i.e., cells that are directly adjacent to the memory cell, either diagonally, vertically or horizontally) that are programmed with data. Therefore, the memory cells experience little or no cross-coupling interference. On the other hand, this scheme stores data at only 25% of the capacity of the memory—since only a quarter of the memory cells are actually programmed.
In another embodiment, processor 48 applies a sparse storage scheme that is defined in the following table:
In this scheme, data is programmed only to the LSB pages of the even-order bit lines on the even-order word lines. As in the previous scheme, the programmed memory cells in the present scheme have no adjacent neighbors that are programmed with data. Therefore, the memory cells experience little or no cross-coupling interference. Moreover, the present scheme stores data at a reduced density of 1 bit/cell instead of 2 bits/cell (by storing only the LSB page and not the MSB page), and therefore is more resilient to read errors. The high resilience comes at the expense of reduced capacity—The present scheme utilizes 12.5% of the memory capacity.
In yet another embodiment, processor 48 applies a sparse storage scheme that is defined in the following table:
In this scheme too, only the even-order word lines are programmed. Memory pages are written alternately to the even-order and odd-order bit lines until the word line is fully programmed, and then programming advances to the next word line. In the present example, word line 0 is first programmed with four pages: A page is written to the LSB page of the even-order bit lines, a second page is written to the LSB page of the odd-order bit lines, then a page is written to the MSB page of the even-order bit lines, and a fourth page is written to the MSB page of the odd-order bit lines. The process is repeated on word line 2 (skipping word line 1), and so on.
In this sparse storage scheme, memory cells may suffer from some horizontal cross-coupling interference, since the horizontal neighbors of each programmed memory cell are also programmed. Vertical and diagonal interference, however, are eliminated. This scheme uses 50% of the memory capacity.
In another alternative embodiment, processor 48 applies a sparse storage scheme that is defined in the following table:
In this scheme, processor 48 programs the even-order bit lines on the even-order word lines, and the odd-order bit lines on the odd-order word lines. Both LSB and MSB pages are programmed. In this sparse storage scheme, the vertical and horizontal neighboring cells are not programmed, but the diagonal neighbors are programmed. This scheme uses 50% of the memory capacity. (In an alternative but equivalent embodiment, processor 48 may program the even-order bit lines on the odd-order word lines, and the odd-order bit lines on the even-order word lines.)
In still another embodiment, processor 48 applies a sparse storage scheme that is defined in the following table:
This scheme is similar to the previous example, with the addition that only the LSB pages are programmed. This sparse storage scheme has improved resilience to interference, at the expense of using only 25% of the memory capacity. As in the previous scheme, in an alternative embodiment processor 48 may program the even-order bit lines on the odd-order word lines, and the odd-order bit lines on the even-order word lines.
The example sparse programming schemes described above are chosen purely for the sake of conceptual clarity. In alternative embodiments, any other suitable programming scheme, which retains at least one un-programmed neighboring cell for each programmed memory cell, can be used. For example, the above-described schemes are applied in a memory that supports separate page write commands for programming the even- and odd-order memory cells in a given word line.
In some embodiments, the disclosed techniques are used in memory devices that program all the memory cells of a given word line in the same command (sometimes referred to as All Bit Lines—ABL—devices), e.g., by programming every second memory cell. This technique helps to reduce horizontal cross-coupling interference, i.e., interference from horizontal neighbors on the same word line as the interfered cell.
In some embodiments, processor 48 uses the sparse programming schemes described herein for increasing the storage reliability of sensitive information, as opposed to non-sensitive information. In these embodiments, the use of sparse programming is restricted to sensitive information because these techniques usually come at the expense of memory capacity. As such, the disclosed techniques may be used in specific areas of array 28, for example in specific sets of word lines in each block 34. In other areas of the memory, processor 48 may store the non-sensitive data while utilizing all the memory cells. Nevertheless, in alternative embodiments the disclosed techniques can be used for storing some or even all non-sensitive data, if desired.
The disclosed techniques enable processor 48 to store data with high reliability but with little or no Error Correction Code (ECC) redundancy. For example, the disclosed techniques, using an ECC rate on the order of 97%, can achieve the effective strength of an ECC having 25% rate and conventional programming schemes. This sort of configuration has performance benefits both during programming (less data is programmed, less resources and latency spent on ECC encoding) and during readout (less data is read, less resources and latency spent on ECC decoding).
Sensitive information may comprise any information whose loss or corruption would affect large amounts of stored data, or whose loss or corruption would cause additional damage or performance degradation beyond the loss of that specific information. Specific examples of sensitive information may comprise management data such as boot code (particularly if the boot time is restricted, so as to limit the boot code read time) or power-down data for which reliability should typically be high and program time is of importance. Non-sensitive information may comprise, for example, user data that is received from the host. Alternatively, processor 48 may use sparse programming for storing any other suitable type of information.
In some embodiments, processor 48 combines a sparse programming scheme with one or more additional protection mechanisms that increase storage reliability. Typically, the additional protection mechanism is not used other than for sparse storage. For example, processor 48 may store the data sparsely, and also using less than the number of bits per cell designated to memory cells 32. Consider, for example, a system in which processor 48 stores user data in memory cells 32 using n bits/cell, e.g., using 2n programming levels. In some embodiments, processor 48 may store sensitive information using sparse programming and also using only k bits/cell (2k programming levels), k<n.
As another example, consider a system in which processor 48 encodes the user data with an ECC having a certain redundancy level (e.g., a certain code rate). In some embodiments, processor 48 may store sensitive information using sparse programming and also encode the sensitive information with an ECC having a higher redundancy level (e.g., lower code rate).
As yet another example, consider a system in which R/W unit 36 programs memory cells 32 in an iterative Programming and Verification (P&V) process. In such a process, the R/W unit applies to a group of memory cells a sequence of programming pulses that progressively increase in magnitude and/or duration. The analog values of the memory cells are verified during the programming sequence, and subsequent pulses are applied only to memory cells that have not yet reached their intended analog values.
In some embodiments, processor 48 may store user data by programming the memory cells using a pulse sequence that increases from pulse to pulse by a certain magnitude and/or duration increment, and store sensitive information by programming the memory cells using a pulse sequence that increases from pulse to pulse by a smaller increment. The smaller increment typically increases the storage accuracy, at the expense of programming speed.
In some embodiments, processor 48 may apply any suitable combination of the above-described protection mechanisms, or any other suitable protection mechanism for increasing storage reliability along with sparse programming.
Processor 48 selects a sparse subset of memory cells for storing the sensitive information, at a selection step 64. In an embodiment, processor 48 assigns a certain group of memory cells, e.g., a set of word lines, for storing the sensitive information. Within this group, processor 48 selects a partial subset of the memory cells that will actually be programmed. The other memory cells in the group will be excluded from programming as long as the sensitive information is stored in the partial subset.
The partial subset is selected such that each cell in the subset (which will be programmed) has at least one neighbor cell in the group that will be excluded from programming. Processor 48 may select the partial subset according to any suitable sparse programming scheme, such as the example schemes described above. Processor 48 stores the sensitive information in the selected subset of the memory cells, at a sparse programming step 68.
Although the embodiments described herein mainly address devices of analog memory cells such as Flash memory, the methods and systems described herein can also be used in other applications, such as in three-dimensional memory devices.
It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.
This application claims the benefit of U.S. Provisional Patent Application 61/486,330, filed May 16, 2011, whose disclosure is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61486330 | May 2011 | US |
