Patent Application
20110161641
Embedded processors often execute code stored in a private memory (e.g., local storage). Executing code larger than a processor's private memory requires a strategy for swapping pieces of code (code segments) into the private memory before use. In some cases, a code segment may include a branch instruction whose target instruction is located in a different code segment. Each time an instruction cache manager retrieves and stores code, the instruction cache manager identifies a location from which to retrieve the code in a backing storage area along with a location in an instruction cache area to store the code.
A method, information handling system, and computer program product are disclosed that executes a direct branch instruction stored in an instruction cache line. Upon execution, the direct branch instruction branches to a branch descriptor, which includes a trampoline branch instruction and a target instruction space address. The trampoline branch instruction sends a branch descriptor pointer to an instruction cache manager that, in turn, extracts the target instruction space address from the branch descriptor and branches to a target instruction corresponding to the target instruction space address.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings, wherein:
Certain specific details are set forth in the following description and figures to provide a thorough understanding of various embodiments of the disclosure. Certain well-known details often associated with computing and software technology are not set forth in the following disclosure, however, to avoid unnecessarily obscuring the various embodiments of the disclosure. Further, those of ordinary skill in the relevant art will understand that they can practice other embodiments of the disclosure without one or more of the details described below. Finally, while various methods are described with reference to steps and sequences in the following disclosure, the description as such is for providing a clear implementation of embodiments of the disclosure, and the steps and sequences of steps should not be taken as required to practice this disclosure. Instead, the following is intended to provide a detailed description of an example of the disclosure and should not be taken to be limiting of the disclosure itself. Rather, any number of variations may fall within the scope of the disclosure, which is defined by the claims that follow the description.
As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects of the present disclosure are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The following detailed description will generally follow the summary of the disclosure, as set forth above, further explaining and expanding the definitions of the various aspects and embodiments of the disclosure as necessary.
A system, method, and program product are disclosed that utilize local storage address space semantics within a synergistic processing unit (SPU) for swapping pieces of instruction code into the local storage before execution. For each direct branch instruction, the instruction code includes a “branch descriptor” that includes a trampoline branch instruction. When called, the trampoline branch sends a branch descriptor pointer to an instruction cache manager that, in turn, extracts a target instruction space address from the branch descriptor, and branches to a target instruction corresponding to the target instruction space address accordingly.
Control plane 110 includes processing unit 120, which runs operating system (OS) 125. For example, processing unit 120 may be a Power PC core that is embedded in PEA 100 and OS 125 may be a Linux operating system. Processing unit 120 manages a common memory map table for PEA 100. The memory map table corresponds to memory locations included in PEA 100, such as L2 memory 130 as well as non-private memory included in data plane 140.
Data plane 140 includes Synergistic Processing Elements (SPE) 150, 160, and 170. Each SPE processes data information and each SPE may have different instruction sets. For example, PEA 100 may be used in a wireless communications system and each SPE may be responsible for separate processing tasks, such as modulation, chip rate processing, encoding, and network interfacing. In another example, each SPE may have identical instruction sets and may be used in parallel to perform operations benefiting from parallel processes. Each SPE includes a synergistic processing unit (SPUs 155, 165, 175), which is a processing core, such as a digital signal processor, a microcontroller, a microprocessor, or a combination of these cores. Each SPU includes a local storage area (local stores 158, 168, and 178), which may be segmented into private and non-private memory. Each of local stores 158, 168, and 178 store a cache directory and tag directory (instruction and/or data), along with a cache manager (see
While
In order to effectively move instructions from backing store 135 to icache 230, icache manager 220 requires an effective address within backing store 135 that corresponds to the location of the target instruction (target backing store address 280), as well as a local storage address within icache 230 to store the instruction (target local store address 260). In addition, icache manager 220 requires an instruction tag that corresponds to the target instruction in order to utilize ITAG directory 225 and determine a cache hit or a cache miss (target ITAG 270). As discussed herein, icache manager 220 uses an instruction's “instruction space address” (target instruction space address 255) to compute an instruction's target backing store address, target local store address, and target ITAG. The instruction space address is an address given to an instruction at link/load time based upon the location of the instruction in a program (program 250).
When icache manager 220 is requested (by an application thread) to branch to a particular target instruction, icache manager 220 determines whether the target instruction already resides in icache 230 by checking whether the target instruction's corresponding instruction tag (ITAG) is located in ITAG directory 225 (target ITAG 270). In order to generate target ITAG 270, icache manager 220 uses target ITAG subroutine 265, which generates target ITAG 270 using target instruction space address 255 and a tag array mask (see
When icache manager 200 needs to load the target instruction from backing store 135 into icache 230, icache manager 220 computes the location of the target instruction in backing store 135 (target backing store address 280) as well as the location to store the target instruction in icache 230 (target local store address 260). Icache manager 220 utilizes target instruction space address 255 to generate these addresses as discussed below.
In the example shown in
In order to identify the location in backing store 135 to retrieve the instruction (target backing store address 280), icache manager 220 uses backing store subroutine 275, which generates an offset using target instruction space address 255 and an icache base address, and uses the offset and a mask to generate target backing store address 280 (see
When an application thread executes direct branch instruction 310, direct branch instruction 310 branches to branch descriptor 330. Branch descriptor 330 includes trampoline branch instruction 335 and target instruction space address 345. A trampoline branch is an instruction that, when executed, branches to, or “bounces” to icache manager 220, thus causing a trampoline effect. When branch instruction 310 branches to branch descriptor 330, trampoline branch instruction 335 is invoked, which branches to icache manager 220 and loads pointer 340 into a link register via a branch and set link instruction, which points back to branch descriptor 330. In turn, icache manager 220 uses pointer 340 to locate branch descriptor 330 and retrieve target instruction space address 345. Icache manager 220 uses target instruction space address 345 to generate various addresses and locate a target instruction corresponding to direct branch instruction 310 (see
Likewise, when the application thread executes direct branch instruction 320, the branch instruction branches to branch descriptor 350, which is different than branch descriptor 330. Branch descriptor 350 includes trampoline branch instruction 355 and target instruction space address 365. Target instruction space address 365 corresponds to a location of the target instruction for branch instruction 320. When branch instruction 320 branches to branch descriptor 350, trampoline branch instruction 355 is invoked, which branches to icache manager 220 and loads pointer 360 into the link register via a branch and set link instruction, which points back to branch descriptor 350. In turn, icache manager 220 uses pointer 360 to locate branch descriptor 350 and retrieve target instruction space address 365.
Processing commences at 400, whereupon processing retrieves an instruction from source code 410 at step 405. A determination is made as to whether the retrieved instruction is a branch instruction (decision 420). If the instruction is not a branch instruction, decision 420 branches to “No” branch 422 whereupon processing compiles the instruction (step 425) in a traditional manner known to those skilled in the art.
On the other hand, if the retrieved instruction is a branch instruction, decision 420 branches to “Yes” branch 428, whereupon a determination is made as to the type of branch instruction (decision 430). If the instruction is a direct branch instruction, decision 430 branches to “Direct” branch 432 whereupon processing generates a branch descriptor that includes a trampoline branch instruction and a target instruction space address at step 440. During runtime execution, the direct branch instruction branches to the trampoline branch instruction, which sends a pointer to the icache manager and, in turn, the icache manager retrieves the target instruction space address from the branch descriptor (see
If the branch type is an indirect branch, however, decision 430 branches to “Indirect” branch 438, whereupon processing generates a number of instructions (step 460) to handle the indirect branch during runtime execution. The instructions include an instruction to translate the indirect branch's target instruction space address to an instruction tag (ITAG) along with an instruction to look up the ITAG in an icache directory (icache directory 225 shown in
A determination is made as to whether there are more instructions to process in source code 410 (decision 480). If there are more instructions to process, processing branches to “Yes” branch 482, which loops back to retrieve and process the next instruction. This looping continues until there are no more source code instruction to process, at which point decision 480 branches to “No” branch 488 whereupon processing ends at 490.
Processing commences at 500, whereupon processing (e.g., application thread) loads a direct branch instruction at step 505. The direct branch instruction was arranged at load time to branch to a trampoline branch instruction included in the direct branch's corresponding branch descriptor (see
Icache manager processing commences at 530, whereupon the icache manager retrieves the branch descriptor pointer from the link register at step 535. At step 540, the icache manager uses the branch descriptor pointer to locate and extract the target instruction space address from the branch descriptor. The target instruction space address is an address that corresponds to the direct branch's target instruction.
At step 545, the icache manager computes a target ITAG from the target instruction space using a tag array mask (see
A determination is made as to whether ITAG directory 225 includes the target ITAG (decision 560). If ITAG directory 225 includes the target ITAG (cache hit), decision 560 branches to “Yes” branch 562 whereupon the icache manager translates the target instruction space address to a target local store address at step 564 by masking off a portion of the target instruction space address (see
On the other hand, if ITAG directory 225 fails to include the target ITAG (cache miss), decision 560 branches to “No” branch 568 whereupon processing computes a target backing store address from the target instruction space address using an offset and mask at step 570 (see
Processing looks up the target ITAG in ITAG directory 225 at step 620, and a determination is made as to whether the lookup results in a cache hit or a cache miss (decision 630). If a cache miss occurs, decision 630 branches to “No” branch 632, whereupon processing calls icache manager 220 to move the target instruction from backing store 135 into icache 230 (step 640). Icache manager 220, in turn, translates the target instruction space address to a target backing store address and a target local store address in order to move the target instruction from backing store 135 into icache 230 (see
At step 650, processing translates the target instruction space address to the target local store address and, at step 660, processing retrieves the target instruction from icache 230 at the target local store address. Processing continues program execution at step 670, and ends at 680.
While waiting for the instruction to finish, a determination is made as to whether the target instruction is being evicted from the icache (decision 710). If the target instruction address is being evicted from the icache, decision 710 branches to “Yes” branch 712, whereupon processing translates the target local store address to a target instruction space address and stores the target instruction space address in the link register at step 715. The target instruction space address is stored in the link register such that when the function return completes, processing realizes that the target instruction is no longer in icache 230 and should call the icache manager to move the target instruction from backing store 135 into icache 230 (discussed below). On the other hand, if the target instruction is not evicted from the icache, decision 710 branches to “No” branch 718 bypassing translation steps.
A determination is made as to whether the function return has completed (decision 730). If the function return has not yet completed, decision 730 branches to “No” branch 732, which loops back to monitor function return completion and target instruction eviction. This looping continues until the function return completes, at which point decision 730 branches to “Yes” branch 738 whereupon processing retrieves the link register value from register store 720 (step 740).
A determination is made as to whether the link register value is a target local store address (TLSA) or a target instruction space address (TISA) (decision 750). If the link register value is a target instruction space address, decision 750 branches to “TISA” branch 752, whereupon processing calls icache manager 220 to move the target instruction from backing store 135 into icache 230 (step 760). Icache manager 220, in turn, translates the target instruction space address to a target backing store address and a target local store address in order to move the target instruction from backing store 135 into icache 230 (see
At step 770, processing branches to the target address at the target local store address and continues program execution at step 780. Processing ends at 790.
tag array mask=Number of cache lines−1
ITAG index=(TISA/linesize) & tag mask
Next, at step 850, the icache manager generates the target instruction tag at step 850 from the generated ITAG index, such as by using the instruction:
Target ITAG=tag[ITAG index]
The icache manager may then use the target ITAG to look in the ITAG directory and determine whether a corresponding target instruction is located in the icache or whether the icache manager should retrieve the target instruction from backing store and load it into the icache. Processing ends at 860
offset=(TISA−icachebase)
Next, at step 890, the icache manager generates the target backing store address (TBSA) using the generated offset and mask that preserves an index into a cache array, such as with the instruction:
TBSA=(offset&mask that preserves idx into cache array)|(offset>>(18−log 2 icachesize))
where “&” is a bitwise AND operator; “|” is a bitwise OR operator; and “>>” is a bitwise right shift. The icache manager may then use the target backing store address to retrieve the target instruction from backing store at the target backing store address, and load the target instruction into the icache (see
Northbridge 915 and Southbridge 935 connect to each other using bus 919. In one embodiment, the bus is a Direct Media Interface (DMI) bus that transfers data at high speeds in each direction between Northbridge 915 and Southbridge 935. In another embodiment, a Peripheral Component Interconnect (PCI) bus connects the Northbridge and the Southbridge. Southbridge 935, also known as the I/O Controller Hub (ICH) is a chip that generally implements capabilities that operate at slower speeds than the capabilities provided by the Northbridge. Southbridge 935 typically provides various busses used to connect various components. These busses include, for example, PCI and PCI Express busses, an ISA bus, a System Management Bus (SMBus or SMB), and/or a Low Pin Count (LPC) bus. The LPC bus often connects low-bandwidth devices, such as boot ROM 996 and “legacy” I/O devices (using a “super I/O” chip). The “legacy” I/O devices (998) can include, for example, serial and parallel ports, keyboard, mouse, and/or a floppy disk controller. The LPC bus also connects Southbridge 935 to Trusted Platform Module (TPM) 995. Other components often included in Southbridge 935 include a Direct Memory Access (DMA) controller, a Programmable Interrupt Controller (PIC), and a storage device controller, which connects Southbridge 935 to nonvolatile storage device 985, such as a hard disk drive, using bus 984.
ExpressCard 955 is a slot that connects hot-pluggable devices to the information handling system. ExpressCard 955 supports both PCI Express and USB connectivity as it connects to Southbridge 935 using both the Universal Serial Bus (USB) the PCI Express bus. Southbridge 935 includes USB Controller 940 that provides USB connectivity to devices that connect to the USB. These devices include webcam (camera) 950, infrared (IR) receiver 948, keyboard and trackpad 944, and Bluetooth device 946, which provides for wireless personal area networks (PANs). USB Controller 940 also provides USB connectivity to other miscellaneous USB connected devices 942, such as a mouse, removable nonvolatile storage device 945, modems, network cards, ISDN connectors, fax, printers, USB hubs, and many other types of USB connected devices. While removable nonvolatile storage device 945 is shown as a USB-connected device, removable nonvolatile storage device 945 could be connected using a different interface, such as a Firewire interface, etcetera.
Wireless Local Area Network (LAN) device 975 connects to Southbridge 935 via the PCI or PCI Express bus 972. LAN device 975 typically implements one of the IEEE 802.11 standards of over-the-air modulation techniques that all use the same protocol to wireless communicate between information handling system 900 and another computer system or device. Optical storage device 990 connects to Southbridge 935 using Serial ATA (SATA) bus 988. Serial ATA adapters and devices communicate over a high-speed serial link. The Serial ATA bus also connects Southbridge 935 to other forms of storage devices, such as hard disk drives. Audio circuitry 960, such as a sound card, connects to Southbridge 935 via bus 958. Audio circuitry 960 also provides functionality such as audio line-in and optical digital audio in port 962, optical digital output and headphone jack 964, internal speakers 966, and internal microphone 968. Ethernet controller 970 connects to Southbridge 935 using a bus, such as the PCI or PCI Express bus. Ethernet controller 970 connects information handling system 900 to a computer network, such as a Local Area Network (LAN), the Internet, and other public and private computer networks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
While particular embodiments of the present disclosure have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, that changes and modifications may be made without departing from this disclosure and its broader aspects. Therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this disclosure. Furthermore, it is to be understood that the disclosure is solely defined by the appended claims. It will be understood by those with skill in the art that if a specific number of an introduced claim element is intended, such intent will be explicitly recited in the claim, and in the absence of such recitation no such limitation is present. For non-limiting example, as an aid to understanding, the following appended claims contain usage of the introductory phrases “at least one” and “one or more” to introduce claim elements. However, the use of such phrases should not be construed to imply that the introduction of a claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to disclosures containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an”; the same holds true for the use in the claims of definite articles.
