Patent Application
20070266263
The present invention relates to a speed adjustment system and method for performing the same, and particularly in an adjustable chip-speed system, which depends upon various applications of an integrated chip to determine adaptive power saving behaviors.
Generally speaking, the power consumption amount is typically deemed one of the performance indexes for a variety of electrical systems, for example, 3 C (communication, computing, and consumptive) products. An overhigh power consumption is harmful to the heat dissipation, reliability and durability of the electrical system. Therefore, it is a significant topic for the manufacturers to establish a power saving configuration.
As well known in the art, the power consumption amount may be frequently varied upon both a power supply management and a system operating speed (i.e. an operating frequency) of the electrical system (like an IC chip). For an oscillator in support of synchronous operations of the electrical system, an operating frequency output from the oscillator is further considered proportional to the power (or core) voltage that is supplied to the oscillator. This brings a way to adjustably increase/decrease the output frequency based on a difference from a fixed reference frequency to raise up/drop down the power supply voltage in levels.
As well known in the art, the same-model electrical systems, i.e. IC chips, respectively applied in different configurations might have the same power consumption behaviors, even under different system clock speeds that are actually required for the different configurations. For example, a standardized chip, which can operate for a normal configuration (e.g. a personal computer) at a maximum system clock frequency of up to 500 MHz under a specific voltage supply of 1.2 V, is selectively used for a mobile configuration (e.g. a mobile phone) at a chip operating speed of only 400 MHz enough to keep the mobile configuration stably running, needless to reach a speed of 500 MHz. This causes a waste on the power (i.e. under a voltage supply of 1.2 V) capable of achieving the maximum clock speed of 500 MHz, which is consumed to perform the clock speed of approximate 400 MHz. Beside, the power saving behaviors adapted by the same-type chips applied for the different configurations are kept the same as each other. Therefore, the conventional electrical system is unable to provide different configurations with selectable adaptive power saving behaviors.
Furthermore, as well known in the art, fabricating the same-type IC chips under different process speeds would deeply reflect the performance efficiency of these IC chips.
During an identical wafer fabrication process, different level yields of the chips can be distributively depicted on different comers of a statistical chart as a Gaussian Distributions. Most of the chips gather on a Typical-N and Typical-P (TT) corner, and less chips respectively spread on a Fast-N and Fast-P (FF) corner, a Fast-N and Slow-P (FS) corner, a Slow-N and Fast-P (SF) corner or a Slow-N and Slow-P (SS) corner. Under supply of the same power voltage (i.e. 1.2 V), the SS-corner chips inherently operate at a slower speed than the other chips allocated out of the SS corner of the same process, and the FF-corner chips inherently operate at a faster speed than the other chips allocated out of the FF corner of the same process. Nevertheless, yields of these different-corner chips all should be qualified and the chip structures are the same. The difference-corner chips still have the same power saving behaviors, rather than the respective adaptive power saving behaviors. This would result in a power waste for the different-corner chips.
To address the foregoing drawbacks of the prior technology, it is a primary object of the present invention to provide a speed adjustment system and method for performing the same, which determines adaptive power saving behaviors of the electrical system (e.g. an integrated chip) applied for different applications (e.g. a mobile phone, a monitor, a desktop or laptop computer).
It is a secondary object of the present invention to provide a speed adjustment system and method for performing the same, which depends upon different process-speed (so-called “different-corner”) chips to determine the respective adaptive power saving behaviors for the different process-speed chips.
It is another object of the present invention to provide a speed adjustment system and method for performing the same, which depends upon different conditions, e.g. a chip temperature difference, a power consumption mode or a manual order, to determine adaptive power saving behaviors for the same-type chips.
In a first embodiment, the speed adjustment system applied for an electrical system (i.e. a standalone chip) could be used for different applications like a mobile configuration or a computerized configuration, and includes a reference speed generator having a register for pre-storing multiple reference speed values, an operating speed generator having a register for pre-storing multiple operating speed value, a comparing unit for determining whether a predefined logical operational relationship that the operating speed value is identical with or smaller than the reference speed value is satisfied, a voltage controller based on said determination result to determine which logic level of the operating voltage is fed to the speed detector, a voltage-dependent oscillators unit based on the operating voltage supplied to the electrical system to generate multiple operating frequencies which serve as multiple operating speed values and a speed detector for detecting the operating speed value and pre-storing the operating speed values in the operating speed generator as registered.
In a second embodiment, the speed adjustment system further a speed scaling calculator for calculating a speed scaling value of the operating speed value with relation to the reference speed value, and a speed scaling range generator for pre-storing multiple speed scaling ranges, in comparison with the first embodiment. Thus, the comparing unit is operative to determine whether a predefined logical operational relationship that the speed scaling value is in the preset speed scaling range is satisfied or not. Accordingly, the operating speed and voltage supply for the operating chip will be continuously adjusted (raised/lowered) until the predefined logical operational relationship is satisfied to achieve a selected power saving behavior.
Besides, a method for adjusting an operating speed of an electrical system, comprising the steps of:
pre-storing multiple reference speed values;
respectively detecting multiple operating speed values generated relative to an operating voltage supplied to the electrical system;
pre-storing multiple operating speed values;
determining whether or not a predefined logical operational relationship between the operating speed value and the reference speed value is satisfied; and
keeping logic level of the operating voltage unchanged if the predefined logical operational relationship is satisfied; otherwise, adjusting the logic level of the operating voltage until the predefined logical operational relationship is satisfied.
Please refer to a schematic architecture diagram of a speed adjustment system 10 presented in
The reference speed generator 102 as shown in
For another exemplary of a frequency-driven voltage control on the same-type chips for different configurations, a first reference speed value representative of a lowest speed is predetermined in accordance with an operating frequency (i.e. 350 MHz) of the chip enough to support a stable operation of a mobile configuration under a specific voltage supply (i.e. a minimum workable voltage) or a standard voltage supply (i.e. 1.2 V), and a second reference speed value representative of a faster speed is predetermined in accordance with an operating frequency (i.e. 400 MHz) employed by the same-type chip applied for a normal configuration (i.e. PC) under the same voltage supply.
For another exemplary of combination of a frequency-driven and process-driven voltage controls on the same-type and different-corner chips for different configurations, a first speed frequency value representative of a lowest speed is predetermined in accordance with an operating frequency (i.e. 350 MHz) adopted by the SS-corner chip applied for the mobile configuration under a specific voltage supply (i.e. a minimum workable voltage) or a standard voltage supply (i.e. 1.2 V). It is noted that said sampled different-corner chips have the same structures as the electrical system of the present invention under the same fabrication process.
The first embodiment of the present invention will be introduced on utilization of an operating frequency of a sampled SS-corner chip to be as a reference speed value since the SS-corner chip is lower than other corners chip in operating speed, but does not therefore limit the scope of the invention. As well known, an operating frequency adapted by the chip can be regarded as correspondence to the operating speed of the chip. Understandingly, the other corners chips (i.e. a FF corner chip) will consume a higher power than the SS-corner chip does if operating at the same speed under the same configuration. Consequently, the operating speed of the electrical system of the present invention can be reduced with reference to the operating frequency of the sampled SS-corner chip, resulting in reduction of a voltage supply to achieve the lower power consumption.
In other implementation, the specific voltage supply (Ivdd) for the sampled chip (i.e. a SS-corner chip) may be determined by an equation (1) as follows.
Ivdd=1.2V-Delta (1)
The voltage value of 1.2V denotes an exemplar standard voltage supplied to the sampled SS-corner chip but is not used to limit a scope claimed in the present invention. The “Delta” value represents a minimum voltage gap between a first minimum workable voltage applied in a first configuration (e.g. a normal application) and a second minimum workable voltage applied in a second configuration (e.g. a mobile application) lower than the first minimum workable voltage of the first configuration, under different-corner chips. Since the minimum voltage gap can decide number difference of ring oscillators used on the sampled SS-corner chip, a final reference speed value may be generated lower than a normal speed applied in the SS-corner chip with a normal voltage supply, i.e. 1.2V, by way of subtracting the minimum voltage gap from the normal voltage supply.
Turning to
Furthermore, the operating speed generator 112 having an operating speed register is operative to store multiple different operating speed values 1120 thereon, based on different speed conditions, detected from the speed detector 110 and outputs proper one of the operating speed values 1120 to the comparing unit 104.
The comparing unit 104 determines whether a predefined logical operational relationship is accomplished by the operating speed value 1120 and the reference speed value 1020. In the embodiments, the predefined logical operational relationship denotes that the operating speed value 1120 is identical with or smaller than the reference speed value 1020. It also means that the operating speed of the operating chip is identical with or lags behind the reference speed. If the predefined logical operational relationship is satisfied, the comparing unit 104 commands the voltage controller 106 to keep the logic level of an internal operating voltage 1070 unchanged, output from the power supply 107 to the voltage-dependent oscillators unit 108; otherwise to enable the voltage controller 106 to adjust the logic level of the internal operating voltage 1070 output from the power supply 107 to the voltage-dependent oscillators unit 108, based on a difference value determined from the predefined logical operational relationship.
The voltage controller 106 as shown in 3A and 3B has a variable resistor 1060a, 1060b for determining which one logic level of the internal operating voltage (Vdd) 1070 generated from the power supply 107, and a resistance-adjusting unit (not shown) that can be implemented as a software or a hardware, used to adjust resistance of the variable resistor 1060a, 1060b, according to said speed comparison result generated from the comparing unit 104. In an exemplary shown in
The voltage-dependent oscillators unit 108 has multiple ring oscillator (ROSC) sets and depends upon the logic level of the varied operating voltage 1070 generated from the power supply 107 to select proper number of the ring oscillator (ROSC) sets for respectively emulating the multiple operating frequencies to be detected by the speed detector 110. The emulated operating frequency can fully reflect an accurate system operating frequency employed by the electrical system (as an integrated chip), thereby steering more adaptive power saving behavior. Please be noted that each selected ring oscillator (ROSC) set may contain one ring oscillator or more than one of the ring oscillators.
The speed detector 110 as depicted in
Turning to
For an exemplary of the process-driven voltage control on the same-type and different-corner chips for the same configurations, a reference speed value 1020 recorded in the reference speed generator 100 may be predetermined with an operating frequency of 380 MHz steered by a sampled slow-slow (SS) corner chip under a specific voltage supply of 1.2 V. However, an actual operating speed value 1120 (provided from the operating speed generator 112) of the same-type, TT-corner chip that is detected at 400 MHz is higher than the reference speed value 1020 of 380 MHz during the comparison. Under this manner, the voltage controller 106 will be enabled to adjust the variable resistor 1060a or 1060b to lower the logic level of the operating voltage 1070 generated from the power supply 107. Based on the changed operating voltage 1070, the operating speed value 1120 will be lowered and compared with the reference speed value 1020 again to form a loop. By successively adjusting the operating voltage 1070 in each loop, the operating speed value 1120 may be successively renewed from 400 MHz to 380 MHz until the operating speed value 1120 approaches the reference speed value 1020. Thus, a power saving behavior adaptive for the same-type and different-corner chips applied in the same configurations can be selectively achieved.
For another exemplary of the frequency-driven voltage control on the same-type chips for different configurations, the reference speed value is predetermined with a chip operating frequency of 350 MHz that is sufficient in support of a stable operation of a mobile phone under a specific voltage of 1.2 V. Since the same-type chip can run at a maximum speed of up to 400 MHz for a personal computer, an actual operating speed value 1120 of the same-type chip applied for the mobile phone can be detected at 390 MHz, which is higher than the reference speed value (350 MHz) 1020 during the comparison. By utilizing the same invention concept as aforementioned, the operating speed value 1120 is successively lowered from 390 MHz to 350 MHz until the operating speed value 1120 approaches the reference speed value 1020. Due to difference of the reference speed values required between the frequency-driven voltage control and the foregoing process-driven voltage control, another power saving behavior adaptive for the same-type chips applied in different configurations can be selectively achieved.
For another exemplary of combination of a frequency-driven and process-driven voltage controls on the same-type and different-corner chips for different configurations, the reference speed value is predetermined with an operating frequency of 340 MHz, which is sufficient in support of stable operation of a sampled SS-corner chip applied in the mobile phone under the specific voltage supply of 1.2 V Since the SS-corner chip can run at a maximum speed of up to 400 MHz for a personal computer, an actual operating speed value 1120 of the same-type, different-corner (i.e. TT-corner) chip applied for the mobile phone may be detected at 390 MHz, which is higher than the reference speed value (340 MHz) 1020 during the comparison. By utilizing the same invention concept as aforementioned, the operating speed value 1120 is successively lowered from 390 MHz to 340 MHz until the operating speed value 1120 approaches the reference speed value 1020. Thus, another power saving behavior adaptive for the same-type and different-corner chips applied in the different configurations can be selectively achieved.
Further referring to a schematic architecture diagram of another speed adjustment system 20 illustrated in
The reference speed generator 202 is configured as the same structure shown in
The operating speed generator 216 having an operating speed register is operative to pre-store multiple different operating speed value, by way of detection of the speed detector 214, respectively generated from the selected ring oscillator (ROSC) sets of the electrical system, and then selectively outputs proper one of the operating speed values 2160 with regard to the selected reference speed value 2020 to the speed scaling calculator 204.
The speed scaling calculator 204 is operative to calculate a speed scaling value 2040 to the comparing unit 208, by scaling the operating speed value 2160 relative to the reference speed value 2020. For example, a speed scaling value of “110%” denotes that the operating speed of the operating chip is being faster than the predetermined reference speed (i.e. an operating frequency of the sampled SS-corner chip).
The speed scaling range generator 206 implemented as a software or a hardware (e.g. a register) provides the comparing unit 208 with proper one of multiple different speed scaling range parameter sets 2060 which are preset on the speed scaling range generator 206. The preset speed scaling range parameter sets 2060 are designed to contain different scaling conditions, for example, a scaling of 85%, a range scaling of 80%˜100%, or down to 95%, for usage of different configurations and/or different-corner chips. Thus these different scaling conditions will bring different adaptive power-saving behaviors to the different-corner operating chips applied for different configurations. The preset speed scaling range should be predetermined upon a control signal 2030 in response to some special functions (i.e., a power saving mode), a detected environment (i.e. a higher temperature), the user demands, the kinds of the electrical system, or the other factors influencing the power consumption.
The comparing unit 208 determines whether a predefined logical operational relationship is satisfied or not. For example, if the speed scaling value 2040 is “95% ” which is included within the preset speed scaling range of 80%˜100%, it means that the power supply of the operating chip has reached a power saving behavior adaptive for the system. Then the comparing unit 208 will enable the voltage controller 210 to keep the logic level of the operating voltage 2110 unchanged, output from the power supply 211 to the voltage-dependent oscillators unit 212. For another example, if the speed scaling value 2040 is “120%” in excess of the preset speed scaling range of “80%˜100%”, it means that power supply of the operating chip has caused a power waste than required by the system. Then the comparing unit 208 will enable the voltage controller 210 to reduce the logic level of the internal operating voltage 2110 output from the power supply 211, which is fed to the voltage-dependent oscillators unit 212. The voltage controller 210 may have the same configuration as shown in either
Similarly to the first embodiment of
Referring to
Step S500a, selecting and enabling proper number of ring oscillator sets, based on an operating voltage supply or a core voltage of the operating chip;
Step S502a, detecting an operating frequency generated from each of the selected ring oscillator sets based on operating voltage supply, to serve as a corresponding operating speed value to be pre-stored on an operating speed register (detailed as illustrated in
Step S504a, programmably presetting multiple reference speed values to a reference speed register of an operating speed generator;
Step S506a, calculating a speed scaling value of the operating speed value relative to the corresponding reference speed value;
Step S508a, programmably presetting multiple speed scaling range parameters on a speed scaling range generator;
Step S510a, determining whether or not a predefined logical operational relationship that the speed scaling value is scoped within one of the corresponding speed scaling range parameters is satisfied; and
Step S516a, if the predefined logical operational relationship is satisfied, keeping the logic level of the operating voltage unchanged, and then returning to step S500a to continue to detect whether a change of the operating speed value occurs, thereby continuously monitoring the power consumption behavior of the operating chip; otherwise, performing the steps S512a and S514a to adjust a variable resistor of a voltage controller to vary the logic level of the operating voltage of the power supply, based on a difference from the speed comparison, and then returning to the step S500a in order to continuously lower the operating frequency and power consumption of the operating chip per cycle of the loop established from the step S500a to S516a until the predefined logical operational relationship is satisfied. A required power saving behavior adaptive for the operating chip will be therefore obtained.
Further referring to
Step S500b, initializating the operating chip to load several required configurations and settings;
Setp S502b, presetting multiple reference speed values on a reference frequency register of a reference frequency generator for pre-storage;
Step S504b, selecting and enabling proper number of ring oscillator sets of the operating chip, based on an operating voltage supply;
Step S506b, detecting a corresponding operating frequency generated from each of the selected ring oscillator sets, to serve as an operating speed value to be pre-stored on an operating speed register (detailed as illustrated in
Step S508b, outputting proper one of the operating speed values from the operating speed register;
Step S510b, determining whether the operating speed value is lower than one of the reference speed values, corresponding to the operating speed value. In another case, a speed determination of whether a speed scaling value of the operating speed value relative to the reference speed value is in a preset speed scaling range or not can be implemented as the steps 506a and 510a shown in
Step S512b, if the operating speed value (i.e. 299 MHz) is lower than the reference speed value (i.e. 300 MHz), keeping the logic level of the operating voltage unchanged, and then ending; otherwise if the operating speed value (i.e. 350 MHz) is being faster than the reference speed value (i.e. 300 MHz) to result in a power waste behavior, performing the step S516b and S514b to adjust a variable resistor of a voltage controller to vary the logic level of the operating voltage, based on a speed difference from the speed comparison, and then returning to the step S504b for continuously lowering the operating frequency of the chip per cycle of a loop established from the step S504b to S510b, until the operating speed value is completely lower than the reference speed value. A required power saving behavior is therefore obtained.
Detailed in the step S502a of
Step S710, receiving a calibrating clock signal having a standard working frequency provided from an external device or other component;
Step S720, counting up number of cycles at the standard working frequency by a second counter for a specific time period;
Step S712, receiving an operating clock signal having an operating frequency generated from each one of the selected ROSC sets of the voltage-dependent oscillators unit;
Step S722, counting up number of cycles at the operating frequency by a first counter in synchronization with the beginning of counting up of the second counter for the same specific time period;
Step S730, pre-storing number value of counted cycles indicative of the operating frequency to serve as the operating speed value; and
Step S740, determining whether all of the selected ROSC sets have been detected; if so, going to the step S506a of
Please note that the present invention can be implemented to adjust (rising or lowering) an adaptive power supply of an electrical system for different conditions, for example, a power saving (sleeping) mode for a non-operating period, a light power mode for application of a word-processing software or an user-reading period, or a high performance power consumption mode for supporting a 3D graphic engine, by way of predetermining multiple different speed scaling range values for said different conditions. Furthermore, the reference speed value and the operating speed value are not implemented only for limited in frequency value but can be implemented by other parameters under some conditions, like an operating temperatures on the operating chip and a preset reference temperature, or by other signals based on activation of some specific functions, like a huge/less image-data process. The speed scaling range value can be a specific range or a value (e.g. lower than a specified temperature value or a speed percentage), which can be reset during fabrication of the chip or reset by the user on demands.
Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
