This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2010-113873 filed on May 18, 2010 in Japan, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a spin transistor and an integrated circuit.
Recently, spin FETs that use a magnetic material for the sources and drains of conventional MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and generate ON and OFF states by utilizing changes in magnetization direction of the magnetic material in accordance with the applied voltage have been known.
Such a spin FET has a two-dimensional electronic channel as the channel, and carriers move in the two-dimensional electronic channel. The precession of the carriers moving in the two-dimensional electronic channel is controlled by the Rashba effect. Where the spins of the carriers at the drain end are parallel to the spins in the drain, the carriers are conducted through the drain region. Where the spins of the carriers at the drain end are antiparallel to the spins in the drain, the carriers are not conducted through the drain. In this spin FET, however, high-precision carrier spin control needs to be performed in the channel. If there are fluctuations in the characteristics and processes, the standby power consumption becomes particularly high.
a) is a top view of a spin transistor according to a first embodiment;
b) is a cross-sectional view of the spin transistor according to the first embodiment, taken along the line I(a)-I(a) of
a) is a schematic view showing the relationship between the spin state density and the Fermi energy of a half-metal ferromagnetic material according to the first embodiment;
b) is a circuit diagram of the spin transistor according to the first embodiment;
a) through 3(f) are cross-sectional views of relevant parts, showing a method of manufacturing the spin transistor according to the first embodiment;
a) is a circuit diagram showing a case where a VCC signal is input to a third magnetic region according to the first embodiment;
b) is a circuit diagram showing a case where a GND signal is input to the third magnetic region according to the first embodiment;
a) is a circuit diagram of a NAND operational circuit using a spin transistor according to a third embodiment;
b) is a truth table of the NAND operational circuit according to the third embodiment;
c) is a circuit diagram of the NAND operational circuit using the spin transistor according to the third embodiment; and
a) and 7(b) are circuit diagrams of the NAND operational circuit using the spin transistor according to the third embodiment.
A spin transistor according to an embodiment includes: A spin transistor comprising: a first magnetic region including a first input terminal; a second magnetic region including a second input terminal; a third magnetic region including a first output terminal; and a third input terminal. The first magnetic region supplies a first polarized signal polarized in a first magnetization direction in accordance with a first input signal input through the first input terminal. The second magnetic region supplies a second polarized signal polarized in a second magnetization direction opposite from the first magnetization direction in accordance with a second input signal input through the second input terminal, the second input signal being different from the first input signal. The third magnetic region outputs the first polarized signal supplied from the first magnetic region in accordance with a third input signal input through the third input terminal, and outputs the second polarized signal supplied from the second magnetic region in accordance with a fourth input signal input through the third input terminal, the fourth input signal being different from the third input signal.
a) is a top view of a spin transistor according to a first embodiment.
This spin transistor 1 includes a first magnetic region 26 that has a contact 42 as a first input terminal and supplies a signal polarized in a first magnetization direction in accordance with a first signal that is input through the contact 42. The spin transistor 1 also includes a second magnetic region 28 that has a contact 44 as a second input terminal and supplies a signal polarized in a second magnetization direction in accordance with a second signal that is input through the contact 44. The second magnetization direction is the opposite direction from the first magnetization direction. The spin transistor 1 also includes a third magnetic region 30 that has a contact 46 as a first output terminal. The spin transistor 1 also includes a contact 48 as a third input terminal. The contact 48 is electrically connected to a gate electrode 38, and the third magnetic region 30 is capacitive-coupled with the gate electrode 38 through a gate insulating film 36. The third magnetic region 30 outputs, through the contact 46, the signal polarized in the first magnetization direction and supplied from the first magnetic region 26, in accordance with a third signal that is input through the contact 48. The third magnetic region 30 also outputs, through the contact 46, the signal polarized in the second magnetization direction and supplied from the second magnetic region 28, in accordance with a fourth signal that is input through the contact 48.
In this spin transistor 1, the first magnetic region 26, a first conductive region 32, the third magnetic region 30, a second conductive region 34, and the second magnetic region 28 are arranged adjacent to one another on a first insulating film 12, as shown in
A device isolating region 22 having a STI (Shallow Trench Isolation) structure is formed around the first through third magnetic regions 26, 28, and 30, and the first and second conductive regions 32 and 34. The device isolating region 22 is made of SiO2, for example.
The first insulating film 12 is formed on a semiconductor substrate 10, for example. The first insulating film 12 is made of SiO2, for example.
The semiconductor substrate 10 is a Si-based substrate containing Si as the main component, for example. The spin transistor 1 of this embodiment is manufactured with the use of a SOI substrate having a SOI (Silicon On Insulator) structure having the later described single-crystal layer formed on the semiconductor substrate 10 via the first insulating film 12.
An interlayer insulating film 40 is formed to cover the device isolating region 22, a gate insulating film 36, and a gate electrode 38, for example, as shown in
The first magnetic region 26 is electrically connected to the contact 42 formed on the interlayer insulating film 40, for example. The second magnetic region 28 is electrically connected to the contact 44 formed on the interlayer insulating film 40, for example. The third magnetic region 30 is electrically connected to the contact 46 formed on the interlayer insulating film 40, for example. The gate electrode 38 is electrically connected to the contact 48 formed on the interlayer insulating film 40, for example.
The contacts 42, 44, 46, and 48 are made of a metal material such as Cu, Ta, W, or Ti. A diffusion preventing film to prevent diffusion of the metal material is formed around the contacts 42, 44, 46, and 48, for example, but such a diffusion preventing film is not shown in the drawings.
a) is a schematic view showing the relationship between the spin state density and the Fermi energy of a half-metal ferromagnetic body according to the first embodiment.
Here, a VCC signal as the source voltage is input to the first magnetic region 26 via the contact 42, as shown in
Each input signal from the previous stage is input to the gate electrode 38 via the contact 48, as shown in
The third magnetic region 30 accepts electrons spin-polarized by switching magnetization directions in accordance with signals that are input via the contact 48, the gate electrode 38, and the gate insulating film 36. Therefore, the spin transistor 1 outputs the spin-polarized electrons supplied from the first or second magnetic region 26 or 28, without an inversion layer formed immediately below the gate electrode 38. Outputting two types of signals in accordance with the magnetization direction of the third magnetic region 30, the spin transistor 1 as a single spin transistor realizes a switching circuit that has conventionally been realized by a CMOS (Complementary Metal Oxide Semiconductor), for example. Furthermore, the spin transistor 1 has a fewer contacts than in those in a conventional CMOS. It should be noted that, in the following description, the circuit connected to the IN side of the subject circuit will be referred to as the previous stage, and the circuit connected to the OUT side will be referred to as the later stage.
The first through third magnetic regions 26, 28, and 30 are preferably made of a ferromagnetic material that has a high consistency with III-V group semiconductors, a Curie temperature equal to or higher than room temperature (300 K, for example), and a wide bandgap in the vicinity of the Fermi level EF. Such a ferromagnetic material is preferably a half-metal ferromagnetic material having a band structure in which the Fermi level EF runs across one of the spin bands, and runs across a bandgap in the other spin band, for example, as shown in
When a VCC signal is input to the first magnetic region 26, the spin state of the electrons in the crystals is a down state, as shown in
When a GND signal is input to the second magnetic region 28, the spin state of the electrons in the crystals is an up state, as shown in
As shown in
It should be noted that the first through third magnetic regions 26, 28, and 30 may be made of the same ferromagnetic material having the band structure shown in
The first and second conductive regions 32 and 34 are made of a material that forms Schottky junctions with the first through third magnetic regions 26, 28, and 30. The first and second conductive regions 32 and 34 may be made of a Si single-crystal material, for example. Spin-polarized electrons travel through the first and second conductive regions 32 and 34, but there is no need to implant impurities in the first and second conductive regions 32 and 34. In addition, spin-polarized electrons travel beyond the tunnel barrier on the boundary between the first or second conductive region 32 or 34 and the third magnetic region 30. Therefore, there is no need to control the precession by the Rashba effect in the first and second conductive regions 32 and 34. Accordingly, the spin transistor 1 does not need to perform precise control on the sizes and the like with respect to the length of the channel region.
A method of manufacturing the spin transistor of this embodiment is described in the following description.
a) through 3(f) are cross-sectional views of related parts, showing the method of manufacturing the spin transistor according to the first embodiment.
First, a SOI substrate having the first insulating film 12 and a single-crystal film 14 formed thereon is prepared on the semiconductor substrate 10. The film thickness of the first insulating film 12 is 150 nm, for example. The single-crystal film 14 is a Si single-crystal film and has a film thickness of 20 nm, for example. A second insulating film 16 is then formed on the single-crystal film 14 by CVD (Chemical Vapor Deposition). The second insulating film 16 is a SiO2 film, for example. The film thickness of the second insulating film 16 is 10 nm, for example. As shown in
A resist pattern 20 is then formed by a photolithography technique. As shown in
As shown in
As shown in
As shown in
The gate insulating film 36 is then formed by CVD. The gate insulating film 36 is a SiO2 film, for example. The film thickness of the gate insulating film 36 is 3 nm, for example.
As shown in
The interlayer insulating film 40 and the contacts 42, 44, 46, and 48 are then formed through known procedures, and the spin transistor 1 shown in
When the first through third ferromagnetic regions 26, 28, and 30 are made of different ferromagnetic materials, the following manufacturing procedures are added. Where the first through third magnetic regions 26, 28, and 30 are made of two ferromagnetic materials, the procedures up to the one illustrated in
Next, an example and operations of an integrated circuit using spin transistors according to this embodiment are described.
a) is a circuit diagram showing a case where a VCC signal is input to the third magnetic region according to the first embodiment.
When a VCC signal output from the previous stage is input to the third magnetic region 30, the third magnetic region 30 has a downward magnetization direction, as shown in
Meanwhile, the second magnetic region 28 has an upward magnetization direction in accordance with an input GND signal. A spin current spin-polarized in an upward direction is about to flow into the third magnetic region 30 via the second conductive region 34 at this point, but cannot flow into the third magnetic region 30 since the third magnetic region 30 has downward spins.
Accordingly, the spin transistor 1 outputs the VCC signal through the third magnetic region 30.
The case where a GND signal is input to the third magnetic region 30 is now described. When a GND signal output from the previous stage is input to the third magnetic region 30, the third magnetic region 30 has an upward magnetization direction, as shown in
Meanwhile, the first magnetic region 26 has a downward magnetization direction in accordance with a VCC signal supplied from the power supply unit. A spin current spin-polarized in a downward direction is about to flow into the third magnetic region 30 via the first conductive region 32 at this point, but cannot flow into the third magnetic region 30 since the third magnetic region 30 has upward spins.
Accordingly, the spin transistor 1 outputs the GND signal through the third magnetic region 30.
With the spin transistor according to the first embodiment, the problem of high standby power consumption due to fluctuations in the size of the channel region and others can be eliminated in a device using the spin information about carriers.
In the circuit shown in
As shown in
As shown in
In a case where a VCC signal output from the previous stage is input to the third magnetic region 52 of the spin transistor 5, the third magnetic region 52 has a downward magnetization direction. The first magnetic region 50 has a downward magnetization direction in accordance with a VCC signal supplied from a power supply unit. Accordingly, a spin current spin-polarized in a downward direction can flow into the third magnetic region 52 via the first magnetic region 50.
Meanwhile, the second magnetic region 51 of the spin transistor 5 has an upward magnetization direction in accordance with an input GND signal. A spin current spin-polarized in an upward direction is about to flow into the third magnetic region 52 at this point, but cannot flow into the third magnetic region 52 since the third magnetic region 52 has downward spins.
Accordingly, the spin transistor 5 outputs the VCC signal through the third magnetic region 52.
When the VCC signal output from the spin transistor 5 is input to the third magnetic region 62 of the spin transistor 6, the third magnetic region 62 has a downward magnetization direction. The second magnetic region 61 has a downward magnetization direction in accordance with an input GND signal. Accordingly, a spin current spin-polarized in a downward direction can flow into the third magnetic region 62 via the second magnetic region 61.
Meanwhile, the first magnetic region 60 of the spin transistor 6 has an upward magnetization direction in accordance with a VCC signal supplied from the power supply unit. A spin current spin-polarized in an upward direction is about to flow into the third magnetic region 62 at this point, but cannot flow into the third magnetic region 62 since the third magnetic region 62 has downward spins.
Accordingly, the spin transistor 6 outputs the GND signal through the third magnetic region 62.
According to the second embodiment, a cascade connection in a device using spin transistors characterized by low power consumption can be realized.
Next, a NAND operational circuit using a spin transistor is described as an example of a logic operational circuit. Since a number of NAND operational circuits are used for an integrated circuit, the area occupied by the NAND operational circuits can be made smaller by reducing the number of components forming each NAND operational circuit, and the area of the entire integrated circuit can be made smaller, accordingly.
a), 6(c), 7(a), and 7(b) are circuit diagrams of the NAND operational circuit using a spin transistor according to a third embodiment.
As shown in
The third and fourth magnetic regions 72 and 73 are placed between the first and second magnetic regions 70 and 71, so as to be connected in series to the first magnetic region 70. Gate electrodes are formed immediately above the respective third and fourth magnetic regions 72 and 73 via a gate insulating film. The third and fourth magnetic regions 72 and 73 are made of a ferromagnetic material that has a downward magnetization direction when a VCC signal is input thereto, and has an upward magnetization direction when a GND signal is input thereto.
The fifth and sixth magnetic regions 74 and 75 are formed between the second magnetic region 71 and the fourth magnetic region 73, so as to be connected in parallel. Gate electrodes are formed immediately above the respective fifth and sixth magnetic regions 74 and 75 via a gate insulating film. The fifth and sixth magnetic regions 74 and 75 are made of a ferromagnetic material that has a downward magnetization direction when a VCC signal is input thereto, and has an upward magnetization direction when a GND signal is input thereto. That is, in the NAND operational circuit 7, third magnetic regions 30 of the first embodiment are combined to form the third through sixth magnetic regions 72 through 75. In the following description, the operations of the NAND operational circuit 7 are described.
First, as shown in
Where a VCC signal output from the previous stage is input to IN1 and IN2, the third through sixth magnetic regions 72 through 75 each have a downward magnetization direction. The first magnetic region 70 also has a downward magnetization direction in accordance with a VCC signal supplied from a power supply unit. Accordingly, a spin current spin-polarized in a downward direction can flow into the third and fourth magnetic regions 72 and 73 via the first magnetic region 70.
Meanwhile, the second magnetic region 71 has an upward magnetization direction in accordance with an input GND signal. A spin current spin-polarized in an upward direction is about to flow into the fifth and sixth magnetic regions 74 and 75 at this point, but cannot flow into the fifth and sixth magnetic regions 74 and 75 since the fifth and sixth magnetic regions 74 and 75 have downward spins.
Accordingly, the NAND operational circuit 7 outputs the VCC signal as OUT. Therefore, the NAND operational circuit 7 performs inputting and outputting with the combination “(IN1, IN2, OUT)=(down, down, down)” in the truth table shown in
Next, a case where a VCC signal is input to IN1 and a GND signal is input to IN2 as shown in
When a VCC signal output from the previous stage is input to IN1, the third and fifth magnetic regions 72 and 74 each have a downward magnetization direction. When a GND signal output from the previous stage is input to IN2, the fourth and sixth magnetic regions 73 and 75 each have an upward magnetization direction.
The second magnetic region 71 has an upward magnetization direction in accordance with a GND signal. Accordingly, a spin current spin-polarized in an upward direction does not flow into the fifth magnetic region 74 having downward spins, but can flow into the sixth magnetic region 75 via the second magnetic region 71.
Meanwhile, the first magnetic region 70 has a downward magnetization direction in accordance with a VCC signal supplied from the power supply unit. A spin current spin-polarized in a downward direction flows into the third magnetic region 72, and is about to further flow into the fourth magnetic region 73 at this point. However, the spin current cannot flow into the fourth magnetic region 73, since the fourth magnetic region 73 has upward spins.
Accordingly, the NAND operational circuit 7 outputs the GND signal as OUT. In this manner, the NAND operational circuit 7 performs inputting and outputting with the combination “(IN1, IN2, OUT)=(down, up, up)” in the truth table shown in
Next, a case where a GND signal is input to IN1 and a VCC signal is input to IN2 as shown in
When a GND signal output from the previous stage is input to IN1, the third and fifth magnetic regions 72 and 74 each have an upward magnetization direction. When a VCC signal output from the previous stage is input to IN2, the fourth and sixth magnetic regions 73 and 75 each have a downward magnetization direction.
The second magnetic region 71 has an upward magnetization direction in accordance with a GND signal. Accordingly, a spin current spin-polarized in an upward direction does not flow into the sixth magnetic region 75 having downward spins, but can flow into the fifth magnetic region 74 via the second magnetic region 71.
Meanwhile, the first magnetic region 70 has a downward magnetization direction in accordance with a VCC signal supplied from the power supply unit. A spin current spin-polarized in a downward direction cannot flow into the third magnetic region 72, since the third magnetic region 72 has upward spins.
Accordingly, the NAND operational circuit 7 outputs the GND signal as OUT. In this manner, the NAND operational circuit 7 performs inputting and outputting with the combination “(IN1, IN2, OUT)=(up, down, up)” in the truth table shown in
Next, a case where a GND signal is input to IN1 and IN2 as shown in
When a GND signal output from the previous stage is input to IN1, the third and fifth magnetic regions 72 and 74 each have an upward magnetization direction. When a GND signal output from the previous stage is input to IN2, the fourth and sixth magnetic regions 73 and 75 each have an upward magnetization direction.
The second magnetic region 71 has an upward magnetization direction in accordance with a GND signal. Accordingly, a spin current spin-polarized in an upward direction can flow into the fifth and sixth magnetic regions 74 and 75 via the second magnetic region 71.
Meanwhile, the first magnetic region 70 has a downward magnetization direction in accordance with a VCC signal supplied from the power supply unit. A spin current spin-polarized in a downward direction cannot flow into the third magnetic region 72, since the third magnetic region 72 has upward spins.
Accordingly, the NAND operational circuit 7 outputs the GND signal as OUT. Therefore, the NAND operational circuit 7 performs inputting and outputting with the combination “(IN1, IN2, OUT)=(up, up, up)” in the truth table shown in
According to the third embodiment, a logic operational circuit that can lower the standby power consumption can be formed.
According to each of the above described embodiments, an inversion layer is not formed immediately below the gate electrode 38, and spin-polarized electrons supplied from the first or second magnetic region 26 or 28 are output. Accordingly, the power consumption can be lowered.
In addition, according to each of the above described embodiments, a circuit is formed with the use of spin transistors. Accordingly, the number of components forming the circuit can be made smaller than that in a case where a circuit is formed with the use of conventional transistors. Thus, an increase in occupied area can be restrained.
It should be noted that the above described embodiments are merely examples, and do not limit the present invention. Various omissions, replacements, modifications, combinations, expansions, and corrections are possible in the above described embodiments, without departing from or changing the technical spirit of the invention.
The spin transistor 1 of the first embodiment includes the gate electrode 38 that controls the Fermi level of the third magnetic region 30. However, a contact may be formed directly on the third magnetic region 30, and a signal may be input through the contact. Likewise, in the third embodiment, contacts may be made on the third through sixth magnetic regions 72 through 75, and signals may be input through those contacts.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2010-113873 | May 2010 | JP | national |