Claims
- 1. A semiconductor memory comprising a plurality of memory cells arranged in rows and columns and having a pair of bit lines for each column, and a two stage differential current sensing amplifier having a pair of input terminals connected to a pair of said bit lines, said differential current sensing amplifier having a pair of input transistors connected to said bit line pair and means for biasing said input transistors into conduction, whereby neither of said input transistors is cut off during reading or writing access to said memory at a time other than testing said memory.
- 2. The semiconductor memory according to claim 1, wherein the bit lines of said semiconductor memory do not have means for equalizing the voltage on said bit lines.
- 3. A semiconductor memory comprising a plurality of memory cells arranged in rows and columns at least one two stage differential current sensing amplifier having a pair of input terminals connected to a pair of bit lines, said differential current sensing amplifier having a pair of input transistors connected to said bit line pair and means for biasing said input transistors into conduction, and wherein neither of said input transistors is cut off during reading or writing access to said memory.
- 4. The semiconductor memory of claim 3, wherein the means for biasing is comprised of a pair of transistors with gate electrodes connected to a voltage reference.
Parent Case Info
This is a continuation of application Ser. No. 08/342,060, filed Nov. 17, 1994, abandoned—which is a divisional of application Ser. No. 07/942,296, filed Sep. 9, 1992, U.S. Pat. No. 5,384,503.
US Referenced Citations (5)
Continuations (1)
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Number |
Date |
Country |
Parent |
09/342060 |
Nov 1994 |
US |
Child |
08/722486 |
|
US |