Patent Application
20070257323
The present invention relates to semiconductor fabrication, and particularly to a stacked contact structure and methods of fabricating the same.
Electrically conductive lines providing, for example, signal transfer are essential in electronic devices as well as semiconductor integrated circuit (IC) devices. The conductive lines on different levels are connected through conductive plugs in required position to provide a predetermined function. Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and/or higher degrees of integration. Among the various features included within a semiconductor device, contact structures typically provide an electrical connection between circuit devices and/or interconnection layers.
A typical contact structure may include forming a contact hole in an interlevel dielectric (ILD) and then filling such a contact hole with a conductive material, for example, a tungsten contact, however, providing disadvantageously high resistance. The contact height is defined by the thickness of the ILD that separates the two levels in the circuit, such as the substrate and higher wiring levels. Unfortunately, while the contact width continually decreases, the contact height cannot decrease proportionately. The contact aspect ratio continues to increase, causing difficulties in metal filling process.
It is therefore desirable to provide a novel contact structure and fabrication methods for improving the process window of the tungsten contact and reducing the contact resistance.
Embodiments of the present invention include stacked contact structures and method of forming the same, which employ a contact plug of a relatively higher resistance stacked by a second contact plug of a relatively lower resistance for improving resistance/capacitance coupling (RC delay).
In one aspect, the present invention provides a stacked contact structure for a semiconductor device. The semiconductor device has a gate structure on a semiconductor substrate and a source/drain region laterally adjacent to the gate structure in the semiconductor substrate. A first dielectric layer is formed overlying the gate structure and the source/drain region, and has a first contact hole over at least one of the gate structure and the source/drain region. A first contact plug is formed of a first conductive material filling the first contact hole, and is electrically coupled to at least one of the gate structure and the source/drain region. A second dielectric layer is formed overlying the first dielectric layer and the first contact plug, and has a second contact hole exposing the first contact plug. A second contact plug is formed of a second conductive material filling the second contact hole, and is electrically coupled to the first contact plug. The second conductive material is different from the first conductive material, and the second conductive material has an electrical resistance lower than that of the first conductive material.
In another aspect, the present invention provides a stacked contact structure for a semiconductor device. The semiconductor device has a gate structure on a semiconductor substrate and source/drain regions laterally adjacent to the gate structure in the semiconductor substrate. A first dielectric layer is formed overlying the gate structure and the source/drain regions, and has a first contact hole over at least one of the gate structure and the source/drain regions. A tungsten plug is formed in the first contact hole and electrically coupled to at least one of the gate structure and the source/drain regions. A second dielectric layer is formed overlying the first dielectric layer and the first contact plug, and has a second contact hole exposing the tungsten plug. A copper plug is formed in the second contact hole and electrically coupled to the tungsten plug. An interconnection structure is formed overlying the second dielectric layer and electrically coupled to the copper plug.
The aforementioned objects, features and advantages of this invention will become apparent by referring to the following detailed description of the preferred embodiments with reference to the accompanying drawings, wherein:
Reference will now be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness of one embodiment may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, apparatus in accordance with the present invention. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Further, when a layer is referred to as being on another layer or “on” a substrate, it may be directly on the other layer or on the substrate, or intervening layers may also be present.
Herein, cross-sectional diagrams of
In
A light ion implantation process is then performed to form two lightly doped regions 16 respectively at each side of the gate structure in the substrate 10. Next, a dielectric spacer 18 is formed on each sidewall of the gate structure. The dielectric spacer 18 may be formed of oxide, nitride, oxynitride, or combinations thereof. A heavy ion implantation process is then performed to form a heavily doped region 20 on the lightly doped region 16. Thus, two source/drain regions 20 with a lightly doped drain (LDD) structure 16 are formed in the substrate 10 at each side of the gate structure. Whether a MOS transistor is nMOS or pMOS will depend on the conductivity type of the substrate 10 and the source/drain regions 20. For pMOS transistors, the LDD structure and the source/drain regions will be p-type and the substrate will be n-type. For nMOS transistors, the LDD structure and the source/drain regions will be n-type and the substrate will be p-type.
In order to reduce sheet resistance, a silicide layer 22 is formed on the source/drain regions 20 and the gate electrode layer 14. The silicide layer 22 is a metal silicide layer comprising metals such as titanium, cobalt, nickel, palladium, platinum, erbium, and the like.
A contact etch stop layer (CESL) 24 for controlling the end point during subsequent contact hole formation is deposited on the above-described MOS transistor completed on the substrate 10. The CESL 24 may be formed of silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof. A first inter-layered dielectric (ILD) layer 26 is formed on the CESL 24 so as to isolate the MOS transistor from a subsequent formation of an interconnect structure. The first ILD layer 26 may be a silicon oxide containing layer formed of doped or undoped silicon oxide by a thermal CVD process or high-density plasma (HDP) process, e.g., undoped silicate glass (USG), phosphorous doped silicate glass (PSG) or borophosphosilicate glass (BPSG). Alternatively, the first ILD layer 26 may be formed of doped or P-doped spin-on-glass (SOG), PTEOS, or BPTEOS. Following planarization, e.g., chemical mechanical planarization (CMP) on the first ILD layer 26, a dielectric anti-reflective coating (DARC) or/and a bottom anti-reflectance coating (BARC) and a lithographically patterned photoresist layer are provided, which are omitted in the Figures for simplicity and clarity. A dry etching process is then carried out to form a first contact hole 28 that passes though the first ILD layer 26 and the CESL 24 so as to expose the silicide layer 22 positioned over the source/drain region 20. Then the patterned photoresist and the BARC layer are stripped. The depth of the first contact hole 28 is less than 1.5 times the height of the gate structure. As used throughout this disclosure, the term “aspect ratio” refers to a ratio of height to width of a contact hole. It will be appreciated that the first contact hole 28 may also be formed to expose the silicide layer 22 on the gate electrode layer 14, which is depicted in
In
In
The second ILD layer 34 may be formed through any of a variety of techniques, including, spin coating, CVD, and future-developed deposition procedures. The second ILD layer 34 may be a single layer or a multi-layered structure (with or without an intermediate etch stop layer). In one embodiment, the second ILD layer 34 is formed of a low-k dielectric layer. As used throughout this disclosure, the term “low-k” is intended to define a dielectric constant of a dielectric material of 4.0 or less. A wide variety of low-k materials may be employed in accordance with embodiments of the present invention, for example, spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymer, organic silica glass, fluorinated silicate glass (FSG), diamond-like carbon, HSQ (hydrogen silsesquioxane) series material, MSQ (methyl silsesquioxane) series material, porous organic series material, polyimides, polysilsesquioxanes, polyarylethers, fluorosilicate glass, and commercial materials such as FLARE from Allied Signal or SiLK from Dow Corning, and other low-k dielectric compositions.
The second contact hole 36 may be a single-damascene opening or a dual-damascene opening formed using a typical lithographic with masking technologies and anisotropic etch operation (e.g. plasma etching or reactive ion etching). In one embodiment, the second contact hole 36 is a single-damascene opening as depicted in
In
Accordingly, a combination of the tungsten plug 30 and the copper plug 40 forms a staked contact structure to provide electrical coupling with the MOS transistor, such as desired one of source/drain regions 20 formed in a substrate 10 and/or the gate structure patterned on the substrate 10. Following formation of the stacked contact structure, an interconnection structure 42 may be deposited and patterned over the second ILD layer 34 to electrically couple the stacked contact structure, as shown in
In the stacked contact structure, the lower-level contact is the tungsten plug 30 formed in a first ILD layer 26, and the higher-level contact is the copper plug 40 formed in a second ILD layer 34. While the contact width continually decreases, the contact height can decrease proportionately to achieve a smaller aspect ratio, thus improving process window (e.g., photolithography and etching process window) in forming the tungsten plug 30 and being advantageously used in 90 nm, 65 nm, 45 nm technology or below. Also, since the copper plug 40 is a low electrical resistance material lower than that of the tungsten plug 30, the effective-contact resistance of the stacked contact structure can be reduced. In addition, the cumulative thickness of the first ILD layer 26 and the second ILD layer 34 can be increased to reduce the capacitance from the interconnection structure 42 to the gate electrode layer 14 and the capacitance from the interconnection structure 42 to the substrate 10, thus improving resistance/capacitance coupling (RC delay).
Although the present invention has been described in its preferred embodiments, it is not intended to limit the invention to the precise embodiments disclosed herein. Those skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.
