Patent Application
20240379657
The present application relates to semiconductor technology, and more particularly to a semiconductor structure including stacked first and second devices wherein at least one of the stacked devices includes a lateral diode.
Stacking of field effect transistors (FETs) is an attractive architecture for future complementary metal oxide semiconductor (CMOS) scaling, and potentially for ultimately scaled technology. By directly stacking FETs one over the other (for example, pFETs over nFETs, nFETs over pFETs, pFETs over pFETs, or nFETs over nFETs) significant area scaling can be achieved.
In stacked device technology, some of the conventional “passive” devices, i.e., non-transistors, will have to be modified. One such passive device is a diode. A diode is two terminal electronic component that conducts current primarily in one direction (asymmetric conductance). A diode has low (ideally zero) resistance in one direction and high (ideally infinite) resistance in the other direction. Semiconductor diodes are a type of diode that includes a crystalline semiconductor material with a p-n junction connected to two terminals. There is a need to provide a diode that can be implemented in stacked technology.
A semiconductor structure is provided including stacked first and second devices wherein at least one of the stacked devices includes a lateral diode. The lateral diode includes a p-doped region as an anode, an n-doped region as a cathode and a semiconductor channel material region sandwiched between the anode and the cathode.
In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes a first device including a first pair of doped regions separated by a first semiconductor channel material region, and a second device located above the first device and including a second pair of doped regions separated by a second semiconductor channel material region. In the present application, the first pair of doped regions are coplanar with each other and the second pair of doped regions are coplanar with each other, and at least one of the first pair of doped regions and the second pair of doped regions includes an n-doped region and a p-doped region. In the present application, the p-doped region functions as an anode of a lateral diode, and the n-doped region functions as a cathode of the lateral diode. The stacked first and second devices are located in a diode region of a semiconductor substrate.
Embodiments include the first pair of doped regions as the n-doped region and the p-doped region of the lateral diode, and the second pair of doped regions are source/drain regions of a transistor; the second pair of doped regions as the n-doped region and the p-doped region of the lateral diode and the first pair of doped regions are source/drain regions of a transistor; and the first pair of doped regions as the n-doped region and the p-doped region of a first lateral diode and the second pair of doped regions as the n-doped region and the p-doped region of a second lateral diode.
In some embodiments of the present application, the semiconductor structure further includes a stacked FET located in a stacked FET device region of the semiconductor substrate; the stacked FET device region is located adjacent to the diode region including the first and second stacked devices. The stacked FET device includes an upper FET stacked above a lower FET. Embodiments include that the lower FET and the upper FET are of a same conductivity type (i.e., both are nFETs or both are pFET), or the lower FET is of different conductivity type than the upper FET (i.e., the lower FET is a pFET and the upper FET is an nFET, or the lower FET is an nFET and the upper FET is a pFET).
The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
As stated above, a semiconductor structure including a first and second stacked devices (see, for example,
The first semiconductor channel material region 14 and the second semiconductor channel material region 24 can be in the form of a layer, fin, nanosheet and/or a nanowire.
In some embodiments and as is illustrated in
In some embodiments and as is illustrated in
In embodiments of the present application, and as is illustrated in
The various components/elements depicted in
The base semiconductor material layer 10 is composed of a first semiconductor material having semiconducting properties. Examples of first semiconductor materials that can be used to provide the base semiconductor material layer 10 include, but are not limited to, silicon (Si), a silicon germanium (SiGe) alloy, a silicon germanium carbide (SiGeC) alloy, germanium (Ge), III/V compound semiconductors or II/VI compound semiconductors. The base semiconductor material layer 10 can be composed of one or more of these first semiconductor materials. In one example, the first semiconductor material that provides the base semiconductor material layer 10 is composed of silicon. In some embodiments, the first semiconductor material layer that provides the base semiconductor material layer 10 can be undoped, i.e., an intrinsic, semiconductor material. In other embodiments, the first semiconductor material that provides the base semiconductor material layer 10 can be doped with an n-type dopant or p-type dopant.
The term “p-type dopant” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, phosphorus and indium. “N-type dopant” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. In one example, first semiconductor material that provides the base semiconductor material layer 10 can typically have a dopant concentration of from 1e15 atoms/cm3 to 1e16 atoms/cm3.
The insulator layer 12 that can be optionally present includes any dielectric material such as, for example, silicon dioxide and/or boron nitride. When present, the insulator layer 12 can have a thickness from 1 nm to 25 nm; although other thicknesses for the insulator layer 12 are contemplated and can be employed in the present application.
The first semiconductor channel material region 14 is composed of a second semiconductor material. The second semiconductor material that provides the first semiconductor channel material region 14 can include one of the semiconductor materials mentioned above for the first semiconductor material that provides the base semiconductor material layer 10. In one example, the second semiconductor material that provides the first semiconductor channel material region 14 is composed of Si or Ge. In some embodiments, the second semiconductor material that provides the first semiconductor channel material region 14 is capable of providing high channel mobility for an nFET. In other embodiments, the second semiconductor material that provides the first semiconductor channel material region 14 is capable of providing high channel mobility for a pFET. The first semiconductor channel material region 14 can have a thickness from 20 nm to 50 nm; although other thicknesses for the first semiconductor channel material region 14 are contemplated and can be employed in the present application.
The first pair of doped regions 16L, 16R can be composed of a compositionally same or a compositionally different third semiconductor material including one of the semiconductor materials mentioned above for the base semiconductor material layer 10. In one example, the first pair of doped regions 16L, 16R are composed of Si. In another example, doped region 16L is composed of Si, while doped region 16R is composed of SiGe. Each of the doped regions that provide the first pair of doped regions 16L, 16R is typically, but not necessarily always, composed of a compositionally same semiconductor material as the first semiconductor material channel region 14.
In some embodiments, the first pair of doped regions 16L, 16R can be of a same first conductivity type. For example, the first conductivity type can be n-type, or p-type. In the case of being of an n-type conductivity, each of the first pair of doped regions 16L, 16R includes an n-type dopant, as defined above. In the case of being of a p-type conductivity, each of the first pair of doped regions 16L, 16R includes a p-type dopant, as defined above. For embodiments in which the first pair of doped regions 16L, 16R are of a same first conductivity type, the dopant (p-type or n-type) concentration of the first pair of doped regions 16L, 16R can be from 1e19 atoms/cm3 to 1e21 atoms/cm3. In embodiments in which the first pair of doped regions 16L, 16R are of a same first conductivity type, the pair of first doped regions 16L, 16R represent source/drain regions of a lower FET.
In some embodiments, the first pair of doped regions 16L, 16R can be of different conductivity types (i.e., one of doped regions of the first pair of doped regions is of a first conductivity type, while the other of the doped regions of the first pair of doped regions is of a second conductivity type that differs from the first conductivity type). In one example, the first conductivity type can be n-type (including an n-type dopant as defined above), and the second conductivity type can be p-type (including a p-type dopant, as defined above). In another example, the first conductivity type can be p-type (including a p-type dopant, as defined above), and the second conductivity type can be n-type (containing an n-type dopant, as defined above). For embodiments in which the first pair of doped regions 16L, 16R are of different conductivity types, the dopant (p-type an n-type) concentration in each of the doped regions that provide the first pair of doped regions 16L, 16R can be from 1e19 atoms/cm3 to 1e21 atoms/cm3. In embodiments, in which the first pair of doped regions 16L, 16R are of different conductivity types, the first doped region that is p-type represents an anode of a lateral diode, while the first doped region that is n-type represents a cathode of the lateral diode. In such an embodiment, current passes laterally through each of the cathode, the first semiconductor channel material region 14 and the anode.
The first gate dielectric material layer 18 is composed of a first gate dielectric material such as, for example, silicon dioxide, or a dielectric material having a dielectric constant greater than 4.0 (such dielectric materials can be referred to as a high-k gate dielectric material). Illustrative examples of high-k gate dielectric materials include metal oxides such as, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and/or lead zinc niobite (Pb(Zn,Nb)O). The high-k gate dielectric material can further include dopants such as lanthanum (La), aluminum (Al) and/or magnesium (Mg). The first gate dielectric material layer 18 can include one or more of the above mentioned first gate dielectric materials. The first gate dielectric material layer 18 can have a thickness from 1 nm to 20 nm; although other thicknesses for the first gate dielectric material layer 18 are contemplated and can be employed in the present application.
The first gate electrode 20 is composed of a first gate electrode material. In some embodiments, the first gate electrode material is composed of an electrically conductive metal-containing material including, but not limited to, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag), or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaCx), titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide, or nickel silicide.
In other embodiments, the first gate electrode material is composed of a first work function metal (WFM). The first WFM can be used to set a threshold voltage of FET_1 to a desired value. In some embodiments, the first WFM can be selected to effectuate an n-type threshold voltage shift. “N-type threshold voltage shift” as used herein means a shift in the effective work-function of the work-function metal-containing material towards a conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials that can effectuate an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations and thereof. In other embodiments, the first WFM can be selected to effectuate a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive. The term “p-type threshold voltage shift” as used herein means a shift in the effective work-function of the work-function metal-containing material towards a valence band of silicon in the silicon containing material. Examples of such materials that can effectuate a p-type threshold voltage shift include, but are not limited to, titanium nitride, and tantalum carbide, hafnium carbide, and combinations thereof.
In some embodiments, the first gate electrode material that provides the first gate electrode 20 is a multilayered stack of an electrically conductive metal-containing material, and a first WFM.
The first gate electrode 20 can have a thickness from 10 nm to 100 nm; although other thicknesses for the first gate electrode 20 are contemplated and can be employed in the present application.
The first gate spacer 22 is composed of any dielectric spacer material including, but not limited to, silicon dioxide, silicon nitride, and/or silicon oxynitride. The first gate spacer 22 is present entirely along the sidewall of the first gate electrode 20.
The dielectric material layer 24 is composed of a dielectric material that can be compositionally the same as, or compositionally different from, the dielectric spacer material that provides the first gate spacer 22. In one example, the dielectric material layer 24 is composed of silicon dioxide, while the first gate spacer 22 is composed of silicon nitride. The dielectric material layer 24 can have a thickness from 20 nm to 50 nm; although other thicknesses for the dielectric material layer 24 are contemplated and can be employed in the present application. The dielectric material layer 24 typically has a topmost surface that is coplanar with at least a topmost surface of the first gate electrode 20. The dielectric material layer 24 is spaced apart from the sidewalls of the first gate electrode 20 by the first gate spacer 22.
The second semiconductor channel material region 26 is composed of a fourth semiconductor material. The fourth semiconductor material that provides the second semiconductor channel material region 26 can include one of the semiconductor materials mentioned above for the first semiconductor material that provides the base semiconductor material layer 10. In one example, the fourth semiconductor material that provides the second semiconductor channel material region 26 is composed of Si or Ge. In some embodiments, the fourth semiconductor material that provides the second semiconductor channel material region 26 can be compositionally the same as the second semiconductor material that provides the first semiconductor channel material region 14. In other embodiments, the fourth semiconductor material that provides the second semiconductor channel material region 26 can be compositionally different from the second semiconductor material that provides the first semiconductor channel material region 14.
In some embodiments, the fifth semiconductor material that provides the second semiconductor channel material region 26 is capable of providing high channel mobility for an nFET. In other embodiments, the fifth semiconductor material that provides second semiconductor channel material region 26 is capable of providing high channel mobility for a pFET. The second semiconductor channel material region 26 can have a thickness from 20 nm to 50 nm; although other thicknesses for the second semiconductor channel material region 26 are contemplated and can be employed in the present application.
The second pair of doped regions 28L, 28R can be composed of a compositionally same or a compositionally different sixth semiconductor material including one of the semiconductor materials mentioned above for the base semiconductor substrate 10. In one example, the second pair of doped regions 28L, 28R are composed of Si. In another example, doped region 28L is composed of Si, while doped region 28R is composed of SiGe. Each of the doped regions that provide the second pair of doped regions 28L, 28R is typically, but not necessarily always, composed of a compositionally same semiconductor material as the second semiconductor material channel region 26.
In some embodiments, the second pair of doped regions 28L, 28R can be of a same first conductivity type. For example, the first conductivity type can be n-type, or p-type. In the case of being of an n-type conductivity, each of the second pair of doped regions 28L, 28R includes an n-type dopant, as defined above. In the case of being of a p-type conductivity, each of the second pair of doped regions 28L, 28R includes a p-type dopant, as defined above. For embodiments in which the second pair of doped regions 28L, 28R are of a same first conductivity type, the dopant (p-type or n-type) concentration of the second pair of doped regions 28L, 28R can be from 1e19 atoms/cm3 to 1e21 atoms/cm3. In embodiments, in which the second pair of doped regions 28L, 28R are of a same first conductivity type, the pair of second pair of doped regions 28L, 28R represent source/drain regions of an upper FET.
In some embodiments, the second pair of doped regions 28L, 28R can be of different conductivity types (i.e., one of the doped regions of the second pair of doped regions is of a first conductivity type, while the another of the doped regions of the second pair of doped regions is of a second conductivity type that differs from the first conductivity type). In one example, the first conductivity type can be n-type (including an n-type dopant as defined above), and the second conductivity type can be p-type (including a p-type dopant, as defined above). In another example, the first conductivity type can be p-type (including a p-type dopant, as defined above), and the second conductivity type can be n-type (containing an n-type dopant, as defined above). For embodiments in which the second pair of doped regions 28L, 28R are of different conductivity types, the dopant (p-type an n-type) concentration in each of the doped regions that provide the second pair of doped regions 28L, 28R can be from 1e19 atoms/cm3 to 1e21 atoms/cm3. In embodiments, in which the second pair of doped regions 28L, 28R are of different conductivity types, the second doped region that is p-type represents an anode of a lateral diode, while the second doped region that is n-type represents a cathode of the lateral diode. In such an embodiment, current passes laterally through each of the cathode, the second semiconductor channel material region 26 and the anode.
The second gate dielectric material layer 30 is composed of a second gate dielectric material. The second gate dielectric material includes at least one of the first gate dielectric materials mentioned above. The second gate dielectric material that provides the second gate dielectric material layer 30 can be compositionally the same as, or compositionally different from, the first gate dielectric material that provide the first gate dielectric material layer 18. The second gate dielectric material layer 30 can have a thickness from 1 nm to 20 nm; although other thicknesses for the second gate dielectric material layer 30 are contemplated and can be employed in the present application.
The second gate electrode 32 is composed of a second gate electrode material. In some embodiments, the second gate electrode material that provides the second gate electrode 32 is composed of one of the electrically conductive metal-containing materials mentioned above for the first gate electrode 20. In other embodiments, the second gate electrode material is composed of a second work function metal (WFM). The second WFM is compositionally different from the first WFM. The second WFM can be used to set a threshold voltage of FET_2 to a desired value. In some embodiments, the second WFM can be selected to effectuate an n-type threshold voltage shift, as defined above. Examples of such materials that can effectuate an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations and thereof. In other embodiments, the second WFM can be selected to effectuate a p-type threshold voltage shift, as defined above. Examples of such materials that can effectuate a p-type threshold voltage shift include, but are not limited to, titanium nitride, and tantalum carbide, hafnium carbide, and combinations thereof. In yet other embodiments, the second gate electrode material that provides the second gate electrode 32 is composed of both an electrically conductive metal-containing material and a second WFM. The second gate electrode 32 can have a thickness from 10 nm to 100 nm; although other thicknesses for the second gate electrode 32 are contemplated and can be employed in the present application.
The second gate spacer 34 is composed of any dielectric spacer material including, but not limited to, silicon dioxide, silicon nitride, and/or silicon oxynitride. The second gate spacer 34 is present entirely along the sidewall of the second gate electrode 32.
In some embodiments of the present application, the first pair of doped regions 16L, 16R of the first device are the n-doped region and the p-doped region of the lateral diode, and the second pair of doped regions 28L, 28R of the second device are source/drain regions of a transistor. In such embodiment, the transistor can be a functional FET or a non-functional FET; in this embodiment the FET can be referred to as a second FET, FET_2. Non-functional FETs typically are left unconnected in the present application. FET_2 can be an nFET or a pFET.
In other embodiments of the present application, the second pair of doped regions 28L, 28R of the second device are the n-doped region and the p-doped region of the lateral diode and the first pair of doped regions 16L, 16R of the first device are source/drain regions of a transistor. In such embodiment, the transistor can be a functional FET or a non-functional FET in this embodiment the FET can be referred to as a first FET, FET_1. Again, non-functional FETs typically are left unconnected in the present application. FET_1 can be an nFET or a pFET.
In yet other embodiments of the present application, the first pair of doped regions 16L. 16R as the n-doped region and the p-doped region of a first lateral diode and the second pair of doped regions 28L, 28R of the second device are the n-doped region and the p-doped region of a second lateral diode. In this embodiment, each of the n-doped regions are located on a first side of the first device and the second device, and each of the p-doped regions are located on a second side of the first device and the second device wherein the second side is opposite the first side. In this embodiment, a parallel pair of first and second lateral diodes can be provided. Also, and in this embodiment, the second gate structure (i.e., the second gate dielectric material layer 30 and the second gate electrode 32) and the second gate spacer 34 can be present in the structure, or the second gate structure (i.e., the second gate dielectric material layer 30 and the second gate electrode 32) and the second gate spacer 34 can be omitted from the structure.
It is noted that the width of the first semiconductor channel material region 16 can be the same as, or different from, the width of the second semiconductor channel material region 26.
In some embodiments of the present application and as is illustrated in
In some embodiments, the third conductivity type source/drain regions 38 are of the same conductivity type as the fourth conductivity type source/drain regions 50, i.e., both are n-type or both are p-type. In such an embodiment, FET_3 and FET_4 are of the same conductivity. In other embodiments, the third conductivity type source/drain regions 38 are a different conductivity type than the fourth conductivity type source/drain regions 50.
FET_3 of the stacked FET illustrated in
As is further illustrated in
As is further illustrated in
The various components/elements depicted in
The third semiconductor channel material region 36 is composed of a seventh semiconductor material. The seventh semiconductor material that provides the third semiconductor channel material region 36 can include one of the semiconductor materials mentioned above for the first semiconductor material that provides the base semiconductor material layer 10. In some embodiments, the seventh semiconductor material layer that provides the third semiconductor channel material region 36 is compositionally the same as the second semiconductor material layer that provides the first semiconductor channel material region 14. In other embodiments, the seventh semiconductor material layer that provides the third semiconductor channel material region 36 is compositionally different than the second semiconductor material layer that provides the first semiconductor channel material region 14. In some embodiments, the seventh semiconductor material that provides the third semiconductor channel material region 36 is capable of providing high channel mobility for an nFET. In other embodiments, the seventh semiconductor material that provides the third semiconductor channel material region 36 is capable of providing high channel mobility for a pFET. The third semiconductor channel material region 36 can have a thickness in the thickness range mentioned above for the first semiconductor channel material region 14.
The third conductivity-type source/drain regions 38 are composed of an eighth semiconductor material that can be compositionally the same as, or compositionally different from, the seventh semiconductor material that provides the third semiconductor channel material region 36. Typically, the eighth semiconductor material that provides the third conductivity-type source/drain regions 38 and the seventh semiconductor material that provides the third semiconductor channel material region 36 are compositionally the same. The eighth semiconductor material layer that provides the third conductivity-type source/drain regions 38 can be compositionally the same as, or compositionally different from, the third semiconductor material that provides the first pair of doped regions 16L, 16R.
The eighth semiconductor material that provides the third conductivity-type source/drain regions 38 are doped with either a p-type dopant, as defined above, or an n-type dopant as defined above. The dopant concentration in the eighth semiconductor material that provides the third conductivity-type source/drain regions 38 is within the dopant range mentioned above, i.e., from 1e19 atoms/cm3 to 1e21 atoms/cm3. The thickness of the third conductivity-type source/drain regions 38 is typically within the range of the thickness of the third semiconductor channel material region 36. The third conductivity-type source/drain regions 38 typically, but not necessarily always, have a same thickness as the third semiconductor channel material region 36 such that a topmost surface of each of the third conductivity-type source/drain regions 38 is coplanar with a topmost surface of the third semiconductor channel material region 36.
The third gate dielectric material layer 40 is composed of a third gate dielectric material. The third gate dielectric material includes one of the first gate dielectric materials mentioned above for the first gate dielectric material layer 18. The third gate dielectric material that provides the third gate dielectric material layer 40 can be compositionally the same as, or compositionally different from, the first gate dielectric material that provides the first gate dielectric material layer 18. The third gate dielectric material layer 40 can have a thickness within the thickness range mentioned above for the first gate dielectric material layer 18.
The third gate electrode 42 is composed of a third gate electrode material. The third gate electrode material includes one of the first gate electrode materials, i.e., electrically conductive metal-containing materials and/or WFMs, mentioned above for first gate electrode material that provides the first gate electrode 20. The third gate electrode material that provides the third gate electrode 42 can be compositionally the same as, or compositionally different from, the first gate electrode material that provides the first gate electrode 20. The third gate electrode 42 can have a thickness within the thickness range mentioned above for the first gate electrode 20.
The third gate spacer 44 is composed of any dielectric spacer material including, but not limited to, silicon dioxide, silicon nitride, and/or silicon oxynitride. The third gate spacer 44 is present entirely along the sidewall of the third gate electrode 42.
In the stacked FET device region illustrated in
The fourth semiconductor channel material region 48 is composed of a ninth semiconductor material. The ninth semiconductor material that provides the fourth semiconductor channel material region 48 can include one of the semiconductor materials mentioned above for the first semiconductor material that provides the base semiconductor material layer 10. In some embodiments, the ninth semiconductor material that provides the fourth semiconductor channel material region 48 can be compositionally the same as the seventh semiconductor material that provides third semiconductor channel material region 36. In other embodiments, the ninth semiconductor material that provides the fourth semiconductor channel material region 48 can be compositionally different from the seventh semiconductor material that provides the third semiconductor channel material region 36. In some embodiments, the ninth semiconductor material that provides the fourth semiconductor channel material region 48 can be compositionally the same as, or compositionally different from the fourth semiconductor material that provides second semiconductor channel material region 26. In some embodiments, the ninth semiconductor material that provides the fourth semiconductor channel material region 48 is capable of providing high channel mobility for an nFET. In other embodiments, the ninth semiconductor material that provides fourth semiconductor channel material region 48 is capable of providing high channel mobility for a pFET. The fourth semiconductor channel material region 48 can have a thickness from 20 nm to 50 nm; although other thicknesses for the fourth semiconductor channel material region 48 are contemplated and can be employed in the present application.
The fourth conductivity-type source/drain regions 50 are composed of a tenth semiconductor material that can be compositionally the same as, or compositionally different from, the ninth semiconductor material that provides the fourth semiconductor channel material region 48. The tenth semiconductor material that provides the fourth conductivity-type source/drain regions 50 are doped with either a p-type dopant, as defined above, or an n-type dopant as defined above. The conductivity type of the dopant that is present in the fourth conductivity-type source/drain regions 50 can be the same as, or opposite from, from the conductivity type of dopant that is present in the third conductivity type source/drain regions 36. The fourth conductivity-type source/drain regions 50 can have a dopant (p-type or n-type) concentration of from 1e19 atoms/cm3 to 1e21 atoms/cm3. The fourth conductivity-type source/drain regions 50 have a thickness that is typically within the range of the thickness of the fourth semiconductor channel material region 48. The fourth conductivity-type source/drain regions 50 typically, but not necessarily always, have a same thickness as the fourth semiconductor channel material region 48 such that a topmost surface of each of the fourth conductivity-type source/drain regions 50 is coplanar with a topmost surface of the fourth semiconductor channel material layer 40.
The fourth gate dielectric material layer 52 is composed of a fourth gate dielectric material. The fourth gate dielectric material includes at least one of the first gate dielectric materials mentioned above. The fourth gate dielectric material layer that provides the fourth gate dielectric material layer 52 can be compositionally the same as, or compositionally different from, the third and/or second gate dielectric materials mentioned above. The fourth gate dielectric material layer 52 can have a thickness from 1 nm to 20 nm; although other thicknesses for the fourth gate dielectric material layer 52 are contemplated and can be employed in the present application.
The fourth gate electrode 54 is composed of a fourth gate electrode material. The fourth gate electrode material that provides the fourth gate electrode 54 includes one of the first gate electrode materials, i.e., electrically conductive metal-containing materials and/or WFMs, mentioned above for first gate electrode material that provides the first gate electrode 20. The fourth gate electrode material that provides the fourth gate electrode 54 can be compositionally the same as, or compositionally different from, the third gate electrode material that provides the provides the third gate electrode 20 and/or the second gate electrode material that provides the second gate electrode 32. The fourth gate electrode 54 can have a thickness within the thickness range mentioned above for the first gate electrode 20.
The fourth gate spacer 56 is composed of any dielectric spacer material including, but not limited to, silicon dioxide, silicon nitride, and/or silicon oxynitride. The fourth gate spacer 56 is present entirely along the sidewall of the fourth gate electrode 42.
It is noted that the channel width of FET_3 and FET_4 can be the same as is illustrated in
Although the present application describes and illustrates planar FETs for FET_1, FET_2. FET_3 and FET_4, the present application contemplates embodiments in which at least one of FET_1, FET_2, FET_3 and FET_4 is a non-planar device such as, for example, a semiconductor fin-containing FET, a nanowire-containing FET, and/or a nanosheet-containing FET.
The stacked first and second devices and the stacked FET shown in
While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
The present application is related to U.S. application Ser. No. ______ (Attorney Docket No. P202204229US01), filed concurrently on the same date as the present application, the entire content of this related application is incorporated herein by reference.
