This application relates generally to integrated circuits, and more particularly to structures and manufacturing methods of and semiconductor fins and Fin field effect transistors (FinFETs).
With the increasing down-scaling of integrated circuits and increasingly demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFET) were thus developed.
In the formation of STI regions 120, a wet etch is used to recess the top surfaces of STI regions 120 to form fins 100. It is observed that with the wet etching, the center portions of the surfaces of STI regions 120 are lower than the portions of surfaces close to fins 100. The top surfaces of STI regions 120 are referred to as having a smiling profile.
It is realized that the parasitic capacitance (shown as capacitors 110) is generated between gate 108 and semiconductor strips 122, wherein STI regions 120 act as the insulator of parasitic capacitor 110. The parasitic capacitance adversely affects the performance of the respective integrated circuit, and needs to be reduced.
In accordance with one aspect of the embodiment, a method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.
Other embodiments are also disclosed.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the disclosure.
A novel method for forming shallow trench isolation (STI) regions and a fin field-effect transistor (FinFET) is provided. The intermediate stages in the manufacturing of an embodiment are illustrated. The variations of the embodiment are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Referring to
Pad layer 22 and mask layer 24 may be formed on semiconductor substrate 20. Pad layer 22 may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. Pad layer 22 may act as an adhesion layer between semiconductor substrate 20 and mask layer 24. Pad layer 22 may also act as an etch stop layer for etching mask layer 24. In an embodiment, mask layer 24 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). In other embodiments, mask layer 24 is formed by thermal nitridation of silicon, plasma enhanced chemical vapor deposition (PECVD), or plasma anodic nitridation. Mask layer 24 is used as a hard mask during subsequent photolithography processes. Photo resist 26 is formed on mask layer 24 and is then patterned, forming openings 28 in photo resist 26.
Referring to
Depth D of trenches 32 may be between about 2100 Å and about 2500 Å, while width W is between about 300 Å and about 1500 Å. In an exemplary embodiment, the aspect ratio (D/W) of trenches 32 is greater than about 7.0. In other exemplary embodiments, the aspect ratio may even be greater than about 8.0, although they may also be lower than about 7.0, or between 7.0 and 8.0. One skilled in the art will realize, however, that the dimensions and values recited throughout the descriptions are merely examples, and may be changed to suit different scales of integrated circuits.
Liner oxide 34 is then formed in trenches 32, as is shown in
Referring to
A chemical mechanical polish is then performed, followed by the removal of mask layer 24 and pad layer 22. The resulting structure is shown in
Next, the structure shown in
The top surfaces of STI regions 40 in
In order to form STI regions 40 having the profiles as shown in
Simulations were performed to study the effects of the profiles of STI regions 240.
The embodiments have several advantageous features. By forming flat STI regions or divot STI regions underlying gate electrodes of FinFETs, the parasitic gate capacitance of the FinFETs may be reduced, and the speed of the respective FinFETs may be increased.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
This application claims the benefit of U.S. Provisional Application No. 61/255,365 filed on Oct. 27, 2009, entitled “STI Shape Near Fin Bottom of Si Fin in Bulk FinFET,” which application is hereby incorporated herein by reference. This application relates to the following U.S. patent application: Application Ser. No. 61/160,635, filed Mar. 16, 2009, and entitled “Hybrid STI Gap-Filling Approach,” which application is hereby incorporated herein by reference.
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