This application is a continuation of U.S. patent application Ser. No. 08/423,792, filed on Apr. 25, 1995 now abandoned.
Number | Name | Date | Kind |
---|---|---|---|
RE33629 | Palmer et al. | Jul 1991 | |
4338675 | Palmer et al. | Jul 1982 | |
4367524 | Budde et al. | Jan 1983 | |
4484259 | Palmer et al. | Nov 1984 | |
4777613 | Shahan et al. | Feb 1988 | |
4928259 | Galbi et al. | May 1990 | |
5010508 | Sit et al. | Apr 1991 | |
5027308 | Sit et al. | Jun 1991 | |
5036482 | Saini | Jul 1991 | |
5157777 | Lai et al. | Oct 1992 | |
5195051 | Palaniswami | Mar 1993 | |
5204828 | Kohn | Apr 1993 | |
5235533 | Sweedler | Aug 1993 | |
5257215 | Poon | Oct 1993 | |
5258943 | Gamez et al. | Nov 1993 | |
5260889 | Palaniswami | Nov 1993 |
Entry |
---|
Double-Precision Floating Point Processor-Users Manual 1988/9, Advanced Micro Devices, Inc., Chapter 3 (pp. 3-1 to 3-32), Sunnyvale California, Copyright 1988. |
Neil H.E. Weste, et al., Principals of CMOS VLSI Design, A Systems Perspective, Addison-Wesley Publishing Company, 1985, pp310-338. |
Mckinney et al., A Multiple-access Pipeline Architecture of Digital Signal Processing:, IEEE, pp 283-290, Mar. 1988. |
Lange, et al., "An Optima Floating-Point Pipeline CMOS CORDIC Processor"IEEE, pp 2043-2047, 1988. |
Snyder, et al., "100 MegaFlop Double Precision IEEE Multiplier Block for Advanced Bipolar VLSI", IEEE, pp. 17.4.1-17.4.3, 1988. |
Number | Date | Country | |
---|---|---|---|
Parent | 423792 | Apr 1995 |