Patent Application
20140264444
The present disclosure relates to semiconductor devices, and particularly to a field effect transistor including an embedded source region and an embedded drain region that enhances transfer of stress to a channel region, and methods of manufacturing the same.
Formation of an embedded source region and an embedded drain region can be performed by recessing semiconductor material regions that are laterally bounded by shallow trench isolation structures and outer sidewalls of gate spacers. In this case, trenches recessed into the active region of the semiconductor material are formed such that dielectric surfaces of shallow trench isolation structures are physically exposed within the trenches. Selective epitaxy can be employed to grow a semiconductor material only from semiconductor surfaces while suppressing deposition of the semiconductor material on dielectric surfaces, thereby forming the embedded source region and the embedded drain region.
However, due to the tendency of the semiconductor material to form surfaces that do not contact dielectric materials, the embedded source region and the embedded drain region are formed with facets such that the surfaces of the embedded source region and the embedded drain region do not contact the dielectric surfaces of the shallow trench isolation structures. The embedded source region and the embedded drain region do not make physical contact with the surfaces of the shallow trench isolation structures. A predominant portion of the lateral stress generated by the lattice mismatch of the semiconductor material in the embedded source region and the embedded drain region and the underlying semiconductor material is dissipated by a volume change accompanying distortion of the faceted surfaces of the embedded source region and the embedded drain region. As a result, the lateral stress applied to the channel region of a field effect transistor is significantly reduced due to lack of physical contact between the embedded source/drain region and the shallow trench isolation structures.
Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation (STI) spacer is formed on sidewalls of the shallow trench isolation structure around the periphery of the active area. After formation of a gate stack structure and a gate spacer, trenches are formed such that sidewalls of the trenches are vertically coincident with sidewalls of the gate spacer and the STI spacer. Epitaxial semiconductor material can be deposited into the trenches by selective epitaxy to form an embedded source region and an embedded drain region. Because all surfaces of the trenches are semiconductor surfaces, the entire trenches can be filled with the epitaxial semiconductor material, thereby enabling lateral confinement of stress within a channel region of a field effect transistor.
According to an aspect of the present disclosure, a semiconductor structure includes a semiconductor material layer, which contains a first semiconductor material and embeds a shallow trench isolation structure that laterally surrounds an active region of the semiconductor material layer. A planar top surface of the active area is recessed below a top surface of the shallow trench isolation structure. The semiconductor structure further includes a shallow trench isolation spacer, which includes a dielectric material, overlies a periphery of the active region, and contacts sidewalls of the shallow trench isolation structure. A gate stack structure includes a vertical stack of a gate dielectric and a gate electrode, straddling the active region, contacts a top surface of the active region and overlies the shallow trench isolation spacer. An embedded semiconductor material region includes a second semiconductor material that is different from the first semiconductor material and embedded in the active region of the semiconductor material layer. An outer sidewall of the gate spacer is vertically coincident with an upper portion of an interface between the embedded semiconductor material region and a surface of the first semiconductor material.
According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. A shallow trench isolation structure is formed in a semiconductor material layer. The shallow trench isolation structure laterally surrounds an active region of the semiconductor material layer. A top surface of the active region is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation spacer is formed, which includes a dielectric material, overlies a periphery of the active region, and contacts sidewalls of the shallow trench isolation structure. A gate stack structure is formed, which includes a vertical stack of a gate dielectric and a gate electrode and straddles the active region. A gate spacer laterally surrounding the gate stack structure is formed. A trench is formed within the active region by etching a physically exposed portion of the active region. A sidewall of the trench is vertically coincident with an outer sidewall of the gate spacer. An embedded semiconductor material region within the active region is formed. The embedded semiconductor material region includes a second semiconductor material that is different from the first semiconductor material.
As stated above, the present disclosure relates to a field effect transistor including an embedded source region and an embedded drain region that enhances transfer of stress to a channel region, and methods of manufacturing the same, which are now described in detail with accompanying figures. It is noted that like reference numerals refer to like elements across different embodiments. The drawings are not necessarily drawn to scale.
Referring to
A top portion of the substrate 8 includes a semiconductor material layer 10, which includes a first semiconductor material. The first semiconductor material can be, for example, single crystalline silicon, single crystalline germanium, a single crystalline alloy of at least two of silicon, germanium, and carbon, a single crystalline compound semiconductor material, a polycrystalline elemental semiconductor material, a polycrystalline alloy of at least two of silicon, germanium, and carbon, a polycrystalline compound semiconductor material, or an amorphous semiconductor material. In one embodiment, the first semiconductor material is single crystalline.
A shallow trench isolation structure 20 is formed in an upper portion of the semiconductor material layer 10, for example, by formation of a shallow trench that laterally surrounds a region of the semiconductor material layer 10, which is herein referred to as an “active region” in which a semiconductor device such as a field effect transistor can be formed. The shallow trench is filled with a dielectric material such as silicon oxide, silicon nitride, and/or silicon oxynitride to form the shallow trench isolation structure 20. The active region is a portion of the semiconductor material layer 10 that is laterally surrounded by the shallow trench isolation structure 20. In one embodiment, the area of the active region can be rectangular.
The shallow trench isolation structure is formed such that a planar top surface of the semiconductor material layer 10 is recessed below a top surface of the shallow trench isolation structure 20. In one embodiment, the shallow trench isolation structure 10 can be formed by depositing at least one pad layer (not shown) over the semiconductor material layer 10 such that the top surface of the shallow trench isolation structure 20 is above the interface between the semiconductor material layer 10, and by subsequently removing the at least one pad layer selective to the shallow trench isolation structure 20. The at least one pad layer may include a dielectric material different from the dielectric material of the shallow trench isolation structure. Alternately or additionally, the top surface of the semiconductor material layer 10 may be recessed relative to the top surface of the shallow trench isolation structure 20 by an etch that is selective to the shallow trench isolation structure 20. The etch can be an isotropic etch such as a wet etch, or can be an anisotropic etch such as a reactive ion etch. The recess depth rd, which is the vertical distance between the top surface of the semiconductor material layer 10 and a horizontal plane including the top surface of the shallow trench isolation structure 20, can be from 3 nm to 100 nm, although lesser and greater thicknesses can also be employed.
Referring to
The anisotropic etch of the conformal dielectric material layer can be performed, for example, by a reactive ion etch. In one embodiment, the reactive ion etch can be selective to the semiconductor material of the semiconductor material layer 10. A remaining vertical portion of the conformal dielectric material layer after the anisotropic etch constitutes the shallow trench isolation spacer 22. The shallow trench isolation spacer 22 overlies a periphery of the active region, and contacting sidewalls of the shallow trench isolation structure 20. The shallow trench isolation spacer 22 is a single contiguous dielectric material structure. In one embodiment, the shallow trench isolation spacer 22 can be a ring-shaped structure, i.e., can have a single hole therein. As used herein, a structure is “ring-shaped” if the structure is “topologically homeomorphic” to a torus, i.e., can be continuously stretched without creating or destroying a hole into a torus. In one embodiment, the shallow trench isolation spacer 22 can have the same base width throughout the entirety thereof. As used herein, a “base width” refers to the width of a base, i.e., a bottommost surface.
Referring to
The gate stack structure (50, 52, 58) can be formed, for example, by formation of a stack of a gate dielectric layer including a dielectric material, a gate electrode layer including at least one conductive material, and a gate cap dielectric layer including a dielectric material, and by subsequent patterning of the stack of the gate dielectric layer, the gate electrode layer, and the gate cap dielectric layer by a combination of lithographic methods that form a patterned photoresist layer and at least one anisotropic etch that etches physically exposed portions of the stack employing the patterned photoresist layer as an etch mask.
An interface between the gate dielectric 50 and the first semiconductor material of the active region is located below a horizontal plane including an interface between the gate dielectric 50 and the shallow trench isolation structure 20. The gate stack structure (50, 52, 58) is formed on a surface of the shallow trench isolation spacer 22.
A gate spacer 62 can be formed on the sidewalls of the gate stack structures (50, 52, 58). Specifically, the gate spacer 62 can be formed by a conformal deposition of a dielectric material layer and a subsequent anisotropic etch (such as a reactive ion etch) that removes horizontal portions of the deposited dielectric material layer. The remaining vertical portions of the dielectric material layer constitute the gate spacer 62 which laterally surround each of the gate stack structure (50, 52, 58). The gate spacer 62 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The thickness of the gate spacers 62 can be in a range from 5 nm to 100 nm, although lesser and greater thicknesses can also be employed.
Referring to
In one embodiment, two trenches can be formed in the active region such that a first trench 31 is formed on one side of the combination of the gate stack structure (50, 52, 58) and the gate spacer 62, and a second trench 39 is formed on the opposite side of the combination of the gate stack structure (50, 52, 58) and the gate spacer 62. A source region can be subsequently formed within the first trench 31, and therefore, the first trench 31 is herein referred to as a source-side trench. A drain region can be subsequently formed within the second trench 39, and therefore, the second trench 39 is herein referred to as a drain-side trench.
Vertical surfaces of the shallow trench isolation structure that are along the widthwise direction of the gate stack structure (50, 52, 58) can be physically exposed in each of the first and second trenches (31, 39). All sidewalls of the first and second trenches (31, 39) can be substantially vertical.
In one embodiment, an outer sidewall of the gate spacer 62 can be vertically coincident with a sidewall of the first trench 31, and another outer sidewall of the gate spacer 62 can be vertically coincident with a sidewall of the second trench 39. As used herein, a first surface is vertically coincident with a second surface if there exists a vertical plane from which the first surface and the second surface do not deviate by more than the sum of the atomic level roughness of the first surface and the atomic level roughness of the second surface.
Referring to
The second semiconductor material in the embedded semiconductor material regions (72, 78) can be doped with electrical dopants, which can be p-type dopants or n-type dopants. If the first semiconductor material has a doping of the first conductivity type, the second semiconductor material can have a doping of the second conductivity type, which is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The doping of the second semiconductor material can be performed, for example, by in-situ doping during the selective epitaxy process.
If the first semiconductor material is single crystalline, the second semiconductor material can be single crystalline and can be epitaxially aligned to the first semiconductor material. In one embodiment, the first semiconductor material can be single crystalline silicon or a single crystalline silicon-germanium alloy, and the second semiconductor material can be a boron-doped single crystalline silicon germanium alloy or an n-doped and carbon-doped single crystalline silicon.
Within the exemplary semiconductor structure illustrated in
The embedded source region 72 is embedded within the active region, and is laterally spaced from the embedded drain region 78. An outer sidewall of the gate spacer 62, which is a dielectric material structure, is vertically coincident with an upper portion of an interface between the embedded source region 72 and a surface of the first semiconductor material of the active region, which is a surface of a body region of the field effect transistor. The embedded drain region 78 is embedded within the active region, and is laterally spaced from the embedded source region 72. Another outer sidewall of the gate spacer 62 is vertically coincident with an upper portion of an interface between the embedded drain region 78 and another surface of the first semiconductor material of the active region, which is another surface of a body region of the field effect transistor. The gate dielectric 50 is a gate dielectric of the field effect transistor, and the gate electrode 52 is a gate electrode of the field effect transistor.
In one embodiment, the sidewalls of the embedded semiconductor material regions (72, 78) can be faceted so that the dielectric surfaces of the shallow trench isolation structure 20 do not contact any surface of the embedded semiconductor material region (72, 78). In one embodiment, a portion of each embedded semiconductor material region (72, 78) can protrude above a horizontal plane including the top surface of the active region, i.e., the horizontal plane including the bottom surface of the gate dielectric 50, and can include at least one faceted crystallographic surface.
In one embodiment, peripheries of faceted crystallographic surfaces may be coincident with a boundary between a dielectric material and the second semiconductor material. For example, peripheries of faceted crystallographic surfaces of the embedded semiconductor material regions (72, 78) can coincide with the edges at which outer sidewalls of the gate spacer 62 adjoins the active region.
Referring to
In one embodiment, the contact-level dielectric layer 90 can extend below the horizontal plane of the interface between the gate dielectric 50 and the semiconductor material layer 10, and can overlie a portion of each embedded semiconductor material region (72, 78). In one embodiment, the contact-level dielectric layer 90 can physically contact a surface of each embedded semiconductor material region (72, 78) that is not subjected to metal semiconductor alloy formation.
The various exemplary semiconductor structure of the present disclosure provide a physical and areal contact for all sidewalls of the embedded semiconductor material regions (72, 78) with a sidewall of the active region of the semiconductor material layer 10 by laterally offsetting the embedded semiconductor material regions (72, 78) from the shallow trench isolation structure with the shallow trench isolation spacer 22. Thus, the stress generated by the lattice mismatch of the first and second semiconductor materials is not dissipated by volume change in the cavities, but is effectively contained by the shallow trench isolation structure 20 and the peripheral portions of the active region, and is transmitted to the channel region of the field effect transistor between the embedded semiconductor material regions (72, 78), thereby enhancing the on-current of the field effect transistor.
While the present disclosure has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present disclosure. Each of the various embodiments of the present disclosure can be implemented alone, or in combination with any other embodiments of the present disclosure unless expressly disclosed otherwise or otherwise impossible as would be known to one of ordinary skill in the art. It is therefore intended that the present disclosure not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
